JPS6113635A - 集積回路の製造方法 - Google Patents

集積回路の製造方法

Info

Publication number
JPS6113635A
JPS6113635A JP59133724A JP13372484A JPS6113635A JP S6113635 A JPS6113635 A JP S6113635A JP 59133724 A JP59133724 A JP 59133724A JP 13372484 A JP13372484 A JP 13372484A JP S6113635 A JPS6113635 A JP S6113635A
Authority
JP
Japan
Prior art keywords
chip
integrated circuit
metal wire
shoulder
parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59133724A
Other languages
English (en)
Inventor
Kenichi Ono
大野　兼一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59133724A priority Critical patent/JPS6113635A/ja
Publication of JPS6113635A publication Critical patent/JPS6113635A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Dicing (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （技術分野） 本発明は集積回路の製造方法に関し、とくにシリコン等
半導体を基板とした集積回路の分離境界部分の製造方法
に関するものである。
（従来技術） シリコン等半導体を基板としたトランジスタ・ダイオー
ド等を含む集積回路の製造工程に於いて。
円形のシリコンウェハー上に多数の集積回路用チップを
形成するのが好適であるが組立工程では個々の集積回路
チップを取り扱うために、シリコンウェハーから個々の
集積回路チップに分割する作業が必要である。
一般的にはチップとチップの境界部分にダイヤモンドポ
イント或いはレーザービーム等を当てた後シリコンウェ
ハーの襞間性を利用して分割するのが管通である。
第１図は従来製法によるチップの分割から組立工程例の
一部を示す。第１図（ａ）はシリコンウェハ−１に集積
回路に必要なパター／が形成され、シリコンチップ表面
の保護層となる絶縁＠２．外部引き出しのための電極と
なるポンディングパッド３．チップ分割のための目安に
なると伴に分割作業を容易にするために絶縁層２を除去
した溝４が形成された状態を示す。第１図（ｂ）はダイ
ヤモンドポイント又はレーザービーム等により襞間の発
端となるべくつけたスクラッチ跡５がつけられた状態を
示す。第１図（Ｃ）はスクラッチ跡５から襞間して各チ
ップが分割された状態を示す。第１図（ｄ）は組立工程
の一例の一部を示している。分割された集積回路チップ
６をベースリボン７の上に搭載固定し、金又はアルミニ
ウム等の金属細線８で所定の電極間を接続した状態を示
している。
ところがチップ肩部９はその表面が二酸化珪素等の絶縁
物で覆われていすシリコンそのものが露出しているため
、金属細線８の接続の具合によっては、金属細線８とチ
ップ肩部９が接触して電気特性上の不都合を生ずる可能
性があるために、金属細線８の接続作業の後に充分に金
属細線８とチップ肩部９が離れていることを確認する作
業が必要であり、又これらが充分に離れていなければ、
金属細線８がテップ肩部９から光分離れるように金属細
線８を持ち上げて形状を整える等の作業が必要である。
（目的） 本発明の目的はこのような欠点を取り除くことが可能な
集積回路の分離境界部分の製造方法を提供することであ
る。
（構成） 本発明による分離境界部分の製造方法によればチップ肩
部は感光性があり絶縁性を有する樹脂で覆われているこ
とを特徴とする。
（実施例） つぎに本発明を実施例により説明する。第２図は本発明
方法の一実施例に於ける製造方法を説明する断面図であ
る。第２図（ａ）、（ｂ）　　はそれぞれ第１図（ａＬ
（ｂ）　　に示したと同じ内容を示す。第２図（Ｃ）は
シリコンウェハー１の表面を、感光光が１９１絶縁性を
有する樹脂１０で覆った後分離境界部分のスクラッチ溝
５とボンディングパッド３０間が残るようにパターン化
した状態を示し、第２図（ｄ）は第１図（Ｃ）の如く各
チップが分割された状態を示す。第２図（ｅ）は第１図
（ｄ）に示した状態を示している。
以上述べた方法によればチップ肩部が絶縁性を有する樹
脂で覆われているためチップ肩部のシリコンと金属細線
が接触する可能性が極めて小さくなるため、従来例では
必要であった金属細線を接続した後に行なう検査作業が
極めて簡単に行なうるようになるか或いは省略すること
すら可能である。
本発明の一実施例ではスクラッチ跡の部分は樹脂全除去
した状態で説明したが、スクラッチ跡を全く樹脂で覆っ
ても本発明による製造方法の主旨を損なうものではない
。
【図面の簡単な説明】
第１図（ａ）−（ｄ）は従来の分離境界部分の製造方法
を示すための各工程断面図である。 第２図（ａ）−（ｅ）は本発明による分離境界部分の製
造方法を説明するための各工程断面図である。 １・・・・・・シリコ／ウェハー、２・・・・・・絶縁
層、３・・・・・・ボンディングパッド、４−・・・・
・溝、５・・・・・・スクラッチ跡、６・・・・・・集
積回路チップ、７・・・・・・ベースリボン、８・・・
・・・金属細線、９・・・・・・チップ肩部、１０・・
・・・・樹脂。 ５、他

Claims (1)

    【特許請求の範囲】
  1. 　多数の集積回路を同一の半導体ウェハー上に作る集積
    回路の製造工程途中において、個々の集積回路に分離す
    るための溝を作った後、集積回路分離後に集積回路の辺
    部となる分離境界部分を絶縁性の樹脂で覆う工程を有す
    ることを特徴とする集積回路の製造方法。
JP59133724A 1984-06-28 1984-06-28 集積回路の製造方法 Pending JPS6113635A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59133724A JPS6113635A (ja) 1984-06-28 1984-06-28 集積回路の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59133724A JPS6113635A (ja) 1984-06-28 1984-06-28 集積回路の製造方法

Publications (1)

Publication Number Publication Date
JPS6113635A true JPS6113635A (ja) 1986-01-21

Family

ID=15111423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59133724A Pending JPS6113635A (ja) 1984-06-28 1984-06-28 集積回路の製造方法

Country Status (1)

Country Link
JP (1) JPS6113635A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02100340A (ja) * 1988-10-06 1990-04-12 Nec Corp 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02100340A (ja) * 1988-10-06 1990-04-12 Nec Corp 半導体装置の製造方法

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