JPS61134071A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to reduce leakage current by a method wherein an intersection of the edge of the element-isolating region on the surface of a semiconductor substrate with the gate electrode is provided with a conductive layer on which negative voltage to that of the substrate has been impressed. CONSTITUTION:An N-channel MOS transistor is provided with a field oxide film 2 on the surface of the P type Si substrate 1, an element region 3 surrounded by the oxide film 2, N<+> type source and drain regions 8, 9, a gate electrode 6, and a conductive layer 21, on which negative potential to that of the substrate 1 has been impressed, at an intersection of the edge of the oxide film 2 with the gate electrode 6. The presence of the conductive layer 21 on which negative potential to that of the substrate 1 has been impressed enables reduction in leakage current at the edge of the oxide film 2 under the gate electrode 6 and the complete cut of leakage current particularly at the field transistor part. Since the conductive layer 21 is made of polycrystalline Si, an Si oxide film 22 that insulates the conductive layer 21 from the gate electrode 6 can be formed by oxidizing the polycrystalline Si film, and the process is simple.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a MOS transistor with improved edge portions of element isolation regions.

[Technical background of the invention and its problems]

Conventionally, for example, n-channel MOS transistors have been manufactured as shown in FIGS. 6(a) to 6(d), FIGS. 7 and 8.

First, after forming a field oxide film (element isolation region) 2 on the surface of a P-type silicon substrate 1, this field oxidation ff! An oxide film 4 is formed in the element region wt3 surrounded by 2 (as shown in FIG. 6(a)). Next, from directly above the oxide film 4, boron or arsenic is applied for 10 minutes only to the channel portion of the device region 3.
°l ~10a114 ion implantation, ion implantation area 5
(as shown in FIG. 6(b)). Here, injection region 5
is for controlling the threshold voltage of the MOS transistor. Furthermore, after forming a gate electrode 6 made of polycrystalline silicon on the oxide film 4, the oxide film 4 is selectively etched away using the gate electrode 6 as a mask to form a gate oxide 117. Thereafter, using the gate electrode 6 as a mask, n-type impurity ions are implanted into the element region 3.
A heat treatment is performed at about 1000° C. to form N+ type source and drain regions 8.9 (as shown in FIG. 6C). Subsequently, an interlayer insulating film 10 is formed on the entire surface, and after a densification process at around 1000° C., a contact hole 11 is formed in the interlayer insulating film 10, and furthermore, for example, an A2 electrode 12 is formed in this to form an n-channel MOS transistor. (Illustrated in FIG. 6(d), FIG. 7, and FIG. 8). here,
Figure 7 shows the plan view of Figure 6(d), and Figure 8 shows the X of Figure 7.
- A cross-sectional view taken along the X-ray is shown, respectively. In addition to these steps, an interlayer insulating film 1 is also added to prevent the A2 electrode from breaking.
After the gate oxidation modeling step, heat treatment at about 1000° C., ring getter heat treatment, and diffusion of impurities into the gate electrode 6 are performed as a heat treatment at 100° C. as a planarization step.

However, the MOS transistor manufactured as described above has the following drawbacks. That is, the gate oxide film 7
When an electron-hole pair is generated, one of the holes is attracted to the interface between the gate oxide film 7 and the ion implantation layer 1 [5], and a positive fixed charge is formed.

In addition, interface units are generated when holes break bonds between atoms in the gate oxide film 7. Therefore, these fixed charges and interface units increase the leakage current of the transistor. Specifically, as shown in FIGS. 7 and 8, positive charges formed in the gate oxide film 7 or at the interface between the gate oxide film 7 and the semiconductor substrate 1 cause the edges (points) of the field oxide 12 to This is because the area surrounded by 11A) is more likely to be reversed, which makes it easier for current to flow at the edge portion.

In view of this, methods have been considered in which the semiconductor manufacturing process is performed at a lower temperature than before in order to prevent an increase in leakage current, but this method complicates the process and requires ingenuity that was not available in the past. There are many problems.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device that can prevent leakage current.

[Summary of the invention]

The present invention aims to reduce leakage current by providing a conductive layer to which a negative voltage is applied to the substrate at the intersection of the edge of the element isolation region on the surface of the semiconductor substrate and the gate electrode. It is.

(Embodiment of the Invention) Hereinafter, an n-channel MOS transistor according to an embodiment of the present invention will be manufactured in the order of manufacturing steps in FIGS. 1(a) to (d) and FIGS.
This will be explained with reference to FIG. Note that the same members as those of the conventional transistor are given the same reference numerals, and the description thereof will be omitted.

First, field oxidation 1 is applied to the surface of a P-type silicon substrate 1.
After forming oxide 12, it is desired to form oxide 114 in element region 3 (as shown in FIG. 1(a)). Next, we want to form the ion implantation region 5 only in the channel part of the element region 3, as shown in FIG. 1(b).
(Illustrated). Next, after depositing, for example, a polycrystalline silicon layer (not shown) on the entire surface, this is patterned to form a conductive layer made of polycrystalline silicon at the intersection of the edge portion of field @R2 and the portion where the gate electrode is to be formed. 21 was formed.

Here, a negative potential is applied to the conductive layer 21 with respect to the substrate 1. Thereafter, the conductive layer 21 was oxidized to form oxide 1!22 around it. Furthermore, gate oxidation I! is applied to the device region 3! ! After forming the gate electrode 6 through the gate electrode 7, N+ type source and drain regions 8.9 were formed in the element region 3 (as shown in FIG. 1(C), FIG. 2, and FIG. 3). 2 shows a plan view of FIG. 1(d), and FIG. 3 shows a sectional view taken along line X-XI in FIG. 2. Below, the conventional 6th
Similarly to FIG.
1(d) and 4). Here, FIG. 4 is a sectional view taken in a direction perpendicular to the plane of the paper in FIG. 1 (d>).

As shown in FIG. 1(d) and FIG. 4, the n-channel MOS transistor according to the present invention includes a field oxide film 2 provided on the surface of a P-type silicon substrate 1, and the field oxide film 2
N" type source and drain regions 8.9 are provided in the element region 3 surrounded by A2, and a gate electrode 6 is provided, and furthermore, at the intersection of the edge portion of the field oxide film 2 and the gate electrode 6, a The structure includes a conductive layer 21 to which a negative potential is applied.

According to the present invention, due to the presence of the conductive layer 21 to which a negative potential is applied to the substrate 1, the gate voltage ff16
Leakage current at the edge portion of the lower field oxides 1 and 2 is reduced, and in particular, leakage current at the field transistor portion can be completely cut. Therefore, as shown in FIG. 5, variations in threshold value (Vth) can be significantly improved. In addition,
In FIG. 5, (a) shows a characteristic line for a conventional n-channel MOS transistor, and (b) shows a characteristic line for the same according to the present invention.

Further, since the conductive layer 21 is made of polycrystalline silicon, silicon oxide 1 is used to insulate the conductive layer 21 and the gate electrode 6.
1!22 can be formed by oxidizing a polycrystalline silicon layer, and the process is simple.

In the above embodiment, polycrystalline silicon was used as the material for the conductive layer, but the material is not limited to this, and for example, tungsten,
High melting point metals such as molybdenum and titanium, compounds with these high melting point metals, A2, etc. may be used.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a highly reliable semiconductor device that can reduce leakage current and thereby improve variations in threshold voltage.

[Brief explanation of drawings]

1(a) to 1(d) are cross-sectional views showing an n-channel MOS transistor according to an embodiment of the present invention in the order of manufacturing steps, FIG. 2 is a plan view of FIG. 1(d), and FIG. XX in figure 2
FIG. 4 is a cross-sectional view taken along the line, FIG. 4 is a cross-sectional view taken in a direction perpendicular to the plane of the paper in FIG. 6(a) to 6(d) are cross-sectional views showing conventional n-channel MoS transistors in the order of manufacturing steps;
The figure is a plan view of FIG. 6(d), and FIG. 8 is a sectional view taken along the line X--X of FIG. 7. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field oxide film (element isolation region), 3... Element region, 5... Ion implantation region, 6... Gate electrode, 7... Gate Oxide film, 8... N+ type source region, 9... N+ type drain region, 10... Interlayer insulating film, 11... Contact hole, 12... AJ2 electrode, 21... Conductive Layer 22... silicon oxide film. Applicant's agent Patent attorney Takehiko Suzue Figure 1 t! ,2Figure 4Figure N5Figure 116Figure 7

Claims (3)

[Claims] (1) A first conductivity type semiconductor substrate, an element isolation region provided on the surface of this substrate, and a second conductivity type source and drain region provided on the substrate surface surrounded by this element isolation region. , a gate electrode provided on the same substrate via a gate oxide film, and a conductive layer provided at the intersection of the edge portion of the element isolation region and the gate electrode, and to which a negative voltage is applied to the substrate. A semiconductor device comprising: (2) The semiconductor device according to claim 1, wherein the conductive layer is made of polycrystalline silicon, a high melting point metal, or a compound with the high melting point metal. (3) The semiconductor device according to claim 2, wherein the high melting point metal is tungsten, molybdenum, or titanium.