JP3856968B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semi-conductor device Do that from the dual gate such as a CMOS integrated circuit.
[0002]
[Prior art]
As an example of a conventional CMOS integrated circuit, the one shown in FIGS. 7 and 8 is known.
This CMOS integrated circuit is composed of an n-channel MOS transistor 1 and a p-channel MOS transistor 2 as shown in FIG. The n-channel MOS transistor 1 has a source region 4 and a drain region 5 sandwiching a common gate electrode 3. The p-channel MOS transistor 2 has a source region 6 and a drain region 7 sandwiching a gate electrode 3.
[0003]
Further, in this CMOS integrated circuit, as shown in FIG. 8, a P well 12 serving as a region of an n channel MOS transistor 1 and an N well 13 serving as a region of a p channel MOS transistor 2 are formed in a semiconductor substrate 11. Then, an element isolation film 14 is formed in a portion where no element is formed.
[0004]
Polycrystalline silicon layers 16 a and 16 b are formed on the surface of the semiconductor substrate 11 via a gate oxide film 15. An N-type impurity (for example, arsenic) is ion-implanted into the polycrystalline silicon layer 16a on the P-well 12, and a P-type impurity (for example, boron) is ion-implanted into the polycrystalline silicon layer 16b on the N-well 13. A tungsten silicide film 17 is formed on the polycrystalline silicon layers 16a and 16b in order to electrically short-circuit the polycrystalline silicon layer 16a and the polycrystalline silicon layer 16b and lower the gate resistance. Thus, the gate electrode 3 is configured.
[0005]
[Problems to be solved by the invention]
In the CMOS integrated circuit having such a configuration, the gate electrode 3 is composed of the polycrystalline silicon layers 16a and 16b containing different impurities, the tungsten silicide film 17, and the like. Therefore, in the oxidation or diffusion process after the formation of the gate electrode 3, the impurities implanted into the polycrystalline silicon layer 16 b on the N well 13 through the tungsten silicide film 17 and the polycrystalline silicon layer on the P well 12. Impurities implanted into 16a diffuse with each other.
[0006]
As a result, a part of the polycrystalline silicon layer 16b on the N well 13 is changed to N type and a part of the polycrystalline silicon layer 16a on the P well 12 is changed to P type, so that the threshold voltage of the transistor is changed. There was an inconvenience that it fluctuated.
In order to eliminate such inconvenience, it is known that a thin oxide film is interposed between the polycrystalline silicon layers 16a and 16b and the tungsten silicide film 17 as a barrier for preventing mutual diffusion of the impurities. Yes.
[0007]
However, the oxide film becomes a large resistance component and has a new disadvantage that it is disadvantageous for a high-speed switching element.
SUMMARY OF THE INVENTION In view of the above points, on the can be improved to the reliability prevent variation in the threshold voltage of the transistor is to provide a method of manufacturing a semiconductor equipment capable of high-speed operation .
[0009]
[Means for Solving the Problems]
In order to solve the above-described problems and achieve the object of the present invention, the invention according to claim 1 includes a step of forming a first conductivity type region and a second conductivity type region on a silicon substrate, and the first conductivity type. Forming a gate oxide film on each of the mold region and the second conductivity type region, forming a polycrystalline silicon layer on the gate oxide film, and thermally oxidizing the surface of the polycrystalline silicon layer; Removing the oxide film formed by the thermal oxidation; forming a barrier layer made of a silicon oxide film on the polycrystalline silicon layer from which the oxide film has been removed; and on the first conductivity type region. A step of introducing impurities having opposite conductivity types into the polycrystalline silicon layer and the polycrystalline silicon layer on the second conductivity type region, and forming a refractory metal silicide layer on the barrier layer Process and this high melting point gold Silicide layer, the barrier layer, and forming a gate electrode by selectively removing the polycrystalline silicon layer and is characterized in that it consists of.
[0010]
According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect , an oxide film formed by thermal oxidation on the surface of the polycrystalline silicon layer has a thickness of 300 to 800 mm, and the barrier The layer thickness is 20 to 50 mm.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a top view showing an example when an embodiment of a semiconductor device of the present invention is applied to a CMOS integrated circuit. 2 is a cross-sectional view taken along line AA in FIG. 3 is a cross-sectional view taken along line BB in FIG.
[0012]
The CMOS integrated circuit of this embodiment is composed of an n-channel MOS transistor 21 and a p-channel MOS transistor 22 as shown in FIG. The n-channel MOS transistor 21 sandwiches a common gate electrode 23 and has a source region 24 and a drain region 25. The p-channel MOS transistor 24 sandwiches the gate electrode 23 and has a source region 26 and a drain region 27.
[0013]
Further, in this CMOS integrated circuit, as shown in FIG. 2, a P well 32 that becomes a region of an n-channel MOS transistor 21 and an N well 33 that becomes a region of a p-channel MOS transistor 22 are formed in a semiconductor substrate 31. An element isolation film 34 is formed in a portion where no element is formed.
[0014]
Polycrystalline silicon layers 36a and 36b are formed on the surface of the semiconductor substrate 31 via a gate oxide film 35, and irregularities are formed on the surfaces of the polycrystalline silicon layers 36a and 36b. An N-type impurity (for example, arsenic) is ion-implanted into the polycrystalline silicon layer 36a on the P-well 32, and a P-type impurity (for example, boron) is ion-implanted into the polycrystalline silicon layer 36b on the N-well 33. Yes.
[0015]
A barrier layer 37 made of silicon oxide for preventing diffusion of impurities is formed on the surfaces of the polycrystalline silicon layers 36a and 36b. More specifically, the barrier layer 37 is formed on irregularities formed by granular growth of polycrystalline silicon when the surfaces of the polycrystalline silicon layers 36a and 36b are thermally oxidized. A refractory metal silicide layer 38 made of a tungsten silicide layer or the like is formed on the barrier layer 37.
[0016]
As described above, in the CMOS integrated circuit according to this embodiment, the barrier layer 37 is provided between the polycrystalline silicon layers 36 a and 36 b and the refractory metal silicide layer 38. For this reason, in the manufacturing process, it is possible to prevent the impurities in the polycrystalline silicon layers 36a and 36b from diffusing to each other, so that fluctuations in the threshold voltage of the transistor can be prevented, and the transistor operates normally and its reliability can be prevented. Can improve the performance.
[0017]
Further, in the CMOS integrated circuit according to this embodiment, irregularities are formed on the surfaces of the polycrystalline silicon layers 36a and 36b, and the barrier layer 37 is provided on the irregular surfaces. As a result, the electric field becomes strong due to the property that the uneven corners tend to concentrate electric charges, and a tunneling current easily occurs, so that the electric current flows sufficiently. Therefore, the electrical resistance component of the barrier layer 37 can be reduced, and the transistor Can be speeded up.
[0018]
Next, an example of a method for manufacturing a CMOS integrated circuit according to the embodiment configured as described above will be described with reference to FIGS.
First, as shown in FIG. 4A, an N well 33 to which an N-type impurity serving as a p-channel MOS transistor region is added and a P-type impurity serving as an n-channel MOS transistor region are added to a semiconductor substrate 31. A P well 32 is formed.
[0019]
Next, as shown in FIG. 4A, an element isolation region 34 is formed at a predetermined location, and a gate oxide film 35 having a thickness of about 100 mm is formed on the surface of the semiconductor substrate 31 surrounded by the element isolation region 34. Let it form. Subsequently, in order to form a gate electrode, a polycrystalline silicon layer 36 having a thickness of about 2000 mm is formed on the entire surface. The polycrystalline silicon layer 36 is formed in a low-temperature atmosphere such as a temperature of 570 ° C. so that an oxide film 41 can be easily formed by granular growth described later.
[0020]
Next, as shown in FIG. 4B, an oxide film 41 made of silicon oxide is formed on the surface of the polycrystalline silicon layer 36 by thermal oxidation. This oxide film 41 is made of granular growth of polycrystalline silicon. Is. The oxide film 41 is formed by wet oxidation in an atmosphere of 900 ° C., and the film thickness is set to 300 to 800 mm. When the oxide film 41 is formed by wet oxidation, for example, a gas (gas) having a ratio of 6 hydrogen and 4 oxygen is flowed by 1 liter per second.
[0021]
Here, the film thickness of the oxide film 41 is in the range of 300 to 800 mm because the grain size of polycrystalline silicon that grows granular is too small when the film thickness is 300 mm or less, and the grain size is 800 mm or more. This is because a large product cannot be obtained by saturation.
Next, when the oxide film 41 on the polycrystalline silicon layer 36 is removed with hydrofluoric acid (HF), the surface of the polycrystalline silicon layer 36 is uneven as shown in FIG. It becomes.
[0022]
Next, as shown in FIG. 4D, a barrier layer 37 made of a silicon oxide film is formed on the surface of the polycrystalline silicon layer 36 from which the oxide film 41 has been removed in order to prevent diffusion of impurities. The barrier layer 37 is formed by oxidizing only oxygen in an atmosphere of 700 ° C., and the thickness of the barrier layer 37 is about 20 to 50 mm.
[0023]
Here, the thickness of the barrier layer 37 is set to about 20 to 50 mm for the following reason. That is, the thickness of the barrier layer 37 depends on an allowable value that allows mutual diffusion of impurities implanted in the polycrystalline silicon layers 36a and 36b in the manufacturing process, and an upper limit value of the electrical resistance component of the barrier layer 37 (transistor This is because the above range is preferable in consideration of these factors.
[0024]
Subsequently, as shown in FIG. 5E, a resist pattern 42 is formed on the polycrystalline silicon layer 36 on the P well 32 that becomes the region of the n-channel MOS transistor, and on the N well 33 that becomes the region of the p-channel MOS transistor. For example, boron (B) is ion-implanted as a P-type impurity into the polycrystalline silicon layer 36b. This ion implantation is performed by applying acceleration energy of about 35 keV to the ions, and the ion implantation amount is about 10 ¹⁵ ions / cm ² .
[0025]
Next, as shown in FIG. 5F, after the resist pattern 42 is peeled off, a resist pattern 43 is formed on the polycrystalline silicon layer 36b on the N well 33 which becomes the region of the p-channel MOS transistor, and an n-channel NMOS is formed. For example, arsenic (As) or phosphorus (P) is ion-implanted as an N-type impurity into the polycrystalline silicon layer 36a on the P-well 32 serving as a transistor region. This ion implantation is performed by applying acceleration energy of about 35 keV to the ions, and the ion implantation amount is about 10 ¹⁵ ions / cm ² .
[0026]
Next, as shown in FIG. 5G, after the resist pattern 43 is peeled off, a refractory metal silicide layer 38 is formed on the entire surface. The refractory metal silicide layer 38 is made of, for example, a tungsten silicide layer and is formed by sputtering.
Subsequently, as shown in FIG. 5H, a resist pattern 44 is formed, and the gate oxide film 35, the polycrystalline silicon layers 36a and 36b, the barrier layer 37, and the refractory metal silicide layer 38 are etched using the resist pattern 44 as a mask. The gate electrodes of the p-channel MOS transistor and the n-channel MOS transistor are formed simultaneously. Thereby, the gate electrode 23 as shown in FIGS. 1 and 3 is formed.
[0027]
Thereafter, an N-type impurity is implanted on the N well 33 serving as a region of the p-channel MOS transistor 22 using the gate electrode 23 as a mask to form a source region and a drain region. Similarly, a source region and a drain region are formed on a P-well 32 serving as an n-channel MOS transistor region by implanting a P-type impurity using the gate electrode 23 as a mask.
[0028]
As described above, in the CMOS integrated circuit manufactured by the manufacturing method according to this embodiment, the barrier layer 37 made of silicon oxide is provided between the polycrystalline silicon layers 36a and 36b and the refractory metal silicide layer 38. I did it. For this reason, in the manufacturing process after introducing the impurities into the polycrystalline silicon layers 36a and 36b, different impurities in the polycrystalline silicon layer 36a and the polycrystalline silicon 36b can be prevented from diffusing mutually, so that the threshold of the transistor The fluctuation of the value voltage can be prevented, so that the transistor operates normally and the reliability thereof can be improved.
[0029]
In addition, as shown in FIG. 6, irregularities are formed by forming the surfaces of the polycrystalline silicon layers 36a and 36b in a granular form, and a barrier layer 37 made of silicon oxide is formed on the irregular surfaces. As a result, the electric field is strong due to the property that the uneven corners tend to concentrate electric charges, tunnel current easily occurs, and sufficient current flows. Therefore, the electrical resistance component of the barrier layer 37 can be reduced, and the transistor Can be speeded up.
[0031]
【The invention's effect】
As described above , according to the present invention, it is possible to improve the reliability by preventing the fluctuation of the threshold voltage of the transistor due to the mutual diffusion of impurities generated in the conventional manufacturing process. High speed operation can be realized by reducing electrical resistance component.
[Brief description of the drawings]
FIG. 1 is a plan view showing an example of a configuration of a CMOS integrated circuit according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line AA in FIG.
3 is a cross-sectional view taken along line BB in FIG.
FIG. 4 is a cross-sectional view showing a manufacturing process of the CMOS integrated circuit according to the embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a step that follows the manufacturing step.
FIG. 6 is an enlarged cross-sectional view showing a state of an interface between a polycrystalline silicon layer and a barrier layer.
FIG. 7 is a plan view of the prior art.
8 is a cross-sectional view taken along line CC in FIG.
[Explanation of symbols]
21 n-channel MOS transistor 22 p-channel MOS transistor 23 gate electrode 24, 26 source region 25, 27 drain region 31 semiconductor substrate 32 P well 33 N well 35 gate oxide film 36a, 36b polycrystalline silicon layer 37 barrier layer 38 refractory metal Silicide layer

Claims (2)

Forming a first conductivity type region and a second conductivity type region on a silicon substrate;
Forming a gate oxide film on each of the first conductivity type region and the second conductivity type region;
Forming a polycrystalline silicon layer on the gate oxide film;
Thermally oxidizing the surface of the polycrystalline silicon layer;
Removing the oxide film formed by the thermal oxidation;
Forming a barrier layer made of a silicon oxide film on the polycrystalline silicon layer from which the oxide film has been removed;
Introducing impurities having opposite conductivity types into the polysilicon layer on the first conductivity type region and the polysilicon layer on the second conductivity type region,
Forming a refractory metal silicide layer on the barrier layer;
Selectively removing the refractory metal silicide layer, the barrier layer, and the polycrystalline silicon layer to form a gate electrode;
A method for manufacturing a semiconductor device, comprising: 2. The semiconductor according to claim 1 , wherein the oxide film formed by thermal oxidation on the surface of the polycrystalline silicon layer has a thickness of 300 to 800 mm, and the barrier layer has a thickness of 20 to 50 mm. Device manufacturing method.

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