JPH0789571B2 - Method of manufacturing semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor memory device, and particularly
It is used for manufacturing EPROM cells and the like.

[Technical background of the invention]

Conventionally, EPROM cells are manufactured by the method shown in FIGS. 2 (a) and (b).

First, for example, a thermal oxide film is formed on the main surface of the p-type silicon substrate 1, a first polycrystalline silicon film is deposited on the entire surface, and a part thereof is selectively etched and separated. Next, after forming a polysilicon oxide film on the surface of the first polycrystalline silicon film, a second polycrystalline silicon film is deposited on the entire surface. Subsequently, after forming a photoresist pattern on the second polycrystalline silicon film, the second polycrystalline silicon film, the polysilicon oxide film, the first polycrystalline silicon film and the thermal oxide film are subjected to the reactive ion etching method ( The gate oxide film 2, the floating gate 3, the polysilicon oxide film 4 and the control gate 5 are sequentially laminated on the substrate 1 by patterning by the RIE method (shown in FIG. 2A).

Then, for example, arsenic is ion-implanted using the control gate 5 as a mask. Subsequently, for example, by performing heat treatment in an oxidizing atmosphere at 1000 ° C., a thermal oxide film 6 is formed on the exposed surfaces of the floating gate 3, the control gate 5 and the substrate 1, and arsenic is activated to n ⁺ type source, Drain regions 7 and 8 are formed (shown in FIG. 2B).

[Problems of background technology]

Considering the data retention characteristics of the EPROM cell, the breakdown voltage of the thermal oxide film 6 at the edge of the floating gate 3 becomes a serious problem. In order to improve the breakdown voltage of the thermal oxide film 6, it is necessary to perform thermal oxidation at a temperature of 950 ° C. or higher to improve the quality of the thermal oxide film 6.

However, if the heat treatment is performed at a temperature of 950 ° C. or higher, the lateral diffusion length of the source / drain regions 7 and 8 becomes long.
Therefore, when the gate length of the floating gate 3 is as small as 2 mm or less, punch through may occur and the send transistor may not operate normally.

[Object of the Invention]

The present invention has been made to solve the above drawbacks, and maintains a good data retention characteristic even when the gate length is as fine as 2 mm or less, and manufactures a semiconductor memory device that exhibits normal cell transistor operation. It is meant to provide a way to get.

[Outline of Invention]

According to a method of manufacturing a semiconductor memory device of the present invention, a first insulating film, a first gate electrode having a gate length of 2 mm or less, a second insulating film are formed on a main surface of a semiconductor substrate of a first conductivity type according to a normal process. And the second gate electrode are sequentially stacked and formed, and then 950 ° C.
Oxidation is performed at the above temperature to form a thermal oxide film on the exposed first gate electrode, second gate electrode and substrate surface, and ion implantation of the second conductivity type impurity is performed using the second gate electrode as a mask. After that, heat treatment is performed at a temperature of 950 ° C. or lower to activate the impurities to form the second conductivity type source / drain regions.

According to such a method, the thermal oxide film is first formed on the exposed surface of the first gate electrode (floating gate) or the like by high-temperature oxidation at 950 ° C. or higher, so that the thermal oxide film with good film quality can be formed and excellent Gator storage characteristics can be maintained. Then, after ion-implanting impurities, low-temperature heat treatment at 950 ° C. or less can suppress the lateral diffusion length of the source / drain regions, and a good cell transistor can be obtained even if the gate length is as short as 2 μm or less. The characteristics can be obtained.

Example of Invention

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1A to 1D show a memory cell area for 2 bits.

First, after forming the field oxide film 12 on the surface of the p-type silicon substrate 11 by the selective oxidation method, thermal oxidation is performed to obtain a film thickness of 20.
A 0Å gate oxide film 13 is formed. Next, a film thickness of 400 on the entire surface
After the 0Å first polycrystalline silicon film 14 is deposited, it is heat-treated at 900 ° C. for 50 minutes in a POCl ₃ atmosphere to dope the first polycrystalline silicon film 14 with phosphorus. Subsequently, a part of the first polycrystalline silicon 14 is selectively ed and separated. Subsequently, thermal oxidation is performed to form a polysilicon oxide film 15 having a film thickness of 300 Å on the surface of the first polycrystalline silicon film 14. Next, the second polycrystalline silicon film 16 with a film thickness of 3500Å is formed on the entire surface.
After the deposition, the second polycrystalline silicon film 16 is doped with phosphorus by heat treatment at 900 ° C. for 35 minutes in a POCl ₃ atmosphere.
(See FIG. 1 (a)).

Then, after forming a photoresist pattern 17 on the second polycrystalline silicon film 16, the second polycrystalline silicon film 16 is formed by a reactive ion etching method (RIE method) using the photoresist pattern 17 as a mask by a poly (ammonium fluoride) solution. The silicon oxide film 15 is formed on the first polycrystalline silicon film 14 by the RIE method.
The gate oxide film 13 is sequentially etched with an ammonium fluoride solution to sequentially form a gate oxide film 13, a floating gate 18, a polysilicon oxide film 15 and a control gate 19 on the substrate 11. At this time, the gate length of the floating gate 18 is 2 μm or less (shown in FIG.

Then, after removing the photoresist pattern 17, heat treatment is performed in an oxygen atmosphere at 950 ° C. for 20 minutes to form a thermal oxide film 20 on the exposed surfaces of the floating gate 18, control gate 19 and substrate 11 (see FIG. (C) Illustration).

Then, using the control gate 19 as a mask, arsenic is ion-implanted through the thermal oxide film 20 under the conditions of an acceleration energy of 100 keV and a dose of 5 × 10 ¹⁵ / cm ^-2 . Subsequently, heat treatment is performed at 900 ° C. in a nitrogen atmosphere to activate arsenic to form n ⁺ type source / drain regions 21 and 22. Subsequently, after depositing an interlayer insulating film 23 on the entire surface, a contact hole is opened. Subsequently, after depositing an Al film on the entire surface, patterning is performed to form the wiring 24, and an EPROM cell is manufactured ((d) in the figure).

According to this method, since the floating gate 18 and the control gate 19 are formed in the steps up to FIG. 1B, thermal oxidation is performed at 950 ° C. in the step in FIG. The thermal oxide film 20 thus formed has a good film quality, and can maintain a good retention characteristic of the data stored in the floating gate 18. Further, after arsenic is ion-implanted in the step of FIG. 6D, heat treatment is performed at 900 ° C. to activate arsenic, so that the lateral diffusion length of the source / drain regions 21 and 22 can be suppressed. it can. Therefore, the gate length of the floating gate 18 is 2
Punch-through can be prevented and excellent cell transistor characteristics can be obtained even if the size is as small as μm or less.

Although arsenic is ion-implanted in the step of FIG. 1D in the above embodiment, phosphorus may be ion-implanted instead of arsenic. Further, in the above embodiment, the heat treatment after the ion implantation was performed in the nitrogen atmosphere in the step of FIG. 1D, but an oxygen atmosphere or a mixed atmosphere of nitrogen and oxygen may be used.

〔The invention's effect〕

As described above in detail, according to the method of manufacturing a semiconductor memory device of the present invention, good data retention characteristics and cell transistor characteristics can be expected even if the floating gate has a fine gate length of 2 μm or less. This has remarkable effects such as high reliability and high performance of the device.

[Brief description of drawings]

1 (a) to 1 (d) are EPROMs in an embodiment of the present invention.
Sectional views showing a method for manufacturing a cell, FIGS. 2A and 2B.
FIG. 6 is a cross-sectional view showing a conventional method for manufacturing an EPROM cell. 11 …… p-type silicon substrate, 12 …… field oxide film, 13
...... Gate oxide film, 14 …… First polycrystalline silicon film, 15
…… Polysilicon oxide film, 16 …… Second polycrystalline silicon oxide film, 17 …… Photoresist pattern, 18 …… Floating gate, 19 …… Control gate, 20 …… Thermal oxide film, 21, 22 …… n ⁺ Type source / drain region, 23 ... Interlayer insulating film, 24 ... Wiring.

Claims (4)

[Claims] 1. A step of forming a first insulating film on a main surface of a first conductivity type semiconductor substrate, and a step of depositing a first gate electrode material on the entire surface and then selectively etching a part thereof. ,
Forming a second insulating film on the surface of the first gate electrode material, depositing a second gate electrode material on the entire surface, second gate electrode material, second insulating film, first Patterning the gate electrode material and the first insulating film, and sequentially stacking the first insulating film, the first gate electrode having a gate length of 2 μm or less, the second insulating film, and the second gate electrode on the substrate. And the step of forming and oxidation at a temperature of 950 ° C or higher,
A step of forming a thermal oxide film on the exposed first gate electrode, second gate electrode and substrate surface; a step of ion-implanting a second conductivity type impurity using the second gate electrode as a mask; A method of manufacturing a semiconductor memory device, comprising the step of performing heat treatment at the following temperature to activate impurities to form second conductivity type source / drain regions. 2. The method for manufacturing a semiconductor memory device according to claim 1, wherein the second conductivity type impurity is arsenic or phosphorus. 3. The method for manufacturing a semiconductor memory device according to claim 1, wherein the heat treatment at 950 ° C. or lower is performed in a nitrogen or oxygen atmosphere or a mixed atmosphere of nitrogen and oxygen. 4. A method of manufacturing a semiconductor memory device according to claim 1, wherein the first gate electrode is a floating gate and the second gate electrode is a control gate.