JPH0381297B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for introducing impurities into the side surfaces of a groove formed on the surface of a semiconductor substrate. .

(Prior Art) In recent years, in semiconductor storage devices such as dynamic random access memories, so-called groove capacitors have been used as capacitors to cope with higher integration. FIG. 4 shows the structure of a dynamic random access memory using groove capacitors. In the figure, 11 is, for example, P
12 is a groove capacitor formed on this substrate 11, and 13 is a MOS transistor.

Incidentally, an N-type impurity region 121 is formed on the groove surface of the groove capacitor 12 in order to reduce the flat band voltage (V _FB ). A conventional method of forming this impurity region 121 is shown in FIG. First, as shown in FIG. 5a, a first thermal oxide film 22 of about 1000 Å is grown on a P-type silicon substrate 21 in a portion where a groove is to be formed. Thereafter, a silicon nitride (Si ₃ N ₄ ) film 23 of about 1500 Å is deposited on this thermal oxide film 22. Thereafter, a photoresist film is applied on the nitrogen silicon film 23, and a groove pattern 24 is formed by photolithography.

Next, as shown in FIG. 5b, the groove pattern 24
Using this as a mask, the silicon nitride film 23, thermal oxide film 22, and silicon substrate 21 are sequentially etched by the RIE method to form a groove 25.

Next, as shown in FIG. 5c, a second thermal oxide film 26 of about 100 Å is grown on the surface of the groove 25. Thereafter, ions are sequentially implanted into side surfaces A and B of the trench 25. As a result, N-type impurity regions 27 are formed on side surfaces A and B.

Next, as shown in FIG. 5d, the nitrogen silicon film 2
3. After etching the first and second thermal oxide films 22 and 26, a gate oxide film 28 with a thickness of about 100 Å is formed on the surface of the groove 25. Next, an open pattern (not shown) of a photoresist film is formed by photolithography in a planar region other than the groove 25, and ⁷⁵ As ⁺ is ion-implanted. Next, polycrystalline silicon is deposited to form a gate electrode 29.

The conventional method for manufacturing an impurity region has been described above, but this method has the following problems. This will be explained below. Now, set the depth of groove 25 to about 3μ.
m, and the size of the opening surface is approximately 1.0 μm×1.0 μm, it is necessary to set the implantation angle of ^{the 75} As ⁺ ions to the side surface A of the trench 25 at approximately 83°. Then, on the bottom surface C of the groove 25, ⁷⁵ As ⁺ ions are present at an angle of about 7°.
injected with As a result, the bottom surface C has a side surface 251
An impurity region 30 (see FIGS. 5c and 5d) is formed with a concentration about 10 times that of the above. For example, if the implantation conditions for ⁷⁵ As ⁺ ions are 400KeV and 1×10 ¹⁵ cm ^-2 , an N-type impurity region 27 with a concentration of 1×10 ¹⁹ cm ^-3 is formed on side A.
is formed, and 1×10 ²⁰ which is approximately 10 times this is formed on the bottom surface C.
An N-type impurity region 30 having a concentration of cm ^-3 is formed. Moreover, since this relationship also holds between the side surface B and the bottom surface C, an impurity region 30 having a concentration approximately 20 times that of the impurity region 27 on the side surface A or B is formed on the bottom surface C after all.

However, when the impurity concentration on the bottom surface C side of the trench 25 becomes high, when the gate oxide film 28 is formed on this bottom surface C side, accelerated oxidation occurs and the film thickness becomes thicker. As a result, the cell capacitance is reduced and the operating margin of the circuit is reduced. Further, as the impurity concentration on the bottom surface C side increases, the breakdown electric field of the gate oxide film 28 on the bottom surface C side becomes low, although the film thickness is thick, and the reliability decreases.

(Problems to be Solved by the Invention) As described above, when impurities are injected into the groove side surfaces of a groove capacitor, in the conventional method, the impurities are also injected into the groove bottom surface, and the concentration is high, so There were problems such as a decrease in the operating margin and a decrease in the breakdown electric field.

Therefore, the present invention provides a method for manufacturing a semiconductor device that can prevent the introduction of impurities into the bottom surface of the trench due to the introduction of impurities into the side surface of the trench, thereby preventing a decrease in the operating margin of the circuit and a decrease in the breakdown electric field. The purpose is to provide.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention includes a step of forming a first coating on the surface of a groove formed in a semiconductor substrate, and a step of forming a first coating on the bottom surface side of the groove. Part 2
This method includes a step of forming a film, and a step of implanting impurity ions into the side surfaces of the trench.

(Function) According to the above method, when in-implanting impurities into the side surfaces of the groove, the second film formed on the bottom surface of the groove serves as a mask and can prevent ion implantation into the bottom surface of the groove.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIGS. 1A to 1E sequentially show the steps in the manufacturing method of one embodiment, and typically show the case where impurities are introduced into the groove surface of the groove capacitor.

First, as shown in FIG. 1a, an element isolation region 102 is formed on a silicon substrate 101 by the usual LOCOS method. Next, on the silicon substrate in the element area,
A first thermal oxide film 103 is formed to a thickness of about 1000 Å. Next, silicon nitrogen (SiN ₄ ) is deposited on this thermal oxide film 103.
A film 104 is formed to a thickness of about 1500 Å. Next, a groove pattern 105 is formed using a photoresist film by photolithography.

Thereafter, as shown in FIG. 1b, using the photoresist film as a mask, the silicon nitride film 104 and the thermal oxide film 1 are
03. The silicon substrate 101 is continuously etched to form a groove in the silicon substrate 101. next,
After removing the photoresist film, a second thermal oxide film 106 made of silicon dioxide, for example, is formed on the groove surface at a temperature of 100%.
A. Grow. Next, a film 107 made of, for example, polycrystalline silicon is deposited to a thickness of about 6000 Å over the entire surface. Here, if the size of the groove is, for example, 1 μm x 1 μm and the depth in the silicon substrate 101 is 4 μm, the groove will be
Completely filled with polycrystalline silicon film.

Thereafter, as shown in FIG. 1c, the polycrystalline silicon film 107 on the plane and the polycrystalline silicon film 107 deposited in the groove are etched by RIE. By this etching, approximately
A polycrystalline silicon film 108 of 2000 Å is left.
After that, ⁷⁵ As ⁺ was implanted onto the surface of the silicon substrate 101 on one side of the groove at an angle of 83° in the same manner as in FIG. 4c.
Ions are implanted under the conditions of 400KeV and 1×10 ¹⁵ cm ^-2 . As a result, an N-type impurity region 109 having a concentration of about 1×10 ¹⁹ cm ^-3 is formed on the side surface A of the trench. At the same time, ⁷⁵ As ⁺ ions are also implanted onto the polycrystalline silicon film 108 left on the trench bottom surface C.
In this case, on the polycrystalline silicon film 108 on the trench bottom surface C, ⁷⁵ As ⁺ is implanted at a density approximately eight times that on the trench side surface A because the ion implantation angle is 7 degrees.
When the ion implantation into the groove side surface A is completed, ion implantation into the opposing trench side surface B is subsequently performed.

Next, as shown in FIG. 1d, the polycrystalline silicon film 108 is selectively etched and removed using, for example, the CDE method. After that, the silicon nitride film 10
Etch 4.

Next, as shown in FIG. 1e, the first and second thermal oxide films 103 and 107 are etched. Then, a first gate oxide film 110 of 100 Å is grown over the entire surface. Then, by photolithography, ⁷⁵ As ⁺
A resist opening pattern 111 is formed to set a region where ions are to be implanted. Thereafter, using the photoresist film as a mask, ⁷⁵ As ⁺ ions are implanted over the entire surface at 400 KeV and 1×10 ¹⁵ cm ⁻² . As a result, N-type impurity regions 112 having the same concentration as the trench side surfaces A and B are formed on the trench bottom surface C and the trench outer surface.
Thereafter, the photoresist film is removed and a first gate electrode 113 is formed. Next, after selectively etching the first gate oxide film 110, a second gate oxide film 114 is formed in an H ₂ O atmosphere at about 800°C. At this time, an oxide film 114 is grown to a thickness of 1200 Å on the first gate electrode 113 and 200 Å on the silicon substrate 111. Next, a second gate electrode 115 is formed. Thereafter, using this second gate electrode 115 as a mask, a silicon substrate 101 is coated.
⁷⁵ As ⁺ ions were implanted at 5 × 10 ¹⁵ cm ^-2 at 60 KeV,
A source/drain diffusion layer 116 is formed. Thereafter, a silicon oxide film 117 is deposited by the CVD method, and a contact hole 118 for a bit line is formed. Next, after forming aluminum wiring 119, bit lines are formed.

With the above steps, the formation of the dynamic random access memory is completed.

According to this embodiment detailed above, the groove side surface A,
When implanting ⁷⁵ As ⁺ ions into B, the polycrystalline silicon film 108 on the bottom surface C of the trench serves as a mask to prevent ion implantation into the bottom surface C of the trench. Thereby, it is possible to prevent a decrease in the operating margin of the circuit and a decrease in breakdown voltage due to an increase in the ion concentration on the groove bottom surface C side.

Next, another embodiment of the present invention will be described in detail with reference to FIGS. 2a to 2e. In the following description, the present invention will be explained using an example of introducing an impurity into the side surface of an element isolation trench.

First, as shown in FIG. 2a, a silicon substrate 2
A first thermal oxide film 202 with a thickness of about 1000 Å is formed on 01. Next, an ion implantation pattern 203 of a photoresist film is formed by photolithography.
Then, As ⁺ ions are implanted using the photoresist film as a mask to form the first N-type impurity region 2.
Form 04.

Next, as shown in FIG. 2b, after removing the resist, a silicon nitride film 205 of 1500 Å is deposited on the entire surface.
Thereafter, a trench pattern with a width of about 1 μm is formed using a photoresist film in a region that will become an element isolation region by photolithography. Next, silicon nitride film 20
5. Thermal oxide film 202 and silicon substrate 201 are sequentially etched to form grooves 206. in this case,
The depth of the groove 206 in the silicon substrate 201 is
The thickness should be approximately 4 μm. Next, a second thermal oxide film 207 made of, for example, a silicon dioxide film is applied to the surface of the groove 206.
Grow 100Å. Next, at the bottom of groove 206 ¹¹ B ⁺
is about 1×10 ¹³ cm ⁻² at 40 KeV, and a P-type impurity region 208 is formed.

After that, as shown in FIG. 2c, after depositing a first polycrystalline silicon film 209 of 6000 Å on the entire surface,
A first polycrystalline silicon film 210 with a thickness of about 2000 Å is left on the groove bottom surface C by a method such as that of the groove capacitor (see FIG. 2d). Next, ⁷⁵ As ⁺ is applied to sides A and B of the groove 206 at an injection angle of approximately 83°.
Ion implantation is performed at 400KeV and 1×10 ¹⁵ cm ^-2 .

Next, as shown in FIG. 2e, the first polycrystalline silicon film 210 remaining on the trench bottom surface C is removed. Thereafter, after etching the silicon nitride film 205 and the first and second thermal oxide films 202 and 207, a first gate oxide film 211 is formed. Next, a first gate electrode 212 is formed. In this case, since the P-type impurity region 208 with a sufficiently high concentration is formed in the groove bottom surface C, the cells can be electrically isolated sufficiently. Then the first
The second gate oxide film 211 is etched to form a second gate oxide film 213. Next, after forming the second gate electrode 214, source/drain diffusion layers 215 are formed similarly to the groove capacitor. Next, a silicon oxide film 216 is formed using the CVD method.
form. And contact hole 217 in this
After forming, aluminum wiring 218 is formed. This completes the formation of the dynamic random access memory.

As described above, in this embodiment, an impurity region 208 is formed on the groove bottom surface C, a polycrystalline silicon film 210 is formed, and ⁷⁵ As ⁺ ions are implanted into the groove side surfaces A and B. However, even in this case, when ions are implanted into the trench side surfaces A and B, ion implantation into the trench bottom surface C can be prevented, so that the same effect as in the previous embodiment can be obtained.

In the above description, a case has been described in which the polycrystalline silicon film left on the bottom surface of the groove is finally removed, but it may be left as shown in FIG. In the method shown in FIG. 2, there is no problem even if the polycrystalline silicon film 210 is left because the impurity region 208 has already been formed on the bottom surface C of the trench. Furthermore, even with the method shown in Figure 1,
If the object is a trench capacitor, there is no particular need for the impurity region 112 on the trench bottom surface C, so it is fine to leave the polycrystalline silicon film 108 at any time.

Although FIG. 3 shows the case where the oxide film 219 is formed on the polycrystalline silicon film 210, it goes without saying that this may not be necessary.

As described above, a polycrystalline silicon film 10 is formed on the groove bottom surface C.
If 8, 210 are left, the polycrystalline silicon film 108, 210 is
It is more effective to remove the second thermal oxide films 106, 207 by etching using the mask as a mask and then implant the ions in terms of lowering the accelerating voltage for ion implantation.

In addition, when the polycrystalline silicon films 108 and 210 are left, the remaining polycrystalline silicon films ^{108 and} 210 are
8,210 may be oxidized. This corresponds to the case where the polycrystalline silicon film 210 in FIG. 3 becomes a thermally oxidized oxide film.

〔Effect of the invention〕

As described above, the present invention provides a method for manufacturing a semiconductor device that can prevent a decrease in the operating margin of a circuit and a drop in breakdown voltage due to the introduction of impurities into the bottom surface of the trench when introducing impurities into the side surfaces of the trench. be able to.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the steps of one embodiment of the semiconductor device according to the present invention, FIG. 2 is a sectional view showing the steps of another embodiment of the semiconductor device according to the invention,
FIG. 3 is a sectional view for explaining still another embodiment of the semiconductor device according to the present invention, FIG. 4 is a sectional view showing the structure of a dynamic random access memory, and FIG. 5 is a conventional manufacturing method of the semiconductor device. FIG. 3 is a cross-sectional view illustrating the steps of the method. 101, 201...Silicon substrate, 102...
Element isolation region, 103, 106, 202, 207
...Thermal oxide film, 104,205...Silicon nitride film,
105... Groove pattern, 107, 108, 20
9,210...polycrystalline silicon film, 109,11
2,204,208... impurity region, 110,1
14, 211, 213...gate oxide film, 111
...Resist opening pattern, 113, 115, 2
12,214...gate electrode, 116,215...
...diffusion layer, A, B...groove side surface, C...groove bottom surface, 2
03...Ion implantation pattern, 206...Groove, 1
18, 217...Contact hole, 218...Aluminum wiring.

Claims (1)

[Claims] 1. A first step of forming a groove in a semiconductor substrate, a second step of forming a first coating on the surface of the groove, and a second coating on the first coating. a fourth step of removing the second coating so as to leave a portion of the second coating on the bottom surface of the groove; and a fifth step of implanting ions into the side surfaces of the groove. A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first film is a silicon dioxide film and the second film is a polycrystalline silicon film. 3. A first step of forming a groove in the semiconductor substrate, a second step of forming a first coating on the surface of the groove, and a third step of forming a second coating on the first coating. a fourth step of removing the second coating so as to leave a portion of the second coating on the bottom surface of the groove; a fifth step of implanting ions into the side surface of the groove; and a sixth step of removing the second film. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the first film is a silicon dioxide film and the second film is a polycrystalline silicon film. 5. A first step of forming a groove in the semiconductor substrate, a second step of forming a first coating on the surface of the groove, and a third step of forming a second coating on the first coating. a fourth step of removing the second coating so as to leave a portion of the second coating on the bottom surface of the groove; and a fifth step of removing the first coating from the side surface of the groove.
A method for manufacturing a semiconductor device, comprising the steps of: and a sixth step of implanting ions into the side surface of the groove. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the first film is a silicon dioxide film and the second film is a polycrystalline silicon film. 7. A first step of forming a groove in the semiconductor substrate, a second step of forming a silicon dioxide film on the surface of the groove, and a third step of forming a polycrystalline silicon film on the silicon dioxide film. a fourth step of removing the polycrystalline silicon film so as to leave a portion of the polycrystalline silicon film on the bottom surface of the trench; a fifth step of removing the silicon dioxide film on the side surface of the trench; and a fifth step of removing the silicon dioxide film on the side surface of the trench. A method for manufacturing a semiconductor device, comprising: a sixth step of implanting ions into the surface of a semiconductor substrate; and a seventh step of oxidizing the polycrystalline silicon film left on the bottom of the groove.