JP3000657B2 - Method for manufacturing field effect semiconductor device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a method for manufacturing a field-effect semiconductor device,
In particular, the present invention relates to a method for manufacturing a field-effect semiconductor device capable of stably and easily manufacturing a transistor element with control of an inversion voltage.

2. Description of the Related Art In the manufacturing process of a field-effect integrated circuit, as the degree of integration increases, the miniaturization of constituent elements, particularly the reduction of the thickness of the gate oxide film, is progressing, and the control of the withstand voltage and inversion voltage of the gate oxide film becomes a problem. Has become. FIG. 5 shows a conventional general process. First, the semiconductor substrate 101 is oxidized to form a thermal oxide film 103, and then impurity ions, for example, boron are implanted to form the p ^- region 102 and the inversion voltage is controlled (FIG. 5a). Next, thermal oxide film
After removing the 103 by etching (FIG. 5b), the semiconductor substrate 101 is oxidized again to form a gate oxide film 104.
Next, a gate electrode 105 made of a polycrystalline semiconductor is formed at a predetermined position on the gate oxide film 104 (FIG. 5c). Thereafter, source / drain regions 110 are formed (FIG. 5c), an interlayer insulating film 112 is deposited, and aluminum wirings 113 are formed (FIG. 5d) in accordance with a normal MOS type semiconductor manufacturing process.

Problems to be Solved by the Invention The method for manufacturing a semiconductor device as shown in FIG. 5 has the following problems.

(1) Crystal defects are generated in the semiconductor substrate 101 by ion implantation for controlling the inversion voltage, and thereafter, gate oxidation is performed, so that crystal defects are taken into the gate oxide film 104 and reliability is reduced.

(2) Impurity ions introduced into the semiconductor substrate by implantation for controlling the inversion voltage are redistributed when the gate insulating film is formed, and the controllability of the inversion voltage is poor. In particular, in the case of a buried channel type MOS transistor, the inversion voltage in the short channel region is deteriorated, which causes a hindrance to miniaturization.

Even if the implantation amount is determined in consideration of the redistribution of impurities, variations in the gate oxidation time and temperature directly cause variations in the inversion voltage, and the process control is strict.

(3) When the gate oxide film thickness deviates from the target value, re-oxidation is impossible.

The present invention has been made in view of the above-described problems, and has as its object to provide a method of manufacturing a field-effect semiconductor device that facilitates control of inversion control, reduces manufacturing variations, and improves the reliability of a gate insulating film. I do.

Means for Solving the Problems The present invention comprises a step of forming a first insulating film serving as a gate insulating film on a semiconductor substrate, and a step of forming a first conductor film on the first insulating film. Forming a second conductor film on the first conductor film and patterning the second conductor film; and using the second conductor film as a mask to form the first conductor film. Implanting an impurity for controlling a reversal voltage into the substrate by large-angle ion implantation at an angle of 40 to 45 degrees into the substrate via the second conductive film as a mask; Forming a first semiconductor region of the second conductivity type by implanting impurities in a substantially vertical direction into the substrate via the conductor film; and forming a second semiconductor region left on the side wall of the second conductor film. Forming a spacer of an insulating film, and using the second conductor film and the spacer as a mask, Forming a second semiconductor region of a second conductivity type by implanting impurities in a substantially vertical direction into the substrate, wherein the first and second conductor films are used as gate electrodes, and the first and second conductive films are used as gate electrodes. This is a method for manufacturing a field-effect semiconductor device using a second semiconductor region as a source and a drain.

Operation The present invention operates as follows by the above configuration.

(1) Since the gate insulating film is formed before the impurity ions are implanted into the semiconductor substrate, the insulating film has good crystallinity and good withstand voltage and reliability.

(2) The step of controlling the inversion voltage by injecting impurities after the formation of the gate insulating film does not affect the concentration distribution of impurity ions due to the formation of the gate insulating film, so that the control of the inversion voltage is easy and the manufacturing variation is small. . Furthermore, in the case of a buried channel type MOS transistor, since the diffusion of impurity ions in the direction of the substrate is suppressed, the deterioration of the inversion voltage in the short channel region is small.

(3) Even when the gate oxide film thickness deviates from the target value, re-oxidation is possible because the inversion voltage is not affected at all by the gate oxide film formation. This is highly effective when mass-producing semiconductor devices.

Embodiment (First Embodiment) FIG. 1 is a sectional view showing a manufacturing process of a field-effect semiconductor device according to a first embodiment of the present invention. Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (e).

First, a P-type silicon substrate 101 is thermally oxidized to form a gate oxide film 104 of 10 to 15 nm, and then an amorphous silicon film 106 is formed.
Deposit 50 to 60 nm (FIG. 1a). Next, in order to control the inversion voltage, impurity ions such as boron are added at 30 to 40 KeV at 3 to 5 × 10 5
^{Implant 12} cm ^-2 to form p ^- region 102 (FIG. 1b).

Next, 25 polycrystalline silicon 105 is deposited on the amorphous silicon film 106.
Deposit 0 to 350 nm, and diffuse impurity ions, for example, phosphorus by a gas phase reaction (FIG. 1c). Due to this phosphorus diffusion, both the amorphous silicon film 106 and the polycrystalline silicon film 105 become N-type.

Next, a gate electrode composed of the amorphous silicon film 106 and the polycrystalline silicon film 105 is formed by etching. Thereafter, the source / drain regions 110 are formed (FIG. 1d), an interlayer insulating film 112 is deposited, and aluminum wirings 113 are formed (FIG. 1e) by a normal MOS type semiconductor manufacturing process.

Fig. 4 shows Pch by 3D process simulation
4 shows an impurity profile at the center of a channel of a type MOS transistor.

The horizontal axis is the depth from the substrate surface, and the vertical axis is the impurity concentration. Curve A shows an impurity profile in the case where ion implantation for controlling the inversion voltage is performed after forming the gate insulating film according to the manufacturing method of the present invention. However,
No injection protection film such as an amorphous semiconductor film is used.

Curve B shows an impurity profile when a gate insulating film is formed after ion implantation for controlling an inversion voltage is performed according to a conventional manufacturing method. The ion species used for the ion implantation is boron ions, and the implantation energy is 20 KeV. Curve C shows a profile of an impurity (here, P ⁺ ) in an N well formed in a predetermined region of the substrate.

From FIG. 4, it can be seen that the boron ions implanted for controlling the inversion voltage are distributed shallower in the method of the present invention than in the conventional method. The depth of the depletion layer near the drain is near the source / drain diffusion layer (approx.
3 μm) of phosphorus ions. Therefore, when the boron ion distribution is shallow, the phosphorus concentration can be equivalently kept high, the breakdown voltage is high, and the inversion voltage does not deteriorate even in the short channel region.

As described above, the field effect semiconductor device having the following effects can be obtained by the method of the present invention.

(1) Since the gate insulating film 104 is formed before impurity ions are implanted into the semiconductor substrate 101, the crystallinity of the insulating film is good, and the withstand voltage and reliability are good.

(2) The step of controlling the inversion voltage by implanting boron after the formation of the gate insulating film 104 does not affect the concentration distribution of the impurity ions due to the formation of the gate insulating film 104, so that the control of the inversion voltage is easy and the manufacturing is easy. There is little variation.

(3) Even when the gate oxide film thickness deviates from the target value, re-oxidation is possible because the inversion voltage is not affected by the formation of the gate oxide film 104 at all. This is highly effective when mass-producing semiconductor devices.

In this embodiment, the polycrystalline silicon film 105 and the amorphous silicon film 106 are used as the gate electrode. However, if a metal such as molybdenum or tungsten, or a high melting point metal compound such as tungsten silicide is used for the gate electrode, Since a lower-resistance gate electrode can be formed, the speed of the integrated circuit can be increased.

Further, in this embodiment, it is deposited on the gate insulating film 104,
Since the amorphous semiconductor 106 forming a part of the gate electrode is used, the impurity ion-implanted for controlling the inversion voltage does not cause channeling, and a uniform impurity distribution can be obtained. Even if an amorphous conductor containing an amorphous metal such as amorphous tungsten is used instead of the amorphous semiconductor 106, channeling does not occur and a uniform impurity distribution can be obtained. Polysilicon films deposited at lower temperatures, for example
Since the polysilicon film deposited at 600 ° C. does not grow grains so much, the boundary between the grains becomes smaller than a polysilicon film deposited at 600 ° C. or more, for example, 700 ° C. Therefore, when boron is implanted at an implantation energy of 30 to 40 KeV, channeling can be prevented if the thickness of the polysilicon film deposited at about 600 ° C. is about 50 nm.

Usually, when boron is implanted with an implantation energy of 30 to 40 KeV, a silicon oxide film of about 50 nm is required to prevent channeling, and a gate oxide film of 10 to 15 nm is completely insufficient. However, when an amorphous conductor such as the amorphous semiconductor 106 is used, even if the thickness is small enough (10 to 15 nm) to sufficiently transmit the impurity for controlling the inversion voltage, the implanted impurity almost causes channeling. And a shallow and uniform impurity distribution can be obtained.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS. 2 (a) to 2 (e).
It will be described based on.

First, as in FIG. 1, a P-type silicon substrate 101 is thermally oxidized to form a gate oxide film 104 having a thickness of 10 to 15 nm.
The amorphous silicon film 106 is deposited. Next, in order to control the inversion voltage, impurity ions such as boron are added at 30 to 40 KeV for 3 hours.
Implant 〜5 × 10 ¹² cm ⁻² to form p ⁻ region 102 (FIG. 2a).

Next, after depositing a polycrystalline silicon film 105 of 150 to 250 nm and a silicon oxide film 108 of 100 to 150 nm on the amorphous silicon film 106, etching is performed using a photoresist 107 as a mask,
A silicon oxide film 108 is formed (FIG. 2B).

Next, using the silicon oxide film as a mask, the polycrystalline silicon film 105 is etched. At this time, the natural oxide film formed on the surface of the amorphous silicon film 106 functions as an etching stop.

Next, using silicon oxide film 108 as a mask, phosphorus is
An N ⁻ region 109 serving as a source / drain is formed by implanting 0 ¹³ cm ⁻² (FIG. 2c).

Next, after an oxide film is uniformly deposited again, the oxide film and the amorphous silicon film 106 are etched by self-alignment etching to form a gate sidewall 111. Silicon oxide film 111 and
Using 108 as a mask, arsenic is implanted at 4 to 7 × 10 ¹⁵ cm ⁻² to form N ⁺ -type source / drain 110 of the field effect transistor (FIG. 2d).

Thereafter, an interlayer insulating film 112 is deposited and an aluminum wiring 113 is formed by a normal MOS-type semiconductor manufacturing process (FIG. 2E).

As described above, according to the present embodiment, since the N ⁻ region 109 is located immediately below the gate electrode, high reliability and high driving force were obtained. In addition, a field effect semiconductor device in which the control of the inversion voltage is easy and the production variation is small is obtained.

Note that, similarly to the first embodiment, the polycrystalline silicon shown in FIG.
105 may be a metal such as molybdenum or tungsten, or a high melting point metal compound such as tungsten silicide. For example, if a gate is formed by etching tungsten silicide and used as a mask when phosphorus is ion-implanted, the silicon oxide film 108 as a mask becomes unnecessary. In this case, as in the first embodiment, a gate electrode having a lower resistance can be formed, and the speed of the integrated circuit can be increased.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIGS. 3 (a) to 3 (e).
It will be described based on. First, similarly to FIG. 1, after a P-type silicon substrate 101 is thermally oxidized to form a gate oxide film 104 of 100 to 150 nm, an amorphous silicon film 106 of 50 to 60 nm is deposited. (FIG. 3a).

Next, a 150-250 nm polycrystalline silicon film 105 and 100-150 nm
After the silicon oxide film is deposited, etching is performed using the photoresist 107 as a mask to form a silicon oxide film 108 (FIG. 3B).

Next, polycrystalline silicon 105 is etched using silicon oxide film 108 as a mask. At this time, amorphous silicon 103
The natural oxide film formed on the surface of the substrate functions as an etching stop.

Then, using the silicon oxide film 108 and the polycrystalline silicon 105 as a mask, boron is ion-implanted at a large angle of 40 to 45 ° to 100 to 1
The inversion voltage is controlled by injecting ² to 3 × 10 ¹² cm ⁻² at 20 KeV (FIG. 3c). When a silicon substrate having 100 planes is used, channeling becomes large when ions are implanted at 30 ° and 60 °. Therefore, about 45 ° is appropriate as the angle of large tilt ion implantation.

Next, using the silicon oxide film 108 as a mask,
X10 ¹³ cm ^{-2 is} implanted to form an N ^- region 109 serving as a source / drain. Next, after an oxide film is uniformly deposited again, the oxide film and the amorphous silicon 106 are etched by self-aligned etching to form a gate sidewall 111. Silicon oxide film 1
Using 11 and 108 as masks, arsenic is implanted at 4 to 7 × 10 ¹⁵ cm ^−2, and the N ⁺ type source / drain 11 of the field effect transistor is implanted.
0 is formed (FIG. 3d).

Thereafter, an interlayer insulating film 112 is deposited and an aluminum wiring 113 is formed by a normal MOS-type semiconductor manufacturing process (FIG. 3E).

In the Nch field-effect transistor obtained by this method, boron ions implanted for controlling the inversion voltage suppress the extension of the depletion layer of the source and drain, so that the inversion voltage does not deteriorate even in the short channel region, and Is suitable for Further, since boron ions for controlling the inversion voltage are ion-implanted using the gate electrode as a mask after the formation of the gate electrode, the concentration of the impurity ions in the center of the channel region becomes low, so that the driving force of the transistor is large.

As described above, the present invention facilitates control of the inversion voltage of a field-effect semiconductor, suppresses manufacturing variations, and greatly contributes to higher efficiency of semiconductor device manufacturing and miniaturization of elements. is there.

[Brief description of the drawings]

1A to 1E are cross-sectional views showing a method for manufacturing a field-effect semiconductor device according to a first embodiment of the present invention.
FIGS. 3A to 3E are cross-sectional views showing the steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention, and FIGS.
(E) is a process sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention, FIG. 4 is an impurity profile diagram by a three-dimensional process simulation, and FIG.
(D) is a process cross-sectional view illustrating a conventional method for manufacturing a semiconductor device. 101: P-type semiconductor substrate, 102: P-type semiconductor region, 103
... thermal oxide film, 104 ... gate oxide film, 105 ... polycrystalline silicon film, 106 ... amorphous silicon film, 107 ... photoresist, 108, 111 ... silicon oxide film, 109, 110 ... N-type semiconductor region, 112 ... interlayer insulation film, 113 ... aluminum wiring.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mizuki Segawa 1006 Oaza Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-1-243418 (JP, A) JP-A-63- 160276 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/336 H01L 29/78

Claims (1)

(57) [Claims] A step of forming a first insulating film serving as a gate insulating film on a semiconductor substrate; a step of forming a first conductor film on the first insulating film; Forming a second conductor film on the body film and patterning the second conductor film; and using the second conductor film as a mask through the first conductor film in the substrate. Implanting an impurity for controlling an inversion voltage by large-angle ion implantation at an angle of 40 to 45 degrees, and using the second conductor film as a mask through the first conductor film. Forming a first semiconductor region of a second conductivity type by implanting impurities in a substantially vertical direction into the substrate; and forming a spacer of a second insulating film left on a side wall of the second conductor film. And using the second conductor film and the spacer as a mask,
Forming a second semiconductor region of a second conductivity type by injecting impurities in a substantially vertical direction into the substrate, using the first and second conductor films as gate electrodes, A method for manufacturing a field-effect semiconductor device, wherein a second semiconductor region is used as a source and a drain.