JPS61131857U - - Google Patents

Info

Publication number
JPS61131857U
JPS61131857U JP1985014595U JP1459585U JPS61131857U JP S61131857 U JPS61131857 U JP S61131857U JP 1985014595 U JP1985014595 U JP 1985014595U JP 1459585 U JP1459585 U JP 1459585U JP S61131857 U JPS61131857 U JP S61131857U
Authority
JP
Japan
Prior art keywords
diffusion region
semiconductor substrate
electrode
variable capacitance
lead wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985014595U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985014595U priority Critical patent/JPS61131857U/ja
Publication of JPS61131857U publication Critical patent/JPS61131857U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案による可変容量ダイオードの断
面図、第2図は従来の可変容量ダイオードの断面
図である。 主な図番の説明、1は可変容量ダイオード、2
はN型のシリコン基板、3はN型のエピタキシ
ヤル層、4はリング状のP型の第1の拡散領域
、5は第2の拡散領域、6は薄いP型の拡散領
域、7は第1の絶縁膜、8は第2の絶縁膜、9は
Al電極、10はリード線、11はジヤケツトコ
ート膜である。
FIG. 1 is a sectional view of a variable capacitance diode according to the present invention, and FIG. 2 is a sectional view of a conventional variable capacitance diode. Explanation of main figure numbers, 1 is variable capacitance diode, 2
is an N + type silicon substrate, 3 is an N type epitaxial layer, 4 is a ring-shaped P + type first diffusion region, 5 is a second diffusion region, 6 is a thin P + type diffusion region, 7 is a first insulating film, 8 is a second insulating film, 9 is an Al electrode, 10 is a lead wire, and 11 is a jacket coat film.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一導電型の半導体基板と該半導体基板に形成し
た逆導電型の第1の拡散領域と該拡散領域上に形
成した電極と該電極上に形成したリード線とを具
備し空乏層の厚さを容量変化として検知する可変
容量ダイオードに於て、前記リード線接合部と対
応する半導体基板内に形成した第2の拡散領域と
、該第2の拡散領域と対応する前記電極内に形成
した絶縁膜とを具備することを特徴とした可変容
量ダイオード。
It includes a semiconductor substrate of one conductivity type, a first diffusion region of an opposite conductivity type formed on the semiconductor substrate, an electrode formed on the diffusion region, and a lead wire formed on the electrode. In a variable capacitance diode that detects a capacitance change, a second diffusion region formed in the semiconductor substrate corresponding to the lead wire junction, and an insulating film formed in the electrode corresponding to the second diffusion region. A variable capacitance diode comprising:
JP1985014595U 1985-02-04 1985-02-04 Pending JPS61131857U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985014595U JPS61131857U (en) 1985-02-04 1985-02-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985014595U JPS61131857U (en) 1985-02-04 1985-02-04

Publications (1)

Publication Number Publication Date
JPS61131857U true JPS61131857U (en) 1986-08-18

Family

ID=30499662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985014595U Pending JPS61131857U (en) 1985-02-04 1985-02-04

Country Status (1)

Country Link
JP (1) JPS61131857U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006294776A (en) * 2005-04-08 2006-10-26 Toko Inc Diode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006294776A (en) * 2005-04-08 2006-10-26 Toko Inc Diode

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