JPS61128630A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To apply direct AD conversion to a URR expression by DA-converting an output of a split point generating means of a section, comparing a converted output with an input signal and using the comparison output to control an output of the split point generating means. CONSTITUTION:A value generated from a split point generating means 1 generating a split point of the section is inputted to a DA converter 2, and the DA conversion output being an analog value corresponding to the split point and the input signal 101 are compared by a comparator 3. The output of the comparator 3 is inputted to a control circuit 4 to obtain a bit string of numerical expression method (URR) without overflow/underflow and the means 1 is controlled to generate the next split point. The operation is conducted sequentially to obtain the URR bit string as an output 102. Thus, the handling is much simplified in the application where an analog signal requiring a large dynamic range is converted to a digital signal.

Description

[Detailed Description of the Invention] r Q sE (+': Jll m G * 1 The present invention relates to an analog-to-digital converter (hereinafter abbreviated as ADC) K, and particularly has a large dynamic range, over 70- Under 71: This relates to an ADC that directly converts into a numerical representation in which I- does not occur.

[Background of the invention]

When AD converting a signal with a relatively large dynamic range, such as audio or images, it is necessary to perform AD conversion coarsely where the input signal is large and finely where it is small, expanding the dynamic range without increasing the number of bits. A companding method is used.

On the other hand, using the obtained image signal etc.,
When processing, etc., overflow in the middle of calculation o −
, Numerical Representation Method (URR) that does not produce under-70- (Information Processing Society of Japan Transactions Vol. 24).

Grave 2. p149-156, 1983). Conventional ADCs often have the disadvantage that because the ADC output is not in URR representation, it is necessary to add a special circuit to convert it into URa representation.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and provide an ADC that directly performs AD conversion into digital signals in UR and R representations.

[Summary of the invention]

In the present invention, in order to convert to U8 expression, division points are generated sequentially and the divisions are limited by comparing the division points with the input signal to obtain the necessary bit string.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to examples.

FIG. 1 shows a first embodiment. First, U.R.
8 is cited literature (Information Processing Society of Japan Journal Vol24゜A2.
p149-156.1983).

That is, any value '1u in the interval corresponding to the bit string S
(S), and the concatenation of bit 0 to the right of S is S
The concatenation of O and bit 1 is expressed as 81, and the distinction is divided in the following four steps.

(a) Rough division One flash ≦ u (100) (-2 -2≦u(101)(-1 -1≦u(110)(-0,5 −0,5<, u (111) (0 0≦u(000)<0.5 0.5≦u　(001)(1 1≦u　(0103<2 2≦u　(0111(Flash) (b) Double exponential division 22”?: Set as a dividing point.

(C) Geometric division a≦u (81(b'''c' when a≦u(SO) (aV17) - av'F;'7 d≦u (81) (b (d) Arithmetic division a <u(S)(b then a≦u (80) <(a+b l/2(a+bl
/2<u(f131)<b The above divisions are performed sequentially, and the real value is expressed as a pix string representation URR.

Therefore, as shown in FIG.
01 by the comparator 3, input the comparator output to the control device 4, obtain a bit string of UR8 display, and
The division point generating means is controlled to generate the next division point, and this operation is sequentially performed to obtain the bit string of UR as the output 102.

Next, the division point generating means 1 will be specifically explained using FIG. 2.

Here, for simplicity, we will consider positive numbers. First, regarding double exponential division, the division points are 22°, specifically 22, 24, 28, 216°, 232, .
...However, in the case of an AD converter, inertia is also involved, and a value of 216 or more is meaningless. So the dividing point is 2
164 is sufficient for practical use. Rough division point 7
Since only 6 points and 6 dividing points (plus and minus) are needed for double exponential division, these dividing points are stored in the soft device 10 as shown in FIG. 2, and sequentially input to the DA converter 2. All that is required is to compare the DA conversion output (analog value corresponding to the division point) and the input using the comparator 3 to determine the classification.

Going further, we perform geometric division, which can be done by narrowing the range by sequentially dividing the division points by 1/2, and 1/2 of the division points can be shifted by 1 bit in a binary code. This can be easily done using the shift register 51.

Proceeding further and moving to arithmetic division, a≦u (S) (b
, then divide by (a + b) / 2 and get a≦
u (80) ((a+b)/2 (a+b )/2<u (S 1 )(b is obtained, but (
a + b ) / 2 can be realized by an adder 52 and a shift register 51, and a temporary storage device 53 may be used to store a and b.

The consideration device 1, the address of the temporary storage device, the shift of the shift register, etc. are controlled by the control device 4.

Note that the register 54 temporarily holds the signal input to the DA converter 2, and can be omitted by adjusting the timing appropriately. Further, switches 61 and 62 are used to switch according to each division method.

In the above-mentioned embodiment, the division points of the double exponential division are stored in the first device, but the bits 1, 1, 2, 4, etc.
, 8.16, and by 21, so it may be generated by such means.

Furthermore, a second embodiment is shown in FIG. This corresponds to a large dynamic range, and has an attenuator 6 placed at the input 101. (a) Rough division and (b)
) In double exponential division, if there is a large input greater than a certain value, the input is attenuated according to the division point, rather than obtaining a corresponding DA conversion output. This makes it possible to handle inputs larger than the output that the DA converter 2 can generate.

〔Effect of the invention〕

According to the present invention, AD conversion can be performed directly to U multiplication representation without overflow or under 70-, so there is no need for a special circuit for conversion to U multiplication representation, which requires a large dynamic range. This makes handling extremely easy in the field of converting analog signals into digital signals. Further, according to the present invention, it is possible to implement a mono-I77 IC without requiring any special parts, and the economic effect is also great.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the concept of the invention, FIG. 2 is a diagram showing a specific embodiment of the invention, and FIG. 3 is a diagram showing a third embodiment. 1... Division point generating means, 2... DA converter, 3...
-Comparator, 4...control device. ll third country

Claims (1)

[Scope of Claims] 1. A means for generating a dividing point of a division, a DA converter that receives the output of the generating means as an input, a comparator that compares the OA conversion output with an input signal, and the comparator. An AD converter comprising a control device for controlling the output of the dividing point generating means according to the output, and obtaining a bit string corresponding to the input signal by sequentially limiting the division to which the input signal belongs. 2. The AD converter according to claim 1, wherein the division point generating means comprises a storage device, an adder, a shift register, and a temporary storage device. 3. If the category to which the input signal belongs is larger than a certain value,
2. The AD converter according to claim 1, wherein the input signal is attenuated by an attenuator.