JPH04340814A - A/d converter having variable characteristic - Google Patents

Abstract

PURPOSE:To attain speed-up and simplification in the arbitrary change of an A/D conversion characteristic, and to attain cost reduction. CONSTITUTION:A comparator 24 compares an input analog voltage VO impressed on an analog input terminal 34, with a comparison reference analog value VDA outputted from a D/A conversion circuit 22, and outputs the compared result to a conversion control circuit 20. The conversion control circuit 20 successively updates the comparison reference analog value VDA to be transferred and set to the D/A conversion circuit 22, based on the input result from the comparator 24. Plural reference point registers 26 are provided so that a preset input can be operated as the original data of the successive update of the comparison reference analog value VDA. The conversion control circuit 20 selects the reference point register 26 to read, based on the compared result from the comparator 24, and the comparison reference analog value VDA obtained from the selected reference point register 26 is set to the D/A conversion circuit 22.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable characteristic A/D converter which varies the conversion characteristic when converting an analog signal into digital data.

0002

[Prior Art] FIG. 3 shows a conventional variable characteristic A/D of this type.
FIG. 2 is a block circuit diagram showing a converter.

In the figure, 2 is a conversion control circuit (successive approximation register), 4 is a D/A conversion circuit, 6 is a comparator,
8 is an A/D converter, 10 is an analog input terminal, 12
1 is a digital data output terminal, and 14 is a characteristic variable filter.

[0004] Now, to simplify the explanation, it is assumed that the number of bits of the A/D converter 8 is 3 bits. Also, consider the operation of only the A/D converter 8 without the characteristic variable filter 14.

When the A/D converter 8 is instructed to start A/D conversion, the conversion control circuit 2 first sends the D/A converter 4 3-bit data "100" with only the most significant digit being 1. " is output. This is D/A conversion circuit 4
It is converted into an analog value "4" and input to the comparator 6 as a comparison standard.

The input analog voltage V1 applied to the analog input terminal 10 is compared with a comparison reference analog value "4", and if V1≧4, the comparator 6 outputs "H" to the conversion control circuit 2. Also, if V1 < 4,
Comparator 6 outputs "L" to conversion control circuit 2.

[0007] Here, the input analog voltage V1 is 5.3
The case where the voltage is [V] and the case where the voltage is 2.7 [V] will be explained in parallel.

[0008] When V1 = 5.3, comparator 6
The output becomes "H", and the most significant bit (MSB) in the conversion control circuit 2 is determined to be "1". V1=2.7
At this time, the output of the comparator 6 becomes "L", and the most significant bit (MSB) in the conversion control circuit 2 is switched to "0" and determined.

Next, the conversion control circuit 2 outputs 3-bit data with the second most significant bit (2thB) set to "1". When V1 is 5.3 [V] which applies to 4, the 3-bit data output from the conversion control circuit 2 is “110
”, and this is the analog value “6” in the D/A conversion circuit 4.
is converted to Also, 2.7 [applicable to V1 < 4]
V], the 3-bit data output from the conversion control circuit 2 becomes "010", which is converted by the D/A conversion circuit 4 into an analog value "2".

When V1 = 5.3, the comparison reference analog value is "6", so the output of comparator 6 is "L".
”, and the second most significant bit (2
thB) is switched to "0" and confirmed. V1=
When the value is 2.7, the comparison reference analog value is "2", so the output of the comparator 6 becomes "H", and the second upper bit (2thB) in the conversion control circuit 2 is determined to be "1".

Next, the conversion control circuit 2 sets the third upper bit (3thB), that is, the least significant bit (LSB) to "1".
” and outputs 3-bit data. When V1 is 5.3 [V] which applies to 4, the 3-bit data output from the conversion control circuit 2 is "101", which is the D/
It is converted into an analog value "5" by the A conversion circuit 4. Also,
When the voltage is 2.7 [V], which applies to V1 < 4, the 3-bit data output from the conversion control circuit 2 becomes "011", which is converted by the D/A conversion circuit 4 into an analog value "3".

When V1 = 5.3, the comparison reference analog value is "5", so the output of the comparator 6 is "H".
”, and the least significant bit (LS
B) is determined to be "1". When V1 = 2.7, the comparison reference analog value is "3", so comparator 6
The output becomes "L", and the least significant bit (LSB) in the conversion control circuit 2 is switched to "0" and determined.

[0013] Since the successive approximation of all three bits is completed in the above manner, the A/D conversion operation is completed.
The 3-bit data output from the conversion control circuit 2 is V1
When =5.3, it is determined to be "101" (=5), and this is output from the digital data output terminal 12. Furthermore, when V1 = 2.7, the 3-bit data output from the conversion control circuit 2 is determined to be "010" (=2),
This is output from the digital data output terminal 12.

The above is an explanation of an example of the A/D conversion operation when the characteristic variable filter 14 is not provided.

The characteristic variable filter 14 is used for the purpose of changing A/D conversion characteristics.

That is, the original input analog voltage V0 is changed to the input analog voltage V1 to the analog input terminal 10.
The voltage is converted non-linearly. An example of the voltage-voltage conversion characteristic is illustrated inside the block showing the characteristic variable filter 14. Taking the above example, for example, when V0 = 3, it is converted to V1 = 5.3,
For example, when V0 = 1, it is converted to V1 = 2.7.

[0017]

However, in the conventional variable characteristic A/D converter in which the characteristic variable filter 14 is added to the A/D converter 8 as described above,
In order to change the A/D conversion characteristics, the variable characteristic filter 14 must be replaced with another filter having different voltage-to-voltage conversion characteristics, which is a hassle.

[0018] Furthermore, in order to obtain a large number of A/D conversion characteristics,
A large number of characteristic variable filters 14 are required, leading to an increase in cost.

The present invention was devised in view of the above circumstances, and eliminates the need for parts replacement when changing A/D conversion characteristics, making it possible to quickly and easily change characteristics, and reducing costs. Variable characteristic A that can achieve
/D converter.

[0020]

[Means for solving the problem] Variable characteristic A according to the present invention
The /D converter includes a comparator that compares the input analog voltage applied to the analog input terminal with a comparison reference analog value output from the D/A conversion circuit, and a comparator that compares the input analog voltage applied to the analog input terminal with a comparison reference analog value output from the D/A conversion circuit, and the D/A conversion based on the input state from the comparator. A variable characteristic A/D converter comprising a conversion control circuit that sequentially updates a comparison reference analog value to be transferred and set to a circuit, the comparison reference being read by the conversion control circuit and transferred to the D/A conversion circuit. The present invention is characterized by providing a plurality of reference point registers that can be externally preset to arbitrary values as analog values, and two sub-reference point registers that interpolate between the reference point registers.

[0021]

[Operation] Since any comparison standard analog value can be freely preset for the reference point register, A
When changing the /D conversion characteristic, there is no need to change the characteristic variable filter as in the conventional example, and it is only necessary to change the input value.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the variable characteristic A/D converter according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block circuit diagram showing a variable characteristic A/D converter according to an embodiment.

In the figure, 20 is a conversion control circuit, 22 is a D/A conversion circuit, 24 is a comparator, 26 is a reference point register, 28 is a preset/conversion terminal, 30 is a start terminal, 32 is a status terminal, and 34 is an analog Input terminal, 36 is digital data input/output terminal, 38 is variable characteristic A/D converter, 39 is sub-reference point register A, 40
is the sub reference point register B.

The two input terminals of the comparator 24 are:
The analog input terminal 34 and the output terminal of the D/A conversion circuit 22 are connected. The output terminal of the comparator 24 is connected to the conversion control circuit 20. The conversion control circuit 20, the plurality of reference point registers 26, the sub-reference point register B and the D/A conversion circuit 22 are connected to each other by a plurality of bit signal lines. In addition, the preset/conversion terminal 28
, a start terminal 30, a status terminal 32, and a digital data input/output terminal 36 are also connected to the conversion control circuit 20. And, with the above connection structure,
This constitutes the entire variable characteristic A/D converter 38.

In the conversion control circuit 20, the preset/conversion terminal 28 is set to "H" level, and the start terminal 30 is set to the "H" level.
is set to “H” level, digital data input/
The reference point setting value set by the external reference point setting key is read through the output terminal 36 and is stored in the reference point register 2.
It is configured to be preset to 6. There are a plurality of reference point registers 26, and reference point setting values can be individually preset for each reference point register 26.

The conversion control circuit 20 also controls preset/
While the conversion terminal 28 is at the "L" level, the start terminal 30 is at the "H" level and the status terminal 32 is at the "L" level.
It is configured to start an A/D conversion operation when the level becomes L''.

The basic A/D conversion function of the conversion control circuit 20 is to read the reference point setting value from the reference point register 26 and transfer it to the D/A conversion circuit 22.
The comparison reference analog value obtained in is compared with the input analog voltage V0 in the comparator 24. According to the result, the reference point register 26 from which the reference point setting value is to be read is determined as appropriate, and the above operation is repeated. and from the reference point register 26 to the sub reference point register A39,
Copying the value to the sub-reference point register B40 and transferring the average value of the two sub-reference point registers to the D/A conversion circuit 22,
The comparison reference analog value obtained by the /A conversion circuit 22 is compared with the input analog voltage VO in the comparator 24. Depending on the result, either the sub-reference point register A39 or the sub-reference point register B40 is updated to the above average value. Then, the above operations on the sub-reference registers are repeated until the desired data is obtained.

The conversion control circuit 20 outputs digital data as the final result of A/D conversion from the digital data input/output terminal 36. The number of bits of the digital data is L bits, and the number of reference point registers 26 is set as L bits. If N is an integer (2N +1) and the number of bits processed by the D/A conversion circuit 22 is M bits, there is a relationship between L, N, and M of M≧L≧N. Reference point register 26
The number of bits of each bit and the number of bits of the sub-reference point register A39 and sub-reference point register B40 are also M bits.

Next, the operation of the variable characteristic A/D converter 38 having the above configuration will be explained.

[1] Registration of reference point setting value When the preset key connected to the preset/conversion terminal 28 is pressed,
Preset/conversion terminal 28 becomes "H" level. Next, a reference point setting value is set using a reference point setting key (not shown) connected to the digital data input/output terminal 36. Then, by pressing the setting start key, the start terminal 30 becomes "H" level. As a result, the conversion control circuit 20 sequentially reads a plurality of reference point setting values set by the reference point setting keys and registers them in the corresponding reference point register 26.

Here, in order to simplify the explanation, for example, let us assume that N=3 and calculate the number of reference point registers 26 (2N +1
) are 9 pieces. It is also assumed that the number of bits of digital data output from the conversion control circuit 20 is L=5.

Assume that the reference point setting values registered in the nine reference point registers 26 are, for example, as follows (in this regard, the conversion characteristics shown in FIG. 2 can be referred to).

Register number No. 1 N
o. 2 No. 3 No. 4 Reference point setting value 0.25 0.30
0.35 0.45 register number
No. 5 No. 6 No.
7 No. 8 Reference point setting value
0.65 1.05 1.85
3.0 Register number No. 9
Reference point setting value 5.0 [2] A/
When the A/D conversion start key is pressed when the presetting of the D conversion operation reference point set value is completed and the preset/conversion terminal 28 is at the "L" level, the start terminal 30 becomes the "H" level and the status terminal 32 becomes "L" level. As a result, the conversion control circuit 20 starts an A/D conversion operation.

■ Determination of the most significant bit (MSB) of the 5-bit data D5 The conversion control circuit 20 first determines the (2N-1 +1)th,
That is, when N=3, the fifth reference point register 26
The reference point setting value "0.65" registered in is read out, transferred to the D/A conversion circuit 22, and set. The reference point setting value at this time is actually binary digital data expressed as 0 and 1, but for convenience, it is expressed as "0.65". The D/A conversion circuit 22 converts this digital data into a comparison reference analog value VDA=“0.65” and outputs it to the comparator 24.

FIG. 2 shows the conversion characteristics between the register number of the reference point register 26 and the comparison reference analog value VDA by the D/A conversion circuit 22. As mentioned above, for example, if the register number is No. When it is 1, VDA is 0.2
It is 5. When written horizontally, N
o. 1=0.25, No. 2=0.30, No
．． 3=0.35, No. 4=0.45, No.
5=0.65, No. 6=1.05, No. 7
=1.85, No. 8=3.0, No. 9=5
．． It is 0.

Comparator 24 connects analog input terminal 3
The input analog voltage V0 input from 4 is compared with the comparison reference analog value VDA, and when V0 ≧VDA, an “H” level is output to the conversion control circuit 20, and V0
<When it is VDA, it outputs “L” level.

Below, as a specific example, input analog voltage V
0 is 4.5 [V] (A), 1.0 [V] (B), 0.73 [V] (C), and 0.27
[V] case (D) will be explained in parallel.

(A) Input analog voltage V0 = 4.5 [
V], the initialized No. Since the comparison reference analog value VDA of No. 5 is 0.65 [V], V0 ≧VD
A, and the comparator 24 outputs the "H" level. When the conversion control circuit 20 receives the "H" level from the comparator 24, it fixes the bit that is currently being determined to "1". We are currently trying to determine the most significant bit (MSB), so (
MSB)=1, and the most significant bit (MSB) of the 5-bit data D5 that the conversion control circuit 20 is going to finally output is set to "1". That is, D5=
Set it to 1xxxxx. Note that x can take either "0" or "1" here, but it is currently undetermined.

(B) Input analog voltage V0 = 1.0 [
V], No. 5, VDA=0.65 [V], V0≧VDA, and the comparator 24 outputs the "H" level. Similarly to the above, the conversion control circuit 20 determines the most significant bit (MSB)=1 and sets the 5-bit data D5=1xxxx.

(C) Input analog voltage V0 = 0.73
In the case of [V], No. 5, VDA=0.65 [V], V0 ≧VDA, and the comparator 24
outputs “H” level. Similarly to the above, the conversion control circuit 20 determines the most significant bit (MSB)=1 and sets the 5-bit data D5=1xxxx.

(D) Input analog voltage V0 = 0.27
In the case of [V], No. 5, VDA=0.65 [V], V0 < VDA, and the comparator 24
outputs “L” level. Contrary to the above, the conversion control circuit 20 determines the most significant bit (MSB)=0 and sets the 5-bit data D5=0xxxx.

■ Determination of the second most significant bit (2thB) of the 5-bit data D5 The conversion control circuit 20 then determines ((2N-1×(MS
B) Read the +2N-2 +1)-th reference point setting value registered in the reference point register 26, that is, the (4×(MSB)+3)-th when N=3, and send it to the D/A conversion circuit 22. Transfer and set. Here, (MSB) is “1”
” or “0”.

(A) Input analog voltage V0 = 4.5 [
V], the reference point register 26 to be read is No. 1 because (MSB)=1 as in (A) of (2) above.
7, and its No. The comparison reference analog value VDA read from the reference point register 26 of No. 7 and set in the D/A conversion circuit 22 is VDA=1.85 [V]. In this case, compared to V0 = 4.5 [V], V0 ≧V
The comparator 24 outputs "H" level. When the conversion control circuit 20 receives the “H” level from the comparator 24, the conversion control circuit 20 sets the second upper bit (2thB), which is the bit that is currently being determined, to (2thB)=
1, and the second most significant bit (2t
hB) is set to “1”. Since the most significant bit (MSB) has already been determined and is "1", the 5-bit data D5 is eventually set as D5 = 11xxx.

(B) Input analog voltage V0 = 1.0 [
In the case of [V], as in (A), (MSB) = 1, so the reference point register 26 to be read is No. 7
Since the comparison reference analog value VDA=1.85 [V], this time, V0<VDA, and the comparator 24 outputs the "L" level. Therefore, the conversion control circuit 20 determines that the second upper bit (2thB)=0 and sets the 5-bit data D5=10xxx.

(C) Input analog voltage V0 = 0.73
In the case of [V], as in (A), (MSB)=1, so the reference point register 26 to be read is No.
7, and the comparison reference analog value VDA = 1.85 [V]
Therefore, V0 < VDA and comparator 2
4 outputs "L" level. Therefore, the conversion control circuit 20 determines that the second most significant bit (2thB) = 0,
Set 5-bit data D5 = 10xxx.

(D) Input analog voltage V0 = 0.27
In the case of [V], (MSB) = 0, so (4 x (
MSB)+3)th reference point register 26 is N
o. This means that there are 3 registers. At this time, the comparison reference analog value VDA=0.35 [V], so V0
<VDA, and the comparator 24 outputs "L" level. Therefore, the conversion control circuit 20
The bit (2thB) is determined to be 0, and the 5-bit data D
5 Set =00xxx.

■ Determination of the third upper bit (3thB) of the 5-bit data D5 The conversion control circuit 20 then determines ((2N-1×(MS
B) +2N-2 × (2thB) +2N-3 +1)th, that is, when N = 3, (4 × (MSB) + 2 ×
The reference point setting value registered in the (2thB)+2)th reference point register 26 is read out, and the D/A conversion circuit 2
Transfer to 2 and set. Here, (MSB) and (2t
Needless to say, each of hB) takes either "1" or "0".

(A) Input analog voltage V0 = 4.5 [
V], as mentioned above, (MSB) = 1, (2th
Since B)=1, the reference point register 2 to be read is
6 is no. 8, and its No. 8 reference point register 2
The comparison reference analog value VDA read from 6 and set in the D/A conversion circuit 22 is VDA=3.0 [V].

In this case, when compared with V0 = 4.5 [V], V0≧VDA and the comparator 24 becomes “H”.
When the conversion control circuit 20 receives the “H” level from the comparator 24, the conversion control circuit 20 outputs the third upper bit (3thB), which is the bit that is currently being determined.
) is determined to be (3thB)=1, and the 5-bit data D5 that the conversion control circuit 20 is finally going to output is set to D5=111xx.

(B) Input analog voltage V0 = 1.0 [
V], since (MSB)=1 and (2thB)=0, the reference point register 26 to be read is No. 6
Therefore, the comparison reference analog value VDA=1.05 [V], so V0 < VDA, and the comparator 24
outputs “L” level. Therefore, the conversion control circuit 20 determines that the third upper bit (3thB)=0, and
Set bit data D5 = 100xx.

(C) Input analog voltage V0 = 0.73
In the case of [V], since (MSB)=1 and (2thB)=0, the reference point register 26 to be read is No.
6, comparison reference analog value VDA = 1.05 [V]
Therefore, V0 < VDA and comparator 2
4 outputs "L" level. Therefore, the conversion control circuit 20 determines that the third upper bit (3thB) = 0,
Set 5-bit data D5 = 100xx.

(D) Input analog voltage V0 = 0.27
In the case of [V], since (MSB)=0 and (2thB)=0, the reference point register 26 to be read is No.
2, and the comparison reference analog value VDA=0.30, so V0 < VDA, and the comparator 24 outputs “
outputs L” level. Therefore, the conversion control circuit 20
The third upper bit (3thB) is determined to be 0, and the 5-bit data D5 is set to 000xx.

[0054] By repeating the above operation N times,
The upper N bits of the 5-bit data D5 are determined. Since N=3 in this example, processing ends with steps 1 to 2, and the upper 3 bits are now determined.

The remaining (L-N) bits, that is, in this example, the remaining (5-3)=2 bits are determined as follows.

■ Determination of the fourth upper bit (4thB) of the 5-bit data D5 The conversion control circuit 20 then determines ((2N-1×(MS
B) +2N-2 × (2thB) +2N-3 × (3t
hB) + +20 × (NthB) + 1)th (temporarily assume this is the Z-th) reference point setting value registered in the reference point register 26, and ((2N-1 × (MSB) +
2N-2 × (2thB) + 2N-3 × (3thB)
+‥‥+20×(NthB)+2)th (i.e.,
This is the (Z+1)th) reference point setting value registered in the reference point register 26, and copy both reference points to the sub-reference point register A39 and sub-reference point register B40, and set both reference points. The average value VAVE4 of the values is calculated, and this average value VAVE4 is further applied to the D/A conversion circuit 22.
Transfer to and configure.

When N=3, the above Z=((22×(
MSB) + 21 × (2thB) + 20 × (3thB
)+1)=(4×(MSB)+2×(2thB)+(3
thB)+1).

(A) Input analog voltage V0 = 4.5 [
V], as mentioned above, (MSB) = 1, (2th
Since B)=1 and (3thB)=1, the Zth and (Z+1)th reference point registers 26 to be read are No. 8 and no. It becomes 9. No. 8, No. The nine reference point registers are copied to the sub-reference point register A39 and sub-reference point register B40, respectively. As a result, the value of the sub-reference point register A39 is 3.0 [V], and the value of the sub-reference point register B40 is 5.0 [V], so the average value VAV
E4=(3.0+5.0)/2=4.0. This average value VAVE4 is used as the comparison reference analog value VDA.
It is transferred to the A conversion circuit 22 and set. That is, V
DA=VAVE4=4.0.

Since the input analog voltage V0 = 4.5 [V], V0 ≧VDA, and the comparator 24
outputs “H” level, so the conversion control circuit 20
The upper 4th bit (4thB), which is the bit that is currently being determined, is determined as (4thB) = 1, and the 5-bit data D5 that the conversion control circuit 20 is going to finally output is set as D5 = 1111x. .

(B) Input analog voltage V0 = 1.0 [
V], (MSB)=1, (2thB)=0, (3
thB)=0, the Z-th and (Z+1)-th reference point registers 26 to be read are No. 5 and N
o. It becomes 6. No. 5, No. The 6 reference point registers are sub-reference point register A39 and sub-reference point register B, respectively.
Copied to 40. As a result, the value of the sub-reference point register A39 is 0.65 [V], and the value of the sub-reference point register B40 is 0.65 [V].
Since the value is 1.05 [V], the average value VAVE4=
(0.65+1.05)/2=0.85. This average value VAVE4 is used as the comparison reference analog value VDA.
It is transferred to the A conversion circuit 22 and set. That is, V
DA=VAVE4=0.85.

Since the input analog voltage V0 = 1.0 [V], V0 ≧VDA, and the comparator 24
outputs “H” level. Therefore, the conversion control circuit 20 determines that the upper 4th bit (4thB)=1, and
Set bit data D5 = 1001x.

(C) Input analog voltage V0 = 0.73
In the case of [V], (MSB) = 1, (2thB) = 0, (
3thB)=0, the Z-th and (Z+1)-th reference point registers 26 to be read are No. 5 and no. It becomes 6. No. 5, No. The six reference point registers are copied to the sub-reference point register A39 and sub-reference point register B40, respectively. As a result, the average value V
AVE4=0.85. This average value VAVE4 is transferred to the D/A conversion circuit 22 and set as the comparison reference analog value VDA. That is, VDA=VAVE4=
It is 0.85.

[0063] Input analog voltage V0 = 0.73 [V]
Therefore, in this case, V0<VDA, and the comparator 24 outputs the "L" level. Therefore, the conversion control circuit 20 calculates that the fourth upper bit (4thB)=
0 and set 5-bit data D5 = 1000x.

(D) Input analog voltage V0 = 0.27
In the case of [V], (MSB) = 0, (2thB) = 0, (
3thB)=0, the Z-th and (Z+1)-th reference point registers 26 to be read are No. 1 and no. It becomes 2. No. 1.No. The two reference point registers are copied to the sub-reference point register A39 and sub-reference point register B40, respectively. As a result, sub reference point register A39
The value of is 0.25 [V], and the sub reference point register B40
Since the value of is 0.30 [V], the average value VAVE4=
(0.25+0.30)/2=0.275. This average value VAVE4 is used as the comparison reference analog value VDA.
/A conversion circuit 22 and set. That is,
VDA=VAVE4=0.275.

Input analog voltage V0 = 0.27 [V]
Therefore, V0 < VDA, and comparator 2
4 outputs "L" level. Therefore, the conversion control circuit 20 determines that the fourth upper bit (4thB) = 0,
Set 5-bit data D5 = 0000x.

■ Determination of the upper 5th bit (5thB) of the 5-bit data D5, that is, the least significant bit (LSB) The conversion control circuit 20 determines (4th
thB) = 1, the sub reference point register B40 and the above average value VA are used as a reference in the process of
Using VE4 as a new standard, these average values VAVE
5 is calculated, VAVE4 is copied to the sub-reference point register A39, and this average value VAVE5 is further transferred to and set in the D/A conversion circuit 22.

[0067] Also, in the process of (2) above, (4thB
) = 0, the sub reference point register A39 and the above average value VAVE4 are used as a reference in the process of
Using this as a new standard, calculate these average values VAVE5, copy VAVE4 to the sub reference point register A39,
Furthermore, this average value VAVE5 is transferred to and set in the D/A conversion circuit 22.

That is, the sub-reference point register A39 or the sub-reference point register B40 is selected so that the input analog voltage V0 can be sandwiched between the input analog voltage V0 and the average value VAVE5.

(A) Input analog voltage V0 = 4.5 [
V], (4thB) = 1, so the reference point setting value 5.0 [V] of the sub reference point register B40 and the average value V
Average value of AVE4=4.0 [V] VAVE5=(5.
0+4.0)/2=4.5 is calculated and VAVE4 is copied to the sub reference point register A39. In other words, since (4thB)=1, the average value VAVE4
This means that the sub reference point register B40 having a reference point setting value greater than =4.0 [V] is selected. Then, the average value VAVE5 is transferred to the D/A conversion circuit 22 and set as the comparison reference analog value VDA. That is, VDA=VAVE5=4.5.

Since the input analog voltage V0 = 4.5 [V], V0 = VDA, and the comparator 24
outputs “H” level, so the conversion control circuit 20
The upper 5th bit (5thB), which is the bit that is currently being determined, is determined as (5thB) = 1, and the 5-bit data D5 that the conversion control circuit 20 is going to finally output is set as D5 = 11111. .

If the input analog voltage V0 is 4
．． If it was 4.49 [V] instead of 5 [V], then D
5=11110.

(B) Input analog voltage V0 = 1.0 [
In the case of (4thB)=1, the average value VAVE5= of the reference point setting value 1.05[V] of the sub-reference point register B40 and the average value VAVE4=0.85[V]
(1.05+0.85)/2=0.95 and VA
Copy VE4 to the sub reference point register A39. In other words, since (4thB)=1, No. 1 with a reference point setting value larger than the average value VAVE4=0.85 [V]. This means that reference point register 26 of No. 6 is selected. And the average value VAVE5
is the comparison reference analog value VDA in the D/A conversion circuit 22.
will be transferred to and set. That is, VDA=VAVE
5=0.95.

Since the input analog voltage V0 = 1.0 [V], V0 ≧VDA, and the comparator 24
outputs “H” level. Therefore, the conversion control circuit 20 determines that the fifth upper bit (5thB)=1, and
Set bit data D5 = 10011.

If the input analog voltage V0 is 1
．． If it was 0.94 [V] instead of 0 [V], then D
5=10010.

(C) Input analog voltage V0 = 0.73
In the case of [V], since (4thB)=0, the average value VAVE5= of the reference point setting value 0.65 [V] of the sub reference point register A39 and the average value VAVE4=0.85 [V]
(0.65+0.85)/2=0.75 and VA
Copy VE4 to sub reference point register B40. In other words, since (4thB) = 0, the sub reference point register A39 with a reference point setting value smaller than the average value VAVE4 = 0.85 [V] is selected. That's true. Then, the average value VAVE5 is transferred to the D/A conversion circuit 22 and set as the comparison reference analog value VDA. That is, VDA=VAVE5=0.75.

Input analog voltage V0 = 0.73 [V]
Therefore, V0 < VDA, and comparator 2
4 outputs "L" level. Therefore, the conversion control circuit 20 determines that the fifth upper bit (5thB) = 0,
Set 5-bit data D5 = 10000.

If the input analog voltage V0 is 0
．． If it were 0.76 [V] instead of 73 [V],
D5=10001.

(D) Input analog voltage V0 = 0.27
In the case of [V], since (4thB) = 0, the average value VAVE5 of the reference point setting value 0.25 [V] of the sub reference point register A39 and the average value VAVE4 = 0.275 [V]
=(0.25+0.275)/2=0.2625 is calculated and VAVE4 is copied to the sub reference point register B40. In other words, since (4thB) = 0, the sub reference point register A39 with a reference point setting value smaller than the average value VAVE4 = 0.275 [V] is selected. That's true. And the average value VA
VE5 is transferred to the D/A conversion circuit 22 and set as the comparison reference analog value VDA. That is, VDA=V
AVE5=0.2626.

Input analog voltage V0 = 0.27 [V]
Therefore, V0 ≧VDA, and comparator 2
4 outputs "H" level. Therefore, the conversion control circuit 20 determines that the fifth upper bit (5thB) = 1,
Set 5-bit data D5 =00001.

If the input analog voltage V0 is 0
．． If it were 0.26 [V] instead of 27 [V],
D5=00000.

As described above, the 5-bit data D5
Since up to the least significant bit (LSB) has been determined, the conversion control circuit 20 ends the A/D conversion operation. Then, the conversion control circuit 20 finally determines the 5-bit data D.
5 is outputted to the digital data input/output terminal 36 consisting of five lines, and the status terminal 32 is set to the "H" level.

[0082]

As described above, according to the present invention, any comparison standard analog value can be freely preset in the reference point register, so that when changing A/D conversion characteristics, it is possible to preset the reference point register as desired. Unlike the example, there is no need to worry about replacing filters for variable characteristics, and all you have to do is change the input values. That is, characteristics can be changed quickly and easily. Further, since any value can be selected as the reference point setting value, it is possible to provide an extremely wide variety of A/D conversion characteristics. However, there is no need to increase costs, and in fact, it is possible to promote cost reductions.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing a variable characteristic A/D converter according to an embodiment of the present invention.

FIG. 2 is a conversion characteristic diagram between a register number of a reference point register and a comparison reference analog value by a D/A conversion circuit according to the embodiment.

[Figure 3] Variable characteristic A using a conventional characteristic variable filter
FIG. 2 is a block circuit diagram showing a /D converter.

[Explanation of symbols]

20 Conversion control circuit 3
4 Analog input terminal 22 D/A conversion circuit 36
Digital data input/output terminal 24 Comparator 3
8 Variable characteristic A/D converter 26 Reference point register 39
Sub-reference register A 28 Preset/conversion terminal 40
Sub-reference register B 30 Start terminal V
0 Input analog voltage 32 Status terminal VD
A Comparison reference analog value

Claims (1)

[Claims] 1. A comparator that compares an input analog voltage applied to an analog input terminal with a comparison reference analog value output from a D/A conversion circuit; A variable characteristic A/D converter comprising a conversion control circuit that sequentially updates a comparison reference analog value to be transferred and set to a circuit,
a plurality of reference point registers capable of externally presetting arbitrary values as comparison reference analog values read by the conversion control circuit and transferred to the D/A conversion circuit; and two sub-references for interpolating between the reference point registers. A variable characteristic A/D converter characterized by being provided with a point register.