JPH0322710A - Parallel comparison type a/d converter - Google Patents

Abstract

PURPOSE:To simplify the constitution and suppress glitch generation by providing an AND gate block which controls an encoder for high-order bits and plural AND gate blocks which control an encoder for low-order bits. CONSTITUTION:The AND gate block 9 for high-order bit control and AND gate blocks 11 and 12 for low-order bit control are provided. Then the AND gate 9 for high-order bit control selects a specific comparator block corresponding to an analog input signal level to control the encoder 10 for high-order bits and the 1st-Nth AND gate blocks 11 and 12 for low-order bit control the encoder 13 for low-order bit. Consequently, the glitch generation can be suppressed with the wimple constitution.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a parallel comparison type A/D converter, and in particular to an L S
I (Large Scale Integrate
d circuit) and is suitable for, for example, 50M
A high-definition television signal that requires high-speed operation of Hz or higher
The present invention relates to a parallel comparison type A/D converter that performs /D conversion.

[Summary of the invention]

A parallel comparison type A/D converter of the present invention includes a plurality of comparator blocks, an encoder for upper bits, and an encoder for lower bits. A gate block and a plurality of AND gate blocks for controlling the lower bit encoder are provided to simplify the configuration and suppress the occurrence of glitches.

[Conventional technology]

Conventionally, a parallel comparison type A/D converter that is capable of high-speed operation and suppresses glitches has been developed, for example, in Japanese Patent Application Laid-Open No. 62
It is described in Publication No.-32724. That is, the sixth
In the block section showing an example of a conventional parallel comparison type A/D converter in the figure, reference numerals 1 denote terminals ■, . This is a resistor group in which 2h (n indicates n bits of digital output) resistors having the same resistance value are connected in series between the terminals Vr and Vr&. Said resistance group 1
2n-1 reference potential points VRI to VR, are 2''-1
The analog input signal connected to each comparator of the comparator group 2 and supplied to the human power terminal IN and the reference potential point VR+
to VR. are compared with each voltage. The output of each comparator of the comparator group 2 is supplied to an encoding circuit 4 via an AND gate group 3, and is converted into a digital signal according to the level of the analog signal. The encoding circuit 4 may have multiple switching points (glitches) between the output "1" corresponding to the analog human input and the output rQJ, resulting in an incorrect output compared to the original digital output. occurs, so an encoding method called a Daley code (alternating binary code) is used. The Gray code is then converted into a natural binary code by a conversion circuit 5. The conversion circuit 5 normally performs an exclusive OR (hereinafter, EX-OR) conversion circuit 5.
It is composed of a circuit called

[Problem to be solved by the invention]

However, the conventional parallel comparison type A/D converter requires a conversion circuit 5 composed of an EX-OR circuit in order to suppress glitches, which has the drawback of making the system complicated.

Therefore, an object of the present invention is to improve the above-mentioned drawbacks, and to provide a parallel comparison type A/D converter that suppresses the occurrence of glitches (digital errors) and simplifies the configuration. be.

[Means to solve the problem]

The parallel comparison type A/D converter of the present invention has the first to Nth (N
≧2) In a parallel comparison type A/D converter having a comparator block, an encoder for upper bits, and an encoder for lower bits, the analog input is connected to a predetermined comparator output of the first to N-th comparator blocks. an AND gate block for upper bit control which selects a predetermined comparator block corresponding to the signal level to control the encoder for upper bits; It consists of first to Nth lower bit control AND gate blocks that control the encoder. Further, the parallel comparison type A/D converter of the present invention is configured to control each of the first to Nth lower bit control AND gate blocks by the output of the upper bit control AND gate block. ．． [Operation] According to the present invention, the upper bit AND gate block selects a predetermined comparator block corresponding to the analog input signal level to control the upper bit encoder, and the first to Nth Since the encoder for lower bits is controlled by the AND gate block for controlling lower bits, it is possible to suppress the occurrence of glitches with a simple structure.

Furthermore, when controlling the first to Nth lower bit control AND gate blocks by the output of the upper bit control AND gate block, deviation from the true value of the digital output (digital error) is possible. can be reduced as much as possible.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. Figure 1 shows the basic structure of the A/D converter of the present invention. It is a block diagram, IN is an input terminal to which an analog input signal is supplied, and 6 is a first comparator block. The first comparator block 6 is composed of comparators 6a to 6d. 7 is an N-th (N≧2, for example, N=3) comparator block, which is composed of comparators 7a to 7C. 8
is a resistance group, and for example, the first
The resistors R1 to 12th resistor R, ■ are connected to the terminal V. and terminals vL, each connection point P1 to Pl
! generate mutually different reference voltages. The input terminal IN is connected to the in-phase input terminals of the comparators 6a to 6d of the first comparator block 6 and the in-phase input terminals of the comparators 7a to 7d of the N-th comparator 7, respectively, and the connection points P1 to Pl! is comparator 6a
They are respectively connected to the negative phase input terminals of the comparators 7d to 7d. Reference numeral 9 denotes an AND gate block for controlling upper bits, and as an example, an AND gate 9a connected to the output of the comparator 6d of the l-th comparator block 6 and an N-th
and an AND gate 9C connected to the comparator 7d of the comparator block 7.
The Nth comparator block 6 or the Nth comparator block 7) is selected to control the upper bit encoder 10. 11 is a first lower bit control AND gate block connected to the output of the first comparator block 6, and includes AND gates lla to AND gate llc.
is threatened by 12 is the Nth comparator block 7
This is an Nth (for example, N=3) lower bit control AND gate block connected to the output of the AND gate 12a to AND gate 12c. Reference numeral 13 denotes an encoder for lower bits, which is controlled by the outputs of the first AND gate block l1 for controlling lower bits and the Nth AND gate block 12 for controlling lower bits.

In addition, Q, to Q. is a switching transistor, D
+ (MSB) to D4 (LSB) are digital output terminals.

The operation in the above configuration will be explained. Manual terminal I
When the level of the analog input signal supplied to N is higher than the reference voltage at point P4, the in-phase outputs of the comparators 6a to 6d of the first comparator block 6 all become high level, and the AND gate 9 for controlling the upper bit The output of the AND gate 9a also becomes high level, and the lth
Comparator block 6 is selected. Therefore, the switching transistor Q of the encoder 10 for upper bits
1 and Q. turns on, and the digital output terminal D+ (MS8
) to D4 (LSD) output is (1100).

Furthermore, when the analog input signal level rises and exceeds the reference voltage at point P, the output of the comparator 6C of the first comparator block 6 and the AND gate llc of the AND gate block 1l for the first lower bit system 11i are output. The output becomes high level, the switching transistor Q3 of the encoder 13 for lower bits turns on, and the output of the digital output terminals D + (MSB) to D4 (LSB) becomes (11
01). The analog input signal level has further increased and exceeded the reference voltage at point P2.The output of the comparator 6b of the first comparator block 6 and the AND gate llb of the first lower bit control AND gate block 1l
The output of becomes high level, and the encoder l for lower bits
3 switching transistor Q4 is turned on, and the output of the digital output terminals D + (MSB) to D 4 (LSB) becomes [1110] (in this case, the AND gate 11
C is off). Furthermore, the analog input signal level increases and P
．． When the reference voltage at the point exceeds the reference voltage, the output of the comparator 6a of the first comparator block 6 and the output of the AND gate lla of the first lower bit control AND gate block 11 become high level, and the switching transistor of the lower pit encoder 13 becomes high level. Q, and Q, are turned on, and the digital output terminals Dr (MSB) to D. (LSB)
The output of is (1111) (in this case, AND gates llb and llc are both off).

Next, the analog input signal level changes from connection point P, to PIm
A case will be described in which the Nth (N=3 as an example) comparator block is selected. When the analog input signal level exceeds the reference voltage at the Ptz point, the output of the comparator 7d of the Nth comparator block 7 and the output of the comparator 9C of the AND gate block 9 for upper bit control become high level, and the encoder 10 for upper bits becomes high level. switching transistor Q7 is turned on, and the digital output terminals DI (MSB) to D. (LS
The output of B) is (0100). Furthermore, the analog input signal level increases and P. When the reference voltage of the point is exceeded, the Nth
The output of the AND gate 12c of the AND gate block 12 for controlling the lower bits becomes high level, the switching transistor Q8 of the encoder 13 for lower bits turns on, and the digital output terminals Dr (MSB) to D4 (LS
B) becomes (0101). Furthermore, the analog input signal level rises to P1. When the reference voltage exceeds the reference voltage at the point, the output of the AND gate 12b of the N-th lower bit control AND gate block l2 becomes high level, the switching transistor Q9 of the lower bit encoder 13 is turned on, and the digital output terminal Dr (MSB) ~D a (LSB)
The output is (0110). When the analog input signal level further increases and exceeds the reference voltage at point P, the output of the AND gate 12a of the N-th lower bit control AND gate block 12 becomes high level, and the switching transistor Q1 of the lower pit encoder 13 . and Q. is turned on, and the digital output terminals D r (MSB) to D .
The output of (LSB) is (0101). Therefore, the output of the upper bit control AND gate block 9 controls the upper bit encoder IO, and the output of the first lower bit control AND gate block 11 or the Nth lower bit control AND gate block 12 controls the lower bit. Since the encoder 13 is controlled, the structure can be simplified to a certain extent, and the occurrence of glitches can be suppressed as described later. Note that, as described above, N is not limited to 3, and the same operation is possible if N≧2. Also, as shown by the broken line in FIG. 1, the AND gate block 9 for controlling the upper bits
When controlling the first lower bit control AND gate block 11 to the Nth lower bit control AND gate block 12 by the output of the first comparator block 6 or the Nth comparator block 7,
For the selected one, the first lower bit control AND gate block 11 or the Nth lower bit control AND gate block 12 is selected, so that the deviation from the true value of the digital output (digital error) can be minimized. can be reduced to

Next, a digital error (deviation from the true value = glitch) when two switching points occur will be described with reference to a block diagram showing a first example of glitch occurrence in FIG. In FIG. 2, when the level of the analog input signal supplied to the input terminal IN corresponds to the reference voltage at point P4, the input voltage corresponding to the reference voltage at point P1 appears to remain in the comparator 6a because the speed is slow. , the outputs of comparator 6a and comparator 6d both become high level. Therefore, the outputs of AND gate 11a and AND gate }9a both become high level, switching transistors Q+, QzsQ, and Q are turned on, and digital output terminals D, (MSB) to D a (LS
The output of B) is (1111), and an output with an error (ignorable) within 3 steps from the true value (1100) is obtained. Further, as shown in the block diagram showing the second example of glitch occurrence in FIG. 3, the analog input signal level is P
If the voltage corresponding to the reference voltage of point P remains in the comparator when it corresponds to the reference voltage of point 16, similarly (switching transistor QIt is turned on), the digital output terminals Dr (MSB) to D a (LSB)
The output is (0111), which is one step away from the true value, but this error is practically negligible.

In the first and second examples described above, the output of the upper bit control AND gate block 9 controls the lower bits of the first lower bit control AND gate blocks 11 to Nth (N=3 as an example). We have described the case where the AND gate block 12 is not controlled.
Referring to the block diagrams illustrating the third and fourth examples of glitch occurrence shown in FIGS. (For example, N
A case will be described in which the AND gate block 12 for controlling the lower bits of =3) is controlled. In FIG. 4, the level of the analog input signal supplied to the input terminal IN is P4.
If the input voltage corresponding to the reference voltage at point P remains in the comparator 6a because the speed of the comparator is slow, the digital output terminal D
．． (MSB) ~ D 4 (LSB) output is (111
1), resulting in an error within 3 steps (same as the first example). Next, in Fig. 5, when the level of the analog input signal supplied to the input terminal IN corresponds to the reference voltage at the PIG point, the input voltage corresponding to the PIG point remains in the comparator corresponding to the PIG point. If so, the output of the AND gate 19b of the AND gate block 9 for upper bit control becomes a low level and turns off the switching transistor Qlt, so that the digital output terminal Dr (MSB) ~
The output of D4 (LSB) is (0110). Therefore,
This fourth example has fewer glitches than the second example described above.

In the above embodiment, a 4-bit parallel comparison type A/D converter has been described, but the present invention is not limited thereto, and can be applied to, for example, a 16-bit or 3-bit converter. .

〔Effect of the invention〕

As is clear from the above explanation, the parallel comparison type A/
By providing an AND gate block for controlling the upper bits and an AND gate block for controlling the lower bits, the D converter eliminates the need for a conversion circuit, which is required in the conventional EX-OR circuit, and suppresses the occurrence of glitches. Together with this, the structure can be simplified. Furthermore, when the AND gate block for controlling the lower bits is controlled by the AND gate block for controlling the upper bits, the deviation of the digital output from the true value (digital error) can be minimized.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the basic structure of the parallel comparison type A/D converter of the present invention, Fig. 2 is a block diagram showing the first example of glitch occurrence, and Fig. 3 is a block diagram showing the first example of Grinch occurrence. A block diagram showing the second example, FIG. 4 is a block diagram showing the third example of glitch occurrence, and FIG. 5 is a block diagram showing the fourth example of glitch occurrence.
A block diagram showing an example of the conventional parallel comparison type A/
It is a block diagram showing an example of a D converter. 6 First comparator blocks 6a to 6d.
- Comparator 7 - - 1 - -. 1----・AND gate block 10 for controlling upper bits ・-・−・1 ・・−・1・1 Encoder 11 for upper bits ・・−・・−・−・・1 ・−・1st AND gate block 11 a to 11 c-7 for lower bit control F 'F' - }12.
-・-・-・−・・−・・Nth lower bit control AND gate block 12a to 12c・−・AND gate 1 3−−−−− ...Encoder D for lower bit
+ (MSB) ~ D4 (LSB) - Digital output terminal R1 ~ Rlt''... 1st to 12th resistor P1 ~
p+z'-・Connection point Q1~Q lr-Switching transistor 1st = 2 Figure 8 A block diagram showing the basic structure of the parallel type 11 comparison type ADD modification #h of the present invention Figure 8 Figure 3 2Φg+1 1 Alock surface number
2 Figure 10g11 showing the occurrence of a 7-lock diagram 8 Figure 4 Third example of a 7-lock occurrence Figure 5

Claims (1)

[Scope of Claims] 1. A parallel comparison type A/D converter having first to Nth (N≧2) comparator blocks, an encoder for upper bits, and an encoder for lower bits, wherein the first
an AND gate block for upper bit control which is connected to the output of a predetermined comparator of the Nth comparator block and controls the upper bit encoder by selecting a predetermined comparator block corresponding to the analog input signal level; A parallel comparison type A characterized in that the first to Nth lower bit control AND gate blocks are connected to the outputs of the first to Nth comparator blocks and control the lower bit encoder.
/D converter. 2. The parallel comparison type A/D conversion according to claim 1, wherein the first to Nth lower bit control AND gate blocks are respectively controlled by the output of the upper bit control AND gate block. vessel.