JPH02186710A - Band limiting system for base band - Google Patents

Abstract

PURPOSE:To facilitate miniaturization by means of LSI without adjustment by constituting a system of a non-cyclic digital filter which inputs transmission data as one bit data, then outputs them as plural bits, and of an analogue filter. CONSTITUTION:Digital transmission data TXD are sample-shifted by an n-stage shift register 10. When the outputs Si-Sn of respective stages have the logical values of '0', switches 111-11n select respective data '0', and select data 1-n having a k-bit width when they have '1'. When switches 111-11n execute multiplication of the signals S1-Sn and coefficients alpha1-alphan, their values are equivalent. The outputs of the switches 111-11n are added in an addition circuit 12, and the result of m-bit can be obtained. Furthermore, it comes to an analogue value DA by a D/A converter 13. Then, a clock CLK frequency and a higher harmonic component and filtered in LPF 14, and are made smooth. When the period of the clock is selected to be a one-to-the integer of a data bit length, noise can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a baseband band limiting scheme in a digital data transmitter.

[Prior Art] In digital data wireless transmitters, in order to reduce the transmission bandwidth, baseband digital data is band-limited using a low-pass filter and then modulated (for example, frequency modulation is performed). 1. In order to improve the reproducibility of digital data on the receiving side, this low-pass filter must be highly accurate.

Conventionally, these filters have been filters that combine coils and capacitors, analog filters such as so-called active filters that use operational amplifiers, or the Fundamentals of Mobile Communications (published in 1986), Vol. 27, edited by the Institute of Electronics and Communication Engineers.
Switched capacitor filters were used, such as those described on pages 2 to 273.

[Problem to be solved by the invention]

Among the conventional techniques described above, analog filters such as active filters require adjustment due to variations in components. When considering the miniaturization of devices, large-scale integrated circuits (L
This has been a problem because it is difficult to summarize them into a group such as Si).

On the other hand, the above-mentioned switched capacitor filter does not require adjustment, can be made into an LSi, and is effective for miniaturization. However, attempting to integrate it with other digital circuits into a single chip is often difficult due to differences in processes.

A possible solution to this problem is to use a digital filter, but the circuit size generally increases and if left as is,
Economically difficult to apply.

The present invention has been made in consideration of the above points, and an object of the present invention is to provide a baseband band limiting method that does not require adjustment and can be easily downsized using L8iK.

[Means to solve the problem]

In order to achieve the above purpose, an acyclic fi (F
4R) Digital filter This is constructed using a simple analog filter.

[Effect]

The transmitted signal is sampled into a 1-bit digital value,
It is input to the FIR digital filter.

The delay element, which is a component of the FIR digital filter, may have a width of 1 bit since the input data is 1 bit and there is no feedback from the output side. Furthermore, since the multiplication circuit for the coefficient applied to each tap of the delay element also has a 1-bit input, it can be significantly reduced. Therefore, it is possible to provide a digital filter with a small circuit scale and a circuit system suitable for LSi implementation.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. Transmission data ('I'XD), which is digital data, is sampled and shifted in the shift register 10. The shift register 10 has n stages, and the outputs 81 to Sn of each stage are used as switching control signals for the switches 111 to 11n.

If the signals 81 to Sn have a logical value of 0, the switch 111
~11n each selects data 0, and vice versa, selects data α1~αn. Of course, the switches 111 to 11n may be a combination of gates. Data α1 to αn are k
It is bit width and represents a numerical value.

The switches 111 to 11n are equivalent to multiplying the signals S1 to Sn by the coefficients α1 to αn. The outputs of the switches 111-11n are added in an adder circuit 12 to obtain an m-bit result. Furthermore, digital
is converted into an analog value by an analog converter (DAC) 13. The converted signal DA contains the clock (CLK) frequency and its harmonic components, so it is filtered by a low-pass filter (LP).
F) On the 14th, there will be a P wave. If the clock frequency is set sufficiently higher than the signal frequency, the LPF 14 can be set to, for example, the third
As shown in the above, a simple one consisting of a resistor R and a capacitor C may be sufficient.

The operation of the nine actual flow side shown in FIG. 1 will be explained using the timing chart of FIG. 2. For the purpose of explanation, we set n = 4. When a pulse for four clocks is generated in the transmission data ('1'XD), the waveforms of each tap of the shift register 10 become as shown in 81 to S4 in FIG. 2, respectively. Signal 81~
Switches 111 to 114 are switched depending on the state of S4. For example, in the second section, only Sl is 1, so α1 is output to the adder circuit 12 output, and DA013
The signal level corresponding to the output (DA)K is outputted. Similarly, in the fifth section, α1+α2 is output. The signal DA has a stepped shape as shown in the figure, and the LPF
Purified by '14.

Noise can be reduced by selecting the period of the clock (CLK) to be an integer fraction of the data bit length.

Next, another embodiment of the present invention will be described using FIG. 4. The difference between this embodiment and FIG. 1 is that the switch and addition circuit are replaced with a memory 15. Other same symbols indicate the same contents. 81 to Sn are input as address signals for the memory 15, and data output is output to the DAC 15.

The memory 15 is programmed with data as shown in FIG. 5, for example, assuming n=4.

That is, the signals 81 to S4 are each used as an address signal for the memory 15, and data as shown in the figure is outputted according to the contents thereof. Using the data shown in the fifth factor, the operation is exactly the same as in FIG. 1.

The memory 15 may be a so-called read-only ROM, but
If you use a rewritable filter, you can freely change the characteristics of the filter.

〔Effect of the invention〕

In general, FI Rfi digital filters require multiplication circuits for each delay output and coefficient (multiple bits) when multiple stages of multi-bit delay circuits are installed, and the circuit size becomes very large when the number of delay stages (orders) is large. Become. However, in the present invention, as explained above, a 1-bit width shift register is used for the delay circuit, and a switch or an equivalent circuit is used for the multiplication circuit, and the multiplication circuit and addition circuit are connected to memory. Since the circuit can be replaced with , the overall circuit scale can be significantly reduced, and since the circuit is mainly a digital circuit, it can be easily integrated into LSi.

[Brief explanation of the drawing]

The first factor is a circuit block diagram of an embodiment of the present invention, FIG. 2 is a timing chart explaining the circuit operation of FIG.
The reason is a circuit example of a low-pass filter, FIG. 4 is a circuit block diagram illustrating another embodiment of the present invention, and FIG. 5 is a diagram illustrating the contents of memory programming. Explanation of symbols 10...Shift registers 111 to 11n...Switches 12...Addition circuit 15...Digital-to-analog converter 14...
...Low pass filter 15...Memory. Figure 3 Figure 4 Kano 2 Diagram System 5

Claims (1)

[Claims] 1. A digital signal transmitter comprising a filter that band-limits a baseband digital data signal and a modulator that modulates a high frequency using the output of the filter, wherein the input of the filter is set to 1 bit. , a baseband band-limiting method that is realized by an acyclic digital filter that outputs multiple bits. 2. The baseband band limiting method according to claim 1, wherein the clock of the digital filter is an integral multiple of the bit clock of the information.