JPS6096014A - Transversal filter - Google Patents

Abstract

PURPOSE:To attain one chip integration of a digital part by constituting that an ROM is used for a tap weight control and the digital part uses logical elements entirely so as to eliminate the need for ROM. CONSTITUTION:A shift register of 32 stages is driven by a speed four times the clock speed, an output of each shift register of 32 taps passes through tap coefficient circuits T1T32, the output is added by two sets each by 16 sets of 8-bit full address 8FA-1-8FA-16, the output is added by two sets each by 8 sets of 9-bit full adders 9FA-1-9FA-8 according to the tournament system, the result passes through the full adder sequentially and the signal through a 13-bit full adder 13FA finally becomes a 14-bit digital signal, from which a desired waveform is obtained through a D/A converter 7 and an LPF8.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a circuit configuration method for a filter that shapes the spectrum of a digital signal.

(Background Art) Conventionally, when operating in a high-speed region using a memory circuit such as a ROM'C read-only memory (as shown in FIG. 12 and FIG. 2), the ramp weighting of a binary transversal filter is performed using However, since it is difficult to use the same chip as other digital parts (shift registers, etc.), the overall structure is slow and consumes a lot of power.

(Problems to be solved by the invention) In order to solve the above-mentioned drawbacks, the present invention provides a transversal filter that does not use -ROM for tap weighting, but uses only logic elements such as full adders, making it possible to downsize and reduce power consumption. This provides a circuit configuration method.

(Structure and operation of the invention) To explain the invention in detail, consider, as an example, a binary transversal filter with a 32-tap shift register and a valley tap precision of 8 bits. Other bit numbers can also be easily implemented by changing the number of digits of the shift register. As an embodiment of the tap weighting circuit according to claim 3, the logic circuit has an 8-bit tap weighting precision for a binary shift register output, and the tap coefficient when the shift register output is "1" is An example of a configuration using this is shown in FIGS. 3 and 4. In the case of FIG. 3, the number of logics can be extremely small, but once designed, it cannot be changed. In the case of Figure 4, two 8-bit shift registers are used to input the tap coefficients.
When the power is turned on, data corresponding to tap coefficients is input from the outside and stored in the shift register. In this case, although a large number of logics are required, changes in tap coefficients can be easily handled.

A specific example of claim (1) is shown in FIG.

The 32-stage shift register is driven at four times the clock speed, and the output of each 32-tap shift register is passed through the tap coefficient circuit (T, ~T32) as shown in FIG. Bit full adder (8FA~1~8FA~
16), 92 sets are added at a time, and the output is added 2 sets at a time using eight 9-bit full adders (9FA~1~9FA~8) in a tournament manner, and finally 13 through the full adder circuit. The signal passed through the bit full adder 13FA is 1
A desired waveform can be obtained by passing the 4-bit digital signal through a D/A converter (7) and a low-pass filter (8).

A specific example of claim (2) is shown in FIG.

The operating speed of the peripheral circuit is equivalent to the data coding speed,
For each of the four series whose phases differ by π/2, two sets are added to each output of the eight-stage shift register by four 8-bit full adders through a tap coefficient circuit as shown in Fig. 3 or Fig. 4. Furthermore, after addition by two 9-bit full adders and finally addition by a 10-bit full adder, 11-bit D
A desired waveform can be obtained by converting the waveform into an analog waveform using a /A converter, adding the signals using analog adders having different phases for each π/2 phase, and passing the signal through a low-pass filter.

(Effects of the Invention) As explained above, by changing the conventional configuration that uses ROAI for tap weight control to a configuration that uses logic elements for all digital parts, the digital part that does not require a ROM can be made into one chip. This configuration is suitable for downsizing the transversal filter and reducing power consumption.

[Brief explanation of drawings]

Figures 1 and 2 are block diagrams of conventional binary transversal filters, Figures 3 (α) and (b), and Figure 4 are specific examples of tap coefficient circuits, and Figure 5 is the scope of claims. FIG. 6 is a specific embodiment of claim 2. DESCRIPTION OF SYMBOLS 1... Clock signal input terminal, 2... Data signal input terminal 3... Analog signal output terminal, 4... Shift register 5... Tap coefficient circuit, 6... Full adder 7
...D/A converter, 8...Low pass filter 9...
・Analog adder, 10...π/2 phase shifter Patent applicant: Nippon Telegraph and Telephone Public Corporation Patent application agent Megumi Yamamoto - Fig. 2 Fig. 4

Claims (4)

[Claims] (1) an M-tap shift register driven at N (an integer greater than or equal to 2) times the clock frequency l/T of input data;
The D/D has a bit tap weighting circuit for each binary shift register output, a full adder for adding a bit digital signal Mm to each output, and an input capacitor corresponding to the output of the full adder.
A transversal filter comprising a Digital to Analog (A) converter and a low-pass filter. (2) The transversal filter according to claim 1, wherein the tap weight circuit for the bits is constituted only by logic elements and receives an output from the shift register as an input. (3) Driven at the same frequency as the input data and υ/I/N(
For each binary shift register output, a K-bit tap weighting circuit, a full adder that adds a set of digital signals A4'/N of bits to each, and a full adder equivalent to an integer) tap shift register. N groups of circuits each consisting of D/A converters with input capacitors, phase shifters (#-i) that shift by 2π/N radians of the clock frequency that drives the shift register, and N D/A converters. 1. A transversal filter characterized by comprising an adder circuit for adding the outputs of the filter and a low-pass filter. (4) The transversal filter according to claim 3, wherein the bit tap weighting circuit is configured in a logical manner and receives the output of the shift register as an input.