JPH05176221A - Gamma correction circuit - Google Patents

Abstract

PURPOSE:To enable gradation conversion with high bit accuracy by converting a video signal into a digital signal with plural A/D converters having a different reference voltage and outputting a gamma correction value corresponding to each data from a memory. CONSTITUTION:The circuit is provided with 2-bit A/D converters 3, 4 whose reference voltage is difference and a memory 5 converting input data whose level indicates the level of an input video signal into a nonlinear video signal. Then the A/D converter 3 converts the video signal into a digital signal of >=(n+1) bits at the low frequency side of the video signal requiring the bit accuracy of >=n-bits. Furthermore, the A/D converter 4 converts the video signal into a digital signal of (n)-(n+1) bits at the high frequency side of the video signal not requiring the bit accuracy of >=n-bits. The gamma correction value corresponding to address data in (n+1) bits converted by the 2 A/D converters 3, 4 is outputted from the memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital gamma correction circuit for performing gamma correction of a video signal of a video camera by digital signal processing.

[0002]

2. Description of the Related Art Conventionally, in a gamma correction of a video camera, a look-up table (hereinafter referred to as LUT) method is mentioned as a digital method. Figure 2 shows a conventional LUT
It is a configuration diagram of a digital gamma correction circuit by the method,
In the figure, 6 is an 8-bit A / D converter, and 7 is a memory.

Next, the operation will be described. The input video signal is digitally converted by the 8-bit A / D converter 6 into 8-bit between the reference voltages a and b. Digital data of the digitally converted video signal is input to the memory 7 as an address. The memory 7 outputs gamma correction data having a magnification corresponding to the gamma curve shown in FIG. 3 according to the input address. In FIG. 3, S _IN is an input video signal digitized into 8 bits, and S _OUT is a normalized digital video output of the memory 7.

[0004]

When digital gamma correction by the LUT method is performed, non-linear conversion is performed as shown in FIG. 3, and therefore, in order to obtain an output of n-bit precision, an input of n-bit or higher precision is required. And Therefore, there is a problem that an A / D converter of n bits or more is required for digital conversion.

Further, in the current A / D converter,
The 8-bit or more A / D converter has a problem that the price and power consumption are significantly increased as compared with the 8-bit A / D converter.

The present invention has been made in order to solve the above problems, and in a digital type gamma correction circuit, by using a plurality of A / D converters and memories properly, an excellent digital structure can be obtained. The purpose is to obtain a gamma correction circuit.

[0007]

A gamma correction circuit according to a first aspect of the present invention uses two n-bit A / D converters having different reference voltage values, and a gamma correction circuit adapted to an address of n + 1 bits by a memory. Gamma correction is performed by outputting the value.

A gamma correction circuit according to a second aspect of the present invention uses N n-bit A / D converters having different reference voltage values and outputs a gamma correction value adapted to an input address by a memory, Gamma correction is performed.

[0009]

The gamma correction circuit according to the first aspect of the present invention uses two n-bit A / D converters having different reference voltage values, so that the low-frequency range of a video signal requiring a bit precision of n bits or more is used. On the side, digital conversion of n + 1 bits or more is performed by the A / D converter (I), and on the high frequency side where bit precision of n bits or more is not required, n bits or more, n + by the A / D converter (II).
Performs digital conversion of 1 bit or less. The above two A
The gamma correction value corresponding to the n + 1-bit address data digitally converted by the / D converter is output from the memory.

The gamma correction circuit according to the second aspect of the present invention uses N n-bit A / D converters having different reference voltage values, so that a low-quality video signal requiring a bit precision of n bits or more is reduced. On the high frequency side, digital conversion of n + lnN / ln 2 bits or more is performed by the A / D converter (I), and on the high frequency side that does not require bit precision of n bits or more, n / bit or more by the A / D converter (N), Digital conversion of n + ln N / ln 2 bits or less is performed, and a video signal is digitally converted by N A / D converters. Select the data digitally converted by the N A / D converters with a switch,
The gamma correction value corresponding to the address data is output from the memory.

[0011]

EXAMPLES Example 1. Hereinafter, each embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a digital gamma correction circuit of the present invention. In the figure, 3
Is an 8-bit A / D converter (II) having a reference voltage VRT of b and VRB of x (x≤ (a + b) / 2), and digital conversion is performed in this voltage region. Reference numeral 4 is an 8-bit A / D converter (I) in which VRT is x and VRB is a. Reference numeral 5 denotes a memory having data output from the A / D converter 3 and the A / D converter 4 as an address and having a gamma correction value corresponding to each data as a data table. The present invention is based on this A / D converter (II) 3, A / D
It is composed of a converter (I) 4 and a memory 5.

The operation of the digital gamma correction circuit configured as described above will be described below. Figure 3
As shown in, the gamma characteristic curve is expressed by the following equation.

[0013]

[Equation 1]

K is a constant and standardized in the equation (2). n is the number of bits, r is a gamma constant, S _IN is a signal obtained by digitally converting the video input signal into 8 bits, and S _OUT is a digital signal after gamma correction. When an output with n-bit precision is required, the required number of input bits N ₀ is expressed by the following equation.

[0015]

[Equation 2]

Therefore, when dS _OUT / dS _IN ≧ 1, the number of input bits requires a bit precision of n bits or more.
_{When OUT} / dS _IN <1, bit precision of n bits or more is not required. Now, when n = 8 and r = 0.7

[0017]

[Equation 3]

## EQU1 ## When S _IN = 1, Δn = 1.9, and according to the conventional method, an 9.9-bit A / D converter is required to obtain an 8-bit precision output image. there were.

As shown in FIG. 1, according to the present invention, the video signal in the reference value a to x region is digitally converted by the A / D converter (I) 4, and the video signal between the reference values x and b is A / D. Digitally converted by the D converter (II) 3. The video signal digitally converted by the two 8-bit A / D converters is input as an address to the memory 5 having a data table as shown in FIG. 4 and gamma-corrected.

The video signal digitally converted by the A / D converter (I) 4 is

[0021]

[Equation 4]

As shown in (1), the video signal digitally converted by N1 bits and digitally converted by the A / D converter (II) 3 is

[0023]

[Equation 5]

Digital conversion is performed with N2 bits as shown in FIG. In FIG. 5, d indicates ΔN1 and c indicates ΔN.
2 is shown. Figure 6. e is the number of bits N ₀ required for digital conversion to obtain an output video signal with 8-bit precision with respect to the value of x.

Here, x / (a + b) · 100 = 25
Set as (%). At this time, S _IN (x = 25) = 64. Therefore, from the expressions (3) and (5), the bit precision of N ₀ (S _IN = 1) = 9.88 (8) N ₀ (S _IN = 64) = 8.09 (9) is required. In the conventional method (8)
Both equations (9) are digitally converted with 8 bits, and the result shown in FIG. As shown in i, the bit precision of 1.88 is insufficient. According to the present invention, digital conversion is performed with the bit precision of N1 (S _IN = 1) = 10.0 (10) N2 (S _IN = 64) = 8.42 (11) from the equations (6) and (7). It is possible (indicated by symbol h in FIG. 6). Therefore, as shown in FIG. 6, while satisfying the required number of bits, digital conversion is performed with a bit precision higher than that (g indicates N1 and N2 when x / (a + b) = 50%).

Example 2. FIG. 7 shows the configuration of a digital gamma correction circuit according to another embodiment of the present invention. 8 is an 8-bit A / D converter (II) and the reference voltage VRT is b, VRB
Is x (x ≦ (a + b) / 2), and digital conversion is performed in this voltage region. Reference numeral 9 is an 8-bit A / D converter (I) in which VRT is x and VRB is a. 10 is A / D
A switch for selecting data output from the converter (II) 8 and the A / D converter (I) 9, 11 is an OR circuit,
Reference numeral 12 is a memory having the data selected by the switch 10 and the output of the OR circuit as an address and having a gamma correction value corresponding to each data as a data table. The present invention is composed of the two A / D converters 8 and 9, the switch 10, the OR circuit 11 and the memory 12 described above.

The operation of the digital gamma correction circuit configured as described above will be described below.

As shown in FIG. 4, between the input video signals a to x,
The A / D converter (I) 9 carries out digital conversion with 8-bit precision, and between x and b is digitally converted with 8-bit precision by the A / D converter (II) 8. 2 depending on the value of x
The bit precision of the video signal digitally converted by one A / D converter has been described above, so avoid duplication. A / D
The data of the converter (II) 8 is input to the OR circuit 11 and outputs the data D ₁₆ . A / D converter (I)
9, the A / D converter (II) data outputted from the 8 when D ₁₆ in the switch 10 is 1 A / D converter (I
Select the data of I) 8 and the data of the A / D converter (I) 9 when _D16 is 0. The data selected by the switch 10 and D ₁₆ are used as addresses, and a gamma correction value corresponding to each data is output from the memory 12 to form a digital gamma correction circuit for performing digital gamma correction.

Example 3. FIG. 8 shows the configuration of a digital gamma correction circuit according to another embodiment of the present invention. 13 is n
In the bit A / D converter (I), the reference voltage VRT is x
₁ , VRB is a, and digital conversion is performed in this voltage region. Reference numeral 14 is an n-bit A / D converter (II) in which VRT is x ₂ and VRB is x ₁ . 15 has VRT x
It is an n-bit A / D converter (N-1) in which _n-1 and VRB are _xn-2 . Reference numeral 15 is an n-bit A / D converter (N) in which VRT is b and VRB is x _n-1 (b> x _n-1 >).
...> x ₂ > x ₁ > a and x ₁ −a <x ₂ −x ₁ <
.. <(ba) / N <... <b- _xn-1 ). A / D
Converter (I) 13 to A / D converter (N) 16
Up to N A / D converters. Reference numeral 17 denotes a data select circuit which outputs data for selecting data of one A / D converter among N A / D converters by the output of each OR circuit 11. Reference numeral 18 is a switch for selecting the data output from the N A / D converters. Reference numeral 19 denotes a memory having the data selected by the switch 18 and the data output from the data select circuit 18 as addresses and having a gamma correction value corresponding to each data as a data table. The present invention is based on the above-mentioned OR circuit 11 and N A / D converters 12.
To 15, data select 16, switch 17, memory 1
It is composed of 8.

The operation of the digital gamma correction circuit configured as described above will be described below. As shown in FIG. 9, the input video signal is digitally converted between VRT and VRB with N-bit precision by N A / D converters. The bit precision of the digitally converted video signal between VRT and VRB is

[0031]

[Equation 6]

It is represented by A / D converter (II) 14
Data from the A / D converter (N) 16 through the respective OR circuits 11 are input to the data select circuit 17. The data select circuit 17 selects one A / D converter out of N A / D converters (lnN / ln2)
Outputs bit data. The (lnN / ln2) -bit data output from the data select circuit 17 is input to the switch 18. The data of (lnN / ln2) bits is transferred from the A / D converter (II) 14 to the A / D by the switch 18.
Of the converter (N) 16, the output data of the OR circuit to which the data of a certain A / D converter is input is 1 and the output data of the OR circuit to which the data of the higher A / D converter is input are all 0. When the data (D _{0 to} D _n-1 ) of the A / D converter is selected, the A / D converter (I) 13 is selected when the data of the OR circuit is all 0. As described above, N A's are set by the switch 18.
One of the D / D converters is selected, the data output from the switch 18 and the data output from the data select circuit 17 are used as addresses, and the gamma correction value corresponding to each data is output from the memory 19,
A digital gamma correction circuit that performs digital gamma correction is configured.

Example 4. In the embodiment of the digital signal processing unit of the present invention, the number of bits of digital data was mainly described as 8. However, the present invention is not limited to that value, and may be an appropriate value determined from the video camera design and the image quality. The effect of the present invention can be realized even with a value.

[0034]

As described above, according to the present invention, by using a plurality of n-bit A / D converters having different reference voltage values,
The digital signal is digitally converted, and the gamma correction value corresponding to each data is output from the memory to perform the digital gamma correction. Correction can be realized. In addition, the gamma correction circuit can be configured simply by providing an A / D converter and a memory, which is extremely simple and has lower power consumption and lower cost than the A / D converter having the required number of bits in the conventional example. Etc. can also be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a digital gamma correction circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional digital gamma correction circuit.

FIG. 3 is a diagram showing a gamma-corrected digital output with respect to an input digitally converted to 8 bits.

FIG. 4 is a diagram showing a gamma-corrected digital output with respect to a digitally converted input that is digitally converted by two A / D converters according to the embodiment shown in FIG. 1;

FIG. 5 is a diagram showing the bit precision that increases in the number of data bits of the video signal digitally converted by the A / D converter with respect to the value x of VRB of the A / D converter (I) and VRT of the A / D converter (II). It is a figure which shows bit precision (DELTA) N2 reduced with (DELTA) N1.

FIG. 6 shows a video signal corresponding to VRB of the A / D converter (I) and VRT of the A / D converter (II), ie, x.
FIG. 3 is a diagram showing the number of bits N ₀ required for digital conversion when obtaining bit precision and the number of bits digitally converted in an embodiment of the present invention.

FIG. 7 is a diagram showing a digital gamma correction circuit according to another embodiment of the present invention.

FIG. 8 is a diagram showing a digital gamma correction circuit according to another embodiment of the present invention.

9 is a diagram showing a gamma-corrected digital output for a digitally converted input obtained by performing digital conversion by N A / D converters according to the embodiment shown in FIG. 8;

[Explanation of symbols]

1 analog video signal input 2 digital video signal output 3 8-bit A / D converter (I) 4 8-bit A / D converter (II) 5 memory 6 8-bit A / D converter 7 memory 8 8-bit A / D converter (I ) 9 8-bit A / D converter (II) 10 switch 11 OR circuit 12 memory 13 n-bit A / D converter (I) 14 n-bit A / D converter (II) 15 n-bit A / D converter (N-1) 16 n-bit A / D converter (N) 17 data select circuit 18 switch 19 memory a voltage value of V RB of A / D converter (I) b A / D converter (II), A / D converter (N)
VRT voltage value of c c indicating ΔN1 d indicating ΔN2 e indicating N f number of bits digitally converted in the conventional example g number of bits digitally converted in one embodiment of the present invention h one embodiment of the present invention Number of bits digitally converted by

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[Procedure amendment]

[Submission date] July 14, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

[0013]

[Equation 1]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

[0021]

[Equation 4]

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction content]

Digital conversion is performed with N2 bits as shown in FIG. In FIG. 5, d indicates ΔN1 and c indicates ΔN.
2 is shown. In FIG. 6 , e is the number of bits N ₀ required for digital conversion in order to obtain an output video signal of 8-bit precision with respect to the value of x.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction content]

[0031]

[Equation 6]

Claims (2)

[Claims] 1. Reference voltages VRT, VRB (VRT> VRB) for digital conversion with n bits are set to a, x (x≤ (a +
b) / 2) A / D converter (I) and VRT, V
Two A / D converters (II) that have x and b in RB
A D converter and a memory for converting input data indicating the level of the input video signal into a non-linear video signal are provided, and a data table of gamma correction data according to the input data is formed in the memory. Characteristic digital gamma correction circuit. 2. N / A converters (N> 2) having different reference voltages VRT and VRB (VRT> VRB) for digital conversion with n bits, and input data indicating the level of an input video signal are non-linear. And a memory for converting the video signal into a video signal, and a data table of gamma correction data according to the input data is formed in the memory.