JPH09219643A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform conversion with high accuracy by a few bit numbers in an A/D converter. SOLUTION: As for the resistance values of ladder resistors 21 to 2255 generating the reference voltage for the compactors 11 to 1255 in an 8-bit A/D converter, the resistances 264 to 2127 are defined as 2R and the resistors 21 to 263 are defined as 4R when the resistors 2128 to 2255 on a LSB side are defined as R. As a result, a level detection is finely performed on the LSB side, the level detection is roughly performed on an MSB side and a nonlinear conversion characteristics can be obtained for an input level. The outputs of 11 to 1255 are decoded in a decoder 3 and the outputs are supplied to a deny circuit 4. In this deny circuit 4, non-linear digital data is converted into linear digital data and the linear digital data is outputted. By making the level of an input analog signal have the non-linear conversion characteristics, a digital conversion with high accuracy can be performed by a few bit numbers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel comparison type A in which high accuracy can be obtained with a small number of bits by giving an input analog signal a non-linear characteristic.
/ D converter.

[0002]

2. Description of the Related Art In a digital video camera for digitally processing a video signal, a CCD as an image pickup device
The output signal from the (Charge Coupled Device) is converted from an analog signal to a digital signal by the A / D converter. This A / D converter usually has a data width of 8 to 10 bits, and from the viewpoint of signal processing speed, a number of comparators connected in parallel corresponding to the data width are used to input analog signals. On the other hand, a parallel comparison type is used in which digital conversion is performed by performing level detection.

[0003]

By the way, in order to improve the image quality of a digital video signal, it is necessary to raise the gradation of the digitally converted data. As described above, in the case where an image pickup signal is digitally converted and processed, a wide data width is required to increase the gradation. Here, in the parallel comparison type A / D converter used for this digital conversion, 2 ⁿ -1 comparators are required, where ^{n is the} number of bits of the data width. Therefore, if the gradation is increased by increasing the data width and increasing the conversion accuracy in the A / D converter, the circuit scale will be greatly increased.

For example, when the data width is 8 bits,
2 ⁸ -1 = 255 comparators were required, but if the data width is 10 bits, the number of comparators is 2 ^10-.
1 = 1023 pieces are required. Therefore, there is a problem that the price of A / D becomes very expensive.

Further, if an inexpensive A / D converter with a narrow data width is used in order to keep the price low, there is a problem in that the gradation is insufficient and, as a result, the image quality is deteriorated. .

Therefore, an object of the present invention is to provide an A / A that can perform highly accurate conversion with a small number of bits.
It is to provide a D converter.

[0007]

In order to solve the above problems, the present invention provides a plurality of comparators for detecting the voltage level of an input analog signal with a predetermined number of bits, and a reference for each of the plurality of comparators. It has a ladder resistor for generating a voltage and a decoder for converting the outputs of a plurality of comparators into digital data, so that the converted digital data has a nonlinear characteristic with respect to the characteristic of the input analog signal. The A / D converter is characterized in that a resistance value of a resistor is set.

As described above, according to the present invention, the resistance value of the ladder resistor for generating the reference voltage for the comparator is
It is changed according to the level of the input analog signal. Therefore, it is possible to detect the level more finely for the low-level input analog signal.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of the configuration of an A / D converter according to an embodiment of the present invention. The A / D converter according to the present invention increases the conversion accuracy by changing the resistance value of the ladder resistor for forming the comparison potential for the comparator in accordance with the input level and increasing the conversion accuracy by providing the conversion characteristic with a non-linear characteristic. The configuration is such that the linear characteristics are restored again.

This A / D converter has a data width of 8 bits and has 2 ⁸ -1 = 255 comparators 1 ₁ to 1 ₂₅₅ . These comparators 1 ₁ to 1
Each of the ₂₅₅ is a reference input that is supplied with a reference voltage,
Further, when the voltage supplied to the comparison input terminal is higher than the voltage supplied to the reference input terminal, the comparison input terminal supplied with the voltage to be compared with the reference voltage is, for example, “1”. Is output, and when it is lower than the reference voltage, for example, “0” is output.

The comparison input terminals of these comparators 1 ₁ to 1 ₂₅₅ are connected to each other, and an input analog signal is supplied to them. In addition, these comparators 1
Ladder resistance 2 is attached to each of the reference input terminals ₁ to _{1255.
1-2 255} are connected. Further, the reference input terminal of the comparator 1 ₁ is supplied with the reference voltage Vt for supplying the voltage defining the highest level, and the ladder resistor 2 ₂₅₅ is supplied with
A reference voltage Vb for supplying a voltage defining the lowest level is supplied. The dynamic range of the input analog signal is standardized to a value of 0 to 1 by these reference voltages Vt and Vb. At this time, Vt> Vb.

The resistance values of the ladder resistors 2 ₁ to 2 ₂₅₅ are all set to the same value in the conventional A / D converter.
In the present invention, it can be changed according to the level of the input voltage. That is, the 128 ladder resistors 2 ₁₂₈ to generate the reference voltage for detecting the low level of the input voltage.
2 If the resistance value of ₂₅₅ is R, 64 ladder resistors 2 ₆₄ to 2 ₁₂₇ that generate the reference voltage for detecting the middle level of the input voltage are doubled 2R, and the high level of the input voltage is detected. The 63 ladder resistors 2 ₁ to 2 ₆₃ that generate the reference voltage for performing the operation are further doubled to 4R.

When the resistance values of the ladder resistors 2 ₁ to 2 ₂₅₅ are set in this way, the reference voltage defined by the ladder resistors 2 ₆₄ to 2 ₁₂₇ is larger than the reference voltage interval defined by the ladder resistors 2 ₁ to 2 ₆₃ . The interval of is reduced to 1/2,
Further, the interval of the reference voltage defined by the ladder resistors 2 _{128 to} 2 _{255 is} made finer to 1/4 of the interval of the reference voltage defined by the ladder resistors 2 ₁ to 2 ₆₃ . Therefore, in the comparators 1 ₁ to 1 ₂₅₅ , a fine level detection is performed for an input voltage of a low level with respect to the input analog signal, and a coarse level detection is performed for an input voltage of a high level. Is done.

An input analog signal is supplied from the analog signal input terminal, and the voltage level of the supplied input analog signal is detected by the comparators 1 ₁ to 1 ₂₅₅ by the reference voltage generated by the ladder resistors 2 ₁ to 2 ₂₅₅ . Then, the outputs of these comparators 1 ₁ to 1 ₂₅₅ are
It is supplied to a decoder 3 having input terminals corresponding to the numbers of these comparators 1 ₁ to 1 ₂₅₅ . This decoder 3
The supplied outputs of the comparators 1 ₁ to 1 ₂₅₅ are decoded to obtain 8-bit digital data D0 to D7.

FIG. 2 shows the relationship of the digital data output from the decoder 3 with respect to the input analog signal supplied to the A / D converter. The level of the input analog signal is standardized by the reference voltages Vt and Vb. Since the standardized level is weighted by the ladder resistors 2 ₁ to 2 ₂₅₅ as described above,
The output data from the decoder 3 has 128 levels up to 1/4 of (Vt-Vb) of the input analog signal.
64 levels from / 4 to 2/4, and 2/4
Levels up to 4/4 are output as digital values in 64 steps.

That is, the digital value is digitized in a finer step at a low level of the input analog signal, and is digitized in a coarser step at a high level of the input analog signal. Generally, in the image pickup signal obtained by the image pickup by the CCD, for a low level signal,
Unless the gradation accuracy is increased, the image quality is significantly deteriorated during reproduction based on this image pickup signal. On the other hand, with respect to the high-level image pickup signal, the deterioration of the image quality during reproduction is not noticeable even if the gradation accuracy is rough. So, like this,
If the level of the input analog signal is weighted during A / D conversion, gradation accuracy can be substantially improved.

The digital output thus obtained by the decoder 3 is supplied to the denier circuit 4. The denier circuit 4 is a circuit for inversely weighting the digital data having the characteristic shown in FIG. 2 and converting it into digital data having the linear characteristic. The denier circuit is composed of a lookup table such as a ROM. It may also be configured in combination with a shift multiplier and an adder.

FIG. 3 shows an example of input / output characteristics of the denier circuit 4. Input level '0' whose level is detected by ladder resistance 2 ₁₂₈ to 2 ₂₅₅ whose resistance value is R during digital conversion.
The data of "-127" is "0"-"127" as it is.
Is output at the level of. On the other hand, the data of the input levels '128' to '191', which are detected by the ladder resistances 2 ₆₄ to 2 ₁₂₇ having the resistance value of 2R, are '128' to
It is extended to the level of '255'. Also, the resistance value is 4R
The data of the input levels '192' to '255', which have been detected by the ladder resistances 2 _{1 to} 2 ₆₃ , are '256' to
It is extended to the level of '511'.

As described above, when the level of the input analog signal is detected, the detection accuracy is changed according to the level of the input signal. Therefore, substantially 9 bits of data are digitally converted into 8 bits. Can have the accuracy of. The output from the denier circuit 4 is 9 from O0 to O8.
It is output as digital data having a bit data width.

Although the present invention is applied to the 8-bit A / D converter in the above description, the present invention is not limited to this example. That is, the present invention can be applied to A / D converters with higher bits such as 10 bits and 16 bits. Also, of course, it can be applied to an A / D converter having a bit lower than 8 bits.

[0021]

As described above, according to the present invention, the ladder resistance used for detecting the level of the input analog signal is changed according to the level of the input analog signal. Therefore, by using the present invention, there is an effect that a highly accurate A / D converter for 1 bit can be configured without increasing the circuit scale.

Further, according to the present invention, the gradation of the low level signal is finely detected, the gradation of the high level signal is roughly detected, and the input analog signal is digitally converted. Therefore, by using the A / D converter according to the present invention as an A / D converter for a video signal with respect to a CCD output of a digital video camera, a case where a fine A / D converter with a gradation of 1 bit is used There is an effect that the same image quality can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a configuration of an A / D converter according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing an example of a relationship of digital data output from a decoder with respect to an input analog signal.

FIG. 3 is a schematic diagram showing an example of input / output characteristics of a denier circuit.

[Explanation of symbols]

1 ₁ to 1 ₂₅₅・ ・ ・ Comparator 2 ₁ to 2 ₂₅₅・ ・ ・
Ladder resistance, 3 ... Decoder, 4 ... Denny circuit

Claims (4)

[Claims] 1. In a parallel comparison type A / D converter, a plurality of comparators for detecting a voltage level of an input analog signal with a predetermined number of bits, and a reference voltage for each of the plurality of comparators are generated. It has a ladder resistance and a decoder for converting the outputs of the plurality of comparators into digital data, and the ladder resistance of the ladder resistance is adjusted so that the converted digital data has a nonlinear characteristic with respect to the characteristic of the input analog signal. A / characterized by setting the resistance value
D converter. 2. The A / D converter according to claim 1, wherein the ratio of the resistance values of the ladder resistors is L when the dynamic range of the input analog signal is standardized to 0 to 1.
From the value on the SB side, 1 in the range of 0 to 1/4, 1/4 to 1 /
An A / D converter characterized in that it is 2 in the range of 2 and 4 in the range of 1/2 to 1. 3. The A / D converter according to claim 1, further comprising a denier circuit supplied with the output of the decoder, wherein the denier circuit converts the digital data converted into the nonlinear characteristic into a linear characteristic. An A / D converter characterized by converting to. 4. The A / D converter according to claim 2, further comprising a denier circuit to which the output of the decoder is supplied, wherein the denier circuit is LSB for the output data supplied from the decoder. To MSB, 0 to
1 in the range of 1/2 and 2 in the range of 1/2 to 3/4
An A / D converter characterized in that the digital data converted by the non-linear conversion characteristic is converted into a linear characteristic by doubling and quadrupling in a range of 3/4.