JPH06177757A - A/d converter - Google Patents

Abstract

PURPOSE:To obtain an A/D converter from which data with high accuracy are obtained with simple configuration. CONSTITUTION:An analog input signal VA is fed to an A/D converter 4, from which a high-order bit VB1 is obtained and it is fed to D/A converters 5, 6, 7 and an average value of DA conversion outputs is subtracted from an analog input signal VA at a subtractor 8. The subtraction output is fed to an A/D converter 9 to obtain a low-order bit VB2. Thus, digital data with high accuracy are obtained without increasing the accuracy of the A/D converter itself.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AD converter for converting an analog signal such as a video signal into a digital signal.

[0002]

2. Description of the Related Art In recent years, with the progress of digital signal processing technology, an analog image pickup signal obtained from an image pickup device such as a CCD is converted into a digital signal using an AD converter, and the digital image pickup signal is converted into a digital signal processing circuit. In addition to the above, many image pickup apparatuses have been proposed which form a composite video signal by performing signal processing such as gamma correction, clipping, and blanking.

In such an image pickup apparatus, since the deterioration of the signal is very small in principle in the digital signal processing section, the conversion error characteristic of the AD converter becomes very important. Conventionally, many AD converters having a conversion bit number of 8 to 10 bits have been widely used, and as a method thereof, a data rate of an image pickup signal (10 to 20 MH
The flash type and the half flash type are widely used to meet the requirement z). The flash type has the number of gradations represented by conversion bits (for example, 256 for 8 bits)
This is a method in which the reference voltage of one lesser number (for example, 255) and the analog input signal are simultaneously compared by the same number of comparators.

Further, the half flash type uses two stages of flash type having a small number of gradations and coarsely converts the first stage,
This is DA converted, subtracted from the analog input signal, the subtracted output is again finely converted in the second stage, and the output of the first stage is output as the upper bit and the output of the second stage is output as the lower bit. is there.

[0005]

However, the image pickup device using the conventional AD converter described above has the following problems.

In the conversion characteristics of the AD converter, if there is a portion where the error increases at a specific level, contour noise (pseudo contour) is generated in a part of the image. In particular, in the case of the image pickup apparatus using the half flash type AD converter described above, a large conversion error occurs at the point where the upper bits change.

As a method for solving this, conventionally, there is a method of finely adjusting the reference voltage by trimming a resistor or the like on the IC circuit by laser trimming, but there is a problem that the cost becomes very high.

The present invention has been made to solve the above problems, and an object thereof is to provide an inexpensive and highly accurate AD converter.

[0009]

A first AD converter to which an analog input signal is added, a DA converter to which the AD conversion output is added, and a subtractor for subtracting the DA conversion output from the analog input signal. An AD converter having a second AD converter to which the output of the subtractor is added and which has a finer resolution than the first AD converter,

In the first invention, a plurality of the DA converters are provided in parallel, and the average value of each DA conversion output or one DA conversion output thereof is added to the subtractor.

In the second aspect of the present invention, switching means for switching the reference voltage for determining the range of the first AD converter is provided.

According to a third aspect of the invention, a correction data generating section for generating correction data according to the output of the first AD converter is provided, and the correction data is added to the subtractor.

[0013]

According to the first to third aspects of the invention, the higher bit of the data obtained by AD-converting the analog input signal is obtained from the first AD converter, and the subtracter subtracts the first AD converter and the DA from the analog input signal. An analog signal from which the error due to the converter is removed is obtained, and this is used as the second AD
By adding it to the converter, lower-order bits with higher accuracy can be obtained than the second AD converter.

[0014]

The first to sixth embodiments of the present invention applied to an image pickup apparatus will be described below.

FIG. 1 shows a first embodiment of the present invention.

In FIG. 1, 1 is an optical system including an image pickup lens, an optical filter and the like, 2 is a CCD as an image pickup device, and 3
Is a sample and hold circuit, 4 is an AD converter,
Reference numerals 5, 6, and 7 are DA converters, 8 is a subtractor, 9 is an AD converter, 10 is a process circuit including a digital signal processing circuit, 11 is a DA converter, and 12 is an output terminal.

Next, the operation of the above configuration will be described.

The subject image is formed on the image pickup surface of the CCD 2 by the optical system 1 and photoelectrically converted by each pixel of the CCD 2 to generate an image pickup signal. The image pickup signal is converted into an analog input signal VA as a continuous signal by the sample and hold circuit 3, and then AD converted by the AD converter 4. This output is input to the process circuit 10 and the DA converters 5, 6 and 7 as the upper bit VB1 of the digital image pickup signal.
In the DA converters 5, 6 and 7, the input signal is D
A conversion is performed, and the resulting analog signal is output.

At this time, each output is the DA converter 5,
Errors are included due to variations in, for example, the resistance group and the switch group that form the elements 6 and 7. These outputs are
It is input to the subtractor 8 together with the output of the sample and hold circuit 3. In the subtractor 8, three DA converters 5, from the output VA of the sample and hold circuit 3,
The average value of the outputs of 6 and 7 is subtracted.

The output of the subtractor 8 is AD-converted by the AD converter 9 to obtain the lower bit V of the digital image pickup signal.
B2 is input to the process circuit 10 together with the upper bit VB1.

In this case, the input range of the AD converter 4 is set to the full range of the output of the sample-and-hold circuit 3 because the AD converter 4 generates upper bits. The input range of the AD converter 9 is
Since this AD converter 9 generates the lower bit, A
The resolution is set to almost the minimum resolution of the D converter 4. For example,
When the AD converter 4 has a 4-bit resolution, the input range of the AD converter 9 is set to 1/16 of the AD converter 4.

In the process circuit 10, the input digital image pickup signal is subjected to predetermined processing such as gamma correction, black and white clipping, and blanking processing by the digital signal processing circuit to form a digital video signal. Next, DA conversion is performed by the DA converter 11, which is output as a composite video signal from the output terminal 12, and is output to the TV, VTR in the subsequent stage.
Etc. to external equipment.

FIG. 2 shows a second embodiment of the present invention, and FIG.
The same reference numerals denote the same functional parts.

In FIG. 2, 13 is a DA converter 5,
A switch for switching the outputs of 6 and 7.

Next, the operation will be described. The operations up to the DA converters 5, 6 and 7 are the same as those in FIG.
The outputs of the DA converters 5, 6, 7 are input to the switch 13. The switch 13 selects one of the three input signals and inputs it to the subtractor 8. The output of the subtractor 8 is subtracted from the output signal VA of the sample-and-hold circuit 3, and the subtracted output is added to the AD converter 9 to generate the lower bit VB2, and the same operation as described above is performed.

The switch 13 is used, for example, when the device is manufactured.
The DA converters 5, 6, and 7 having the smallest error are selected and selected. Alternatively, one of the three is set so that the error is minimized depending on the usage conditions such as the power supply voltage.

FIG. 3 shows a third embodiment of the present invention, and shows only parts different from those in FIGS.

In FIG. 3, reference numeral 14 is a switching signal generating circuit. The output of the AD converter 4 becomes the high-order bit VB1 of the digital image pickup signal as described above, and is input to the process circuit 10 and the three DA converters 5, 6 and 7, and also to the switching signal generation circuit 14. Switching signal generating circuit 14 generates a switching signal in response to an input signal indicating upper bit VB1 to be input, and switches 13
To output one of the output signals of the DA converters 5, 6 and 7 to the subtractor 8.

As an output signal corresponding to a certain input signal of the switching signal generation circuit 14, one having the smallest error among the DA converters 5, 6, 7 is selected in advance for each level of the input signal. The error may be measured and stored in the internal memory of the switching signal generation circuit 14.

As another example, a sequential circuit or a random number circuit may be provided inside the switching signal generating circuit 14 to generate a switching signal that changes in time series. By doing so, the errors of the DA converters 5, 6, 7 are dispersed.

In each of the above embodiments, the subtractor 8
Although three DA converters 5, 6, and 7 are combined with the above, the present invention is not limited to this, and may be two as long as the effect is sufficient, or four or more D if more precision is required.
A converter may be used, and if the number used is increased,
The error of the DA converter is reduced.

FIG. 4 shows a fourth embodiment of the present invention, which is an embodiment in which the circuit of FIG. 1 is formed on a single semiconductor chip.

In FIG. 4, the AD converters 4 and 9, the DA converters 5, 6, and 7 and the subtractor 8 in FIG. 1 are arranged on a single semiconductor chip 15 as shown in the figure. Further, an input terminal 16 connected to the sample and hold circuit 3 and an output terminal 17 connected to the process circuit 10 are provided. Especially in these arrangements, D
The A converters 6 and 7 are arranged so that the A converters 6 and 7 are arranged at right angles to the DA converter 5.
And 7 are arranged in line symmetry. By arranging in this way, it becomes possible to disperse the error generated in each of the DA converters 5, 6, and 7 caused by the deviation in the semiconductor manufacturing process.

The single semiconductor chip 15 shown in FIG.
The portion configured above is not limited to this, and the process circuit 10, the sample-and-hold circuit 3, and the like can be configured on the same semiconductor chip 15. Further, the switch 13, the switching signal generating circuit 14 and the like in FIGS. 2 and 3 may be configured.

FIG. 5 shows a fifth embodiment of the present invention, and FIG.
The same parts as those in FIG.

In FIG. 5, reference numeral 18 denotes a switching signal generating circuit, which is AD according to the horizontal synchronizing signal HD and the vertical synchronizing signal VD.
A switching signal S for switching the operation of converter 4 is output. In this embodiment, the output of the AD converter 4 is added to one DA converter 5.

FIG. 6 shows an embodiment of the AD converter 4, 101 is an input terminal of the analog input signal VA from the sample and hold circuit 3, 102 is an input terminal of the switching signal S, and V1 and V2 are reference voltages. , 103, 10
4 is a switch, 105, 106, 107 and 108 are resistors connected in series, 109, 110 and 111 are comparators, and 112 is a decoder for converting an input signal into a binary number.

Next, the operation will be described. In FIG. 5, the switching signal generating circuit 18 generates a switching signal S for dispersing the error of the AD converter 4 according to the horizontal synchronizing signal HD and the vertical synchronizing signal VD. AD converter 4
Switches the internal operation according to the switching signal S to disperse the conversion error.

The analog input signal VA input from the input terminal 101 in FIG.
0 and 111 compare with the reference voltage of the other input terminal of each, and the result is input to the decoder 112,
It is output as digital data. Each comparator 1
The other input terminals of 09 to 111 have reference voltages V1 and V
2, the reference voltage generated in the circuit configured by the switches 103 and 104 and the resistors 105 to 108 is input. The switches 103 and 104 are switched according to the switching signal S from the input terminal 102.

At this time, the switching signal S is 0 in the current path.
At the time of, V1, switch 103, resistors 105, 106,
107 and 108, the switch 104, and V2. Also,
When the switching signal S is 1, V1, switch 104, resistors 108, 107, 106, 105, switch 103, V
2, the direction of the current flowing through the resistors 105 to 108 is opposite to that when the switching signal S is 0. At this time, each resistor includes a manufacturing error, and the input offset characteristics of the comparators 109 to 111 also vary. However, by switching the switches 103 and 104 as described above, this variation is dispersed. can do.
At this time, the correspondence between the outputs of the comparators 109 to 111 and the binary number changes according to the switching of the switches 103 and 104. Therefore, the decoder 112 corrects this according to the switching signal S and outputs the upper bit VB1. .

The switching signal S is generated by the switching signal generation circuit 18 so as to switch line-by-line or field-by-field sequentially or randomly in order to disperse the variations in this way.

In FIG. 5, the output VB of the decoder 112
1 is output to the DA converter 5, and the DA conversion output is input to the subtractor 8 together with the output VA of the sample and hold circuit 3. In the subtractor 8, the output of the DA converter 5 is subtracted from VA and output to the AD converter 9.

Note that, in FIG. 6, the 2-bit AD converter 4 is configured with three comparators for the sake of simplification of description, but the number of comparators is not limited to this, and an arbitrary number of conversion bits is provided. n AD converter is 2 n
It can be realized by a power of −1 comparator.

FIG. 7 shows another embodiment of the AD converter 4, and the same reference numerals as those in FIG. 6 indicate the same functional portions.

In FIG. 7, 113, 114, 115,
Switches 116 and 117 switch terminals 0 to 3 respectively by a switching signal S. Analog input signal VA
Are the comparators 109, 110, 111 as in FIG.
To the binary number by the decoder 112 and output as the upper bit VB1.

Further, V1, V2 and switches 113 to 11
6. A reference voltage is generated by the resistors 105 to 108 and input to the other input terminal of the comparators 109 to 111.

By the switching signal S, the switches 113 to 1
When 17 is switched, the path of the current flowing through the resistors 105 to 108 also changes. For simplification of explanation, only the resistors corresponding to the current paths are given as follows.

When S = 0 105-106-107-108 When S = 1 106-105-108-107 When S = 2 107-108-105-106 When S = 3 108-107-106- 105, and the current path changes according to S. Further, the switch 117 is switched so that the voltage at the midpoint of the current path is always applied to the comparator 110. Decoder 112
Switches the relationship between the input and the binary number according to the four values of S and outputs the upper bit VB1 as the binary number output signal.

FIG. 8 shows a sixth embodiment of the present invention, and FIG.
The same reference numerals denote the same functional parts.

In FIG. 8, reference numeral 19 denotes a correction data generator, which is a ROM 20 in which correction data is written in advance.
And a DA converter 21 that DA-converts the correction data and outputs it to the subtractor 8.

FIG. 9 shows an example of the configuration of the AD converter 4, and parts corresponding to those in FIGS. 6 and 7 are designated by the same reference numerals.

The AD converter 9 is also constructed in the same manner as the AD converter 4 with four series resistors, three comparators and a decoder.

The number of comparators in the AD converters 4 and 9 is composed of three for upper bits and three for lower bits for simplification of description, but is not limited to this.
For example, in order to configure the 8-bit AD converters 4 and 9, a combination using 15 comparators is also possible.

Next, the operation will be described. In FIG. 9, the analog input signal V input from the input terminal 101
First, A is compared with respective reference voltages obtained by dividing the reference voltage V1 by the resistors 105 to 108 by the comparators 109 to 111. In this case, the reference voltage V1 is, for example, V in accordance with the dynamic range of the analog input signal VA.
When A is 0 to 2V, V1 is also set to 2V. As a result, the resistances 105 to 108 cause 1.5V, 1V, 0.
A reference voltage of 5V is generated.

The outputs of the comparators 109 to 111 are converted into binary numbers by the decoder 112. The output is output as the upper bit VB1 and is also input to the DA converter 5. Therefore, in this example, an output of 0V, 0.5V, 1V, or 1.5V is obtained from the DA converter 5. The output of the decoder 112 is further input as the address of the ROM 20 to the correction data generation unit 19 of FIG. The ROM 20 has the resistors 105 to 10
8, comparators 109 to 111 and DA converter 5
The correction data for correcting the error is written in advance.

The correction data read from the ROM 20 is DA converted by the DA converter 21. The output range of the DA converter 21 at this time is adjusted to the maximum value of the generated error. The outline is set to positive and negative values for one to several gradations of the reference voltage group output from the three resistors forming the AD converter 9 for lower bits.

The outputs of the DA converter 21, the DA converter 5, and the analog input signal VA are input to the subtractor 8, and the outputs of the two DA converters 5 and 21 are subtracted from the analog input signal VA. The subtraction output is AD
It is input to the three comparators forming the converter 9 and compared with the reference voltage divided by the four series resistors. The reference voltage applied to one end of the four series resistors is one gradation of the reference voltage group generated by the AD converter 4. In this example, one gradation is 0.5V, so
The reference voltage applied to the four series resistors is set to 0.5V, and the resistances of 0.3725, 0.25, 0.
A 125V reference voltage group is generated.

The output of the AD converter 9 is the lower bit VB.
2 is output together with the above-mentioned upper bit VB1.

FIG. 10 is a diagram for explaining the operation of FIG. Figure 10
(A) shows the conversion characteristics of the AD converter 4, (b) shows the value of the upper bit VB1 at that time, (c) shows the value of the lower bit VB2 at that time, and (d) shows the level of the correction data at that time.

First, in (a), the conversion characteristic when no correction data is input is indicated by A (solid line). At this time, in (b), when the high-order bit VB1 changes, B is caused by the errors of the resistors 105 to 108, the comparators 109 to 111, and the DA converter 5 as described above.
The characteristics deviate from the theoretical characteristics indicated by (broken line) by an error e.

The correction data generating section 19 generates the correction data of (d) according to the value of the upper bit VB1 of (b). If the value f at this time is e = f, the characteristic of A is theoretically calculated. It can be corrected to the characteristic of the value B.

FIG. 11 shows another embodiment of the correction data generating section 19, in which the same functional parts as in FIG. 9 are designated by the same reference numerals.

In FIG. 11, reference numeral 22 is a power supply detection circuit which generates a power supply detection signal of a predetermined width when power is turned on, 23 is an address generation circuit which generates a predetermined address in a predetermined order according to the power supply detection signal, 24, 25 is a switch, 26 is R
AM.

When the power supply is turned on, the power supply detection circuit 22 detects this and generates a power supply detection signal of a predetermined width, and the switch 24 is placed on the output side of the address generation circuit 23 and the switch 25.
Are connected to the output side of the ROM 20 and RA
Switch M26 to write operation. Next, the address generation circuit 23 generates a predetermined address in a predetermined order as described above, and this is input to the RAM 26 and the ROM 20 as an address. Predetermined correction data is read from the ROM 20 and written in the RAM 26.

After that, the address from the address generation circuit 23 stops, and the power supply detection signal disappears so that the switch 24 is switched to the AD converter 4 side and the switch 25 is switched to the DA converter 21 side. Then, the correction data written in the RAM 26 is read according to the input upper bit VB1, is DA converted by the DA converter 21, and is input to the AD converter 4 as a correction signal.

FIG. 12 is a diagram for explaining the above operation. When the power is turned on and the power supply voltage rises as shown in FIG.
As shown in (b), the power detection signal from the power detection circuit 22 is T
It is delayed by one and output in the T2 period. During this T2 period,
The addresses of (c) are sequentially output, and the data of the ROM 20 is written in the RAM 26 in the write mode as shown in (d).

As described above, by using the RAM 26, the correction can be performed without deteriorating the conversion speed.

Although each of the first to sixth embodiments described above is a case where the present invention is applied to an image pickup apparatus, the present invention can be used when converting an analog signal into a digital signal in other electronic equipment. Of course.

[0069]

As described above, according to the first invention, a plurality of DAs are used.
A converter was provided and configured to subtract the average value of their outputs or one output with the analog input signal. The second aspect of the invention is configured to switch the reference voltage that determines the range of the first AD converter. The third invention is
The correction data is generated according to the output of the first AD converter and is added to the subtractor.

Therefore, according to the present invention, it is possible to obtain output data having high accuracy with respect to an analog input signal with a simple structure without increasing the accuracy of the AD converter itself. Further, when used in an image pickup device, there is an effect that a device capable of obtaining high image quality can be obtained at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a fifth embodiment of the present invention.

FIG. 6 is a configuration diagram showing an embodiment of an AD converter.

FIG. 7 is a configuration diagram showing another embodiment of the AD converter.

FIG. 8 is a block diagram showing a sixth embodiment of the present invention.

FIG. 9 is a configuration diagram showing another embodiment of the AD converter.

FIG. 10 is a timing chart showing the operation of the sixth embodiment.

FIG. 11 is a block diagram showing an embodiment of a correction data generation unit.

FIG. 12 is a timing chart showing another operation of the sixth embodiment.

[Explanation of symbols]

 4 AD converter 5, 6, 7 DA converter 8 Subtractor 9 AD converter 18 Switching signal generation circuit 19 Correction data generation unit 103, 104, 113 to 116 switch

Claims (3)

[Claims] 1. A first A to which an analog input signal is applied.
D converter and a plurality of D to which outputs from the first AD converter are added
A converter, a subtractor for subtracting the average value of the outputs of the plurality of DA converters or one of the outputs and the analog input signal, and the output of the subtractor is added to the first AD converter. An AD converter comprising a second AD converter having a fine resolution. 2. A first A to which an analog input signal is applied.
A D converter, a DA converter to which the output of the first AD converter is added, a subtracter for subtracting the output of the DA converter and the analog input signal, and an output of the subtractor to add the first AD A second AD converter having a finer resolution than that of the converter, and switching means for switching a reference voltage for determining the operating range of the first AD converter, respectively.
D converter. 3. A first A to which an analog input signal is applied.
A D converter, a correction data generation unit that generates correction data according to the output of the first AD converter, a DA converter to which the output of the first AD converter is added, an output of the DA converter, and the correction data And an analog input signal, and a subtractor for subtracting the analog input signal, and a second AD converter having a finer resolution than the first AD converter to which the output of the subtractor is added.