JP2014138364A - Imaging element and imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption without deteriorating image quality in an imaging element performing AD conversion in two divided steps on a signal from a pixel.SOLUTION: An imaging element converts a signal from a pixel to a digital signal by comparing a signal supplied from pixels arranged in a matrix shape through a column signal line arranged for each column with reference voltage which changes with the lapse of time. In the conversion; the imaging element performs AD conversion by dividing the signal into high-order bits and low-order bits, and switches whether to perform AD conversion on the low-order bits or not according to a result of AD conversion on the high-order bits. When the result of the AD conversion on the high-order bits shows that a value of the low-order bits is in a region having no influence on image quality, the imaging element stops the AD conversion on the low-order bits to reduce power consumption.

Description

  The present invention relates to an imaging element and an imaging apparatus having the imaging element.

  Imaging devices such as digital video cameras and digital still cameras are generally supplied with power from a battery, and electronic parts mounted on the imaging device have low power consumption in order to realize long-time shooting with the imaging device. It is hoped that. An imaging element that converts light into an electrical signal is an example of a main electronic component mounted on the imaging apparatus. As typical imaging devices, a CCD (Charge Coupled Device) type imaging device and a CMOS (Complementary Metal-Oxide Semiconductor) type imaging device are known. Among these, as a conventional CMOS image sensor, an electric signal read from a plurality of pixels arranged in a matrix is AD-converted by an analog / digital (AD) conversion circuit provided for each column. An image sensor that outputs a digital signal obtained by AD conversion in units of rows has been proposed (see, for example, Patent Document 1).

  FIG. 9 is a diagram showing a part of the configuration of a conventional image sensor. A conventional CMOS image sensor has a pixel array in which a plurality of unit pixels that convert an optical signal into an electrical signal (voltage) are arranged in a matrix, and outputs a signal from the pixel for each column of the pixel array. A line 906 is provided. An AD conversion unit 908 that converts a signal read from a pixel into a digital signal includes an AD conversion circuit 901 provided for each pixel column. The AD conversion circuit 901 includes a comparator 909, a power down control unit 910, and a counter 911. The comparator 909 compares the voltage of the column signal line 906 with a reference voltage (ramp signal) RAMP. The power down control unit 910 controls power supply to the comparator 909. The counter 911 counts the time until the output logic of the comparator 909 is inverted.

  The power-down control unit 910 includes a buffer 902 that converts a voltage amplitude, and a flip-flop 903 that prevents an unstable operation of a logic circuit due to voltage swingback. The counter 911 includes a logical sum operation circuit (OR circuit) 904 and a counter circuit 905. The OR circuit 904 supplies a clock to the counter circuit 905 based on the clock ADCLK and the output of the flip-flop 903. The counter circuit 905 counts the comparison time in the comparator 909 based on the output of the OR circuit 904.

  The conventional CMOS type image pickup device includes AD conversion circuits 901 corresponding to the number of columns of unit pixels, and the current consumption of the AD conversion unit 908 including these is problematic. Specifically, when the bias current of the comparator 909 in each column is about 10 μA and the number of columns is about 2500, the consumption current of the AD conversion unit 908 is 25 mA. Therefore, in the conventional imaging device, power consumption is reduced by cutting off the power supply to the comparators of the columns for which AD conversion has been completed.

  FIG. 10 is a diagram showing a part of the operation of a conventional CMOS image sensor. At the start of the AD conversion process, the flip-flop 903 and the counter circuit 905 are reset and the supply of the clock ADCLK is started. The flip-flop 903 outputs a high level signal when reset. When the output of the flip-flop 903, that is, the power-down signal output from the power-down control unit 910 is at a high level, the comparator 909 is in an operating state. Prior to time t0, since the reference voltage RAMP is smaller than the voltage of the column signal line 906, the output of the comparator 909 is at a low level. Further, since the output of the flip-flop 903 is at a high level, the clock ADCLK is supplied to the counter circuit 905. Thereby, the counter circuit 905 performs a counting operation according to the clock ADCLK.

  When the voltage of the column signal line 906 coincides with the reference voltage RAMP at time t0, the output of the comparator (comparator) 909 changes from low level to high level. The flip-flop 903 holds the high level at the rising edge of the output of the comparator 909 and then outputs the low level. Since the clock ADCLK is not supplied to the counter circuit 905 while the output of the flip-flop 903 is at a low level, the counter circuit 905 holds the count value at time t0. Further, since the power-down signal that is the output of the power-down control unit 910 is at a low level, the supply of power to the comparator 909 is stopped. Here, since the voltage output to each column signal line 906 differs according to the amount (luminance) of light incident on the pixel, the timing at which the plurality of comparators 909 are stopped is different. As described above, in the related art, the current consumption of the AD conversion unit 908 is reduced by sequentially stopping the AD conversion circuit 901 from which AD conversion has been completed among the plurality of AD conversion circuits 901.

JP 2009-159271 A

  However, the above-described method is a technique that can be applied to an image sensor that converts a signal from a pixel into a digital value by one AD conversion. An image sensor that performs AD conversion by dividing a signal from a pixel into two or more times has room for improvement in reducing power consumption. An object of the present invention is to reduce power consumption without degrading image quality in an image sensor that performs AD conversion by dividing a signal from a pixel into a plurality of times.

  An imaging device according to the present invention includes a plurality of pixels including photoelectric conversion elements arranged in a matrix, and a column that is arranged for each column of the plurality of pixels and outputs a signal from the plurality of pixels for each column. A signal line; reference voltage generating means for outputting a reference voltage whose voltage changes with a predetermined slope as time passes; a signal from the pixel supplied via the column signal line; and the reference voltage. Analog-to-digital conversion means for converting the signal from the pixel into analog signals, and converting the digital signals into high-order bits and low-order bits. A second analog-to-digital conversion for analog-to-digital conversion of the lower-order bits in accordance with a result of the first analog-to-digital conversion for analog-to-digital conversion of the upper bits. And switches whether Ukaina.

  According to the present invention, in an imaging device that performs AD conversion by dividing a signal from a pixel into upper bits and lower bits, whether to perform AD conversion of lower bits is switched according to the result of AD conversion of upper bits. Thus, power consumption can be reduced without degrading the image quality.

It is a figure which shows the structural example of the imaging device which concerns on embodiment of this invention. It is a figure which shows the structural example of the image pick-up element in this embodiment. It is a figure which shows the structural example of the AD conversion part in this embodiment. It is a figure which shows the structural example of the comparator in this embodiment. It is a timing chart which shows the operation example of the normal output area | region of the AD conversion part in this embodiment. It is a timing chart which shows the operation example of the low output area | region of the AD conversion part in this embodiment. It is a timing chart which shows the operation example of the high output area | region of the AD conversion part in this embodiment. It is a figure which shows an example of the gamma curve which concerns on this embodiment. It is a figure which shows a part of structure of the conventional image pick-up element. It is a figure which shows a part of operation | movement of the conventional image pick-up element.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration example of an imaging apparatus according to an embodiment of the present invention. In FIG. 1, an optical system 101 forms a subject image on a light receiving portion of a CMOS image sensor. The optical system 101 includes a zoom lens, a diaphragm mechanism, and the like disposed in a lens barrel (not shown). Each mechanism of the optical system 101 performs control such as autofocus by mechanically driving each part under the control of a CPU (Central Processing Unit) 104.

  The imaging unit 102 images a subject using a CMOS image sensor. The imaging unit 102 performs processing such as AGC (automatic gain control), OB (optical black) clamping, and analog / digital (AD) conversion on the output signal of the CMOS image sensor to generate a digital imaging signal. And output. The imaging unit 102 outputs an imaging signal to a DSP (Digital Signal Processor) 107 provided in the system control unit 103.

  The system control unit 103 includes a CPU 104, a ROM (Read Only Memory) 105, a RAM (Random Access Memory) 106, a DSP 107, an external interface 108, and the like. The CPU 104 executes the supplied processing program using the ROM 105, the RAM 106, and the like, and controls the entire system by sending instructions to each unit of the imaging apparatus. The ROM 105 is for storing information such as firmware for driving the imaging apparatus, and the RAM 106 is for temporarily storing control information of the imaging apparatus.

  The DSP 107 performs various types of signal processing on the imaging signal from the imaging unit 102 to generate a still image or moving image video signal (for example, a YUV signal) in a predetermined format. The external interface 108 is provided with various encoders and digital analog (DA) converters. Various control signals and data are exchanged via the external interface 108 between the system control unit 103 and external elements connected to the system control unit 103 (in this example, the display 112, the memory medium 109, the operation panel 111, etc.). Is called.

  The display 112 is a display device that is incorporated in the imaging device and displays a captured image. In addition to the display device incorporated in the imaging device, it is of course possible to transmit the image data to an external display device for display. The memory medium controller 110 performs control related to the memory medium 109 that can appropriately store images taken on various memory cards and the like. The memory medium 109 is a replaceable memory medium. For example, in addition to various memory cards, a disk medium using magnetism or light can be used. The operation panel 111 is provided with input keys for a user to give various instructions when performing a shooting operation or the like with the imaging apparatus. The CPU 104 monitors an input signal from the operation panel 111 and executes various operation controls based on the input content.

  FIG. 2 is a block diagram illustrating a configuration example of the imaging element of the imaging unit 102 in the present embodiment. 2 is a CMOS image sensor, and includes a pixel array 201, a row scanning unit (vertical scanning unit) 202, an AD conversion unit 203, a reference voltage generation unit 204, a column scanning unit (horizontal scanning unit) 205, An output unit 206 and a timing control unit 207 are included. The pixel array 201 has a plurality of unit pixels 208 arranged in a matrix. The unit pixel 208 is connected to a column signal line 213 arranged for each pixel column and a row control line 214 arranged for each pixel row. The unit pixel 208 includes a photoelectric conversion element, and converts received light into a signal voltage. A signal voltage obtained by photoelectric conversion in the unit pixel 208 is output to the AD conversion unit 203 via the column signal line 213.

  The row scanning unit 202 performs row scanning that sequentially selects pixel rows in the pixel array 201. The AD conversion unit 203 includes a plurality of AD conversion circuits 301 provided for each column signal line 213, and converts signal voltages from the pixels 208 output to the plurality of column signal lines 213 into digital signals in parallel. . The reference voltage generation unit 204 generates a reference voltage RAMP whose voltage changes with a predetermined slope as time passes. As the reference voltage RAMP, an upper bit conversion reference voltage (course DAC) used for AD conversion of the upper bits and a lower bit conversion reference voltage (fine DAC) used for AD conversion of the lower bits are supplied from the reference voltage generation unit 204 to each column. It is supplied to the provided comparator 209. The column scanning unit 205 performs column scanning that sequentially selects pixel columns. The output unit 206 outputs a digital signal obtained by AD conversion in the AD conversion unit 203 to the outside. A timing control unit 207 controls operation timings of the row scanning unit 202, the AD conversion unit 203, the reference voltage generation unit 204, and the column scanning unit 205. A timing control clock MCLK is supplied from the CPU 104 to the timing control unit 207.

  The AD conversion circuit 301 includes a comparator 209, a power down control unit 210, and an up / down counter 211. The comparator 209 compares which of the voltage of the column signal line 213 and the reference voltage (ramp signal) RAMP is greater. The power down control unit 210 controls power supply to the comparator 209. The power-down control unit 210 outputs a control signal (power-down signal) related to power supply control of the comparator 209 to the comparator 209. The up / down counter 211 counts the count value using the clock ADCLK. The memory 212 is a memory that holds the count value of the up / down counter 211. The comparator 209 is supplied with an analog circuit power supply voltage, and the up / down counter 211 is supplied with a digital circuit power supply voltage.

  FIG. 3 is a diagram illustrating a configuration example of the AD conversion unit 203 in the present embodiment. The AD conversion unit 203 includes an AD conversion circuit 301 provided for each column signal line 213. Each of the AD conversion circuits 301 includes a comparator 209, a power-down control unit 210, and an up / down counter 211, and converts a voltage from a pixel output to the corresponding column signal line 213 into a digital signal. The comparator 209 compares the voltage of the column signal line 213 with the reference voltage (ramp signal) RAMP and outputs a comparison result. The power supply of the comparator 209 is controlled by a power down signal SPD supplied from the power down control unit 210.

  The power-down control unit 210 includes a buffer 302, a flip-flop 303, logical sum operation circuits (OR circuits) 308, 310, and 314, logical product operation circuits (AND circuits) 311 and 316, and an inverting circuit (NOT circuit) 315. . The up / down counter 211 includes AND circuits 304 and 312, an upper bit counter circuit 305, and a lower bit counter circuit 313.

  In the power-down control unit 210, the buffer 302 outputs the output of the comparator 209 having the amplitude of the analog circuit power supply voltage (eg, 3.3V) to the signal having the amplitude of the digital circuit power supply voltage (eg, 1.2V). Convert to and output. In the flip-flop 303, the output terminal of the buffer 302 is connected to the clock input terminal, and the power supply voltage VDD is connected to the data input terminal. The output of the flip-flop 303 is supplied to the NOT circuit 315, the AND circuit 316, and the AND circuits 304 and 312 of the up / down counter 211.

  The AND circuit 316 receives the output of the flip-flop 303 and its own output. The output of the flip-flop 303 is input to the OR circuit 308 via the NOT circuit 315 and the output of the AND circuit 316 is input. The NOT circuit 315 delays the input signal by one clock and inverts the logic to output it. The OR circuit 310 receives the signal SUP and the output of the AND circuit 316, and the OR circuit 314 receives the signal SLOW and the output of the AND circuit 316. The signals SUP and SLOW are signals output from the upper bit counter circuit 305 of the up / down counter 211.

  Here, each of the OR circuits 308, 310, and 314 performs determination on the power supply stop condition of the comparator 209. When the power supply stop condition is met, the OR circuits 308, 310, and 314 output. Becomes low level. The OR circuit 308 generates an output for stopping the power supply to the comparator 209 when the output of the flip-flop 303 is inverted for the second time. The OR circuit 310 outputs a signal to the comparator 209 when the count value of the upper bit counter circuit 305 exceeds an arbitrary upper limit value (first threshold value) and the output of the flip-flop 303 is inverted for the first time. Generates output to stop power supply. The OR circuit 314 outputs a signal to the comparator 209 when the output of the flip-flop 303 is inverted for the first time while the count value of the upper bit counter circuit 305 is below an arbitrary lower limit value (second threshold value). Generates output to stop power supply.

  The AND circuit 311 receives the outputs of the OR circuits 308, 310, and 314 and its own output, and outputs the output as a power down signal that is an output of the power down control unit 210. That is, when the power supply stop condition of the comparator 209 is met, a low level is input to the AND circuit 311 and the power down signal SPD becomes a low level. The AND circuit 311 maintains its state until reading of one pixel is completed when its output is input and the power supply to the comparator 209 is stopped.

  In the up / down counter 211, the AND circuit 304 receives the clock ADCLK and the output of the flip-flop 303, and the output is connected to the clock input terminal of the upper bit counter circuit 305. The AND circuit 312 receives the clock ADCLK, the output of the flip-flop 303 is inverted, and the output is connected to the clock input terminal of the lower bit counter circuit 313. That is, the AND circuit 304 provides a counting clock to the upper bit counter circuit 305, and the AND circuit 312 provides a counting clock to the lower bit counter circuit 313.

  The upper bit counter circuit 305 performs first analog / digital conversion for obtaining the value of the upper bit by AD conversion. The upper bit counter circuit 305 counts a period until the first inversion in the output of the comparator 209 (a period from the start of the comparison operation for the upper bit to the inversion of the output of the comparator 209). The lower bit counter circuit 313 performs second analog / digital conversion to obtain a lower bit value by AD conversion. The lower bit counter circuit 313 counts a period until the second inversion of the output of the comparator 209 (a period from the start of the comparison operation for the lower bits until the output of the comparator 209 is inverted).

  The upper bit counter circuit 305 outputs signals SUP and SLOW at a level corresponding to the count value. The signal SUP is normally at a low level, and is a signal that becomes a high level when the count value becomes larger than a certain upper limit value (greater than a first threshold value). The signal SUP can be easily realized by, for example, performing an AND operation on the bits of the first arbitrary digit or more among the bits representing each digit in binary number. Further, the signal SLOW is normally at a low level, and is a signal that becomes a high level when the count value becomes larger than a certain lower limit value (greater than a second threshold value). The signal SLOW can be easily realized by, for example, performing an AND operation on the bits of the second arbitrary digit or more among the bits representing each digit in binary number. Note that the second arbitrary digit is smaller than the first arbitrary digit.

  FIG. 4 is a diagram illustrating a configuration example of the comparator 209 in the present embodiment. The plurality of comparators 209 are connected to one drive current supply circuit 401 and receive supply of drive current. The output of the output buffer 402 is input to the buffer 302 of the power-down control unit, and is also input to the memory 403 for reference voltage switching control for upper bit AD conversion and lower bit AD conversion. The output of the memory 403 is supplied to the gate of the transistor 405 for switching the upper bit conversion reference voltage (course DAC) of the reference voltage RAMP. The transistor 406 is a transistor related to auto-zero operation control, and is on / off controlled by an auto-zero pulse PSET supplied to the gate.

  The transistor 407 is an input transistor on the reference voltage (RAMP) side, and the transistor 408 is an input transistor on the column signal line 213 side. The transistor 407 can supply the upper bit conversion reference voltage (course DAC) of the reference voltage RAMP to the gate via the transistor 405. The gate of the transistor 407 is connected to the other electrode of the capacitor 412 to which one electrode is supplied with the lower bit conversion reference voltage (fine DAC) of the reference voltage RAMP. The gate of the transistor 408 is connected to the other electrode of the capacitor 415 that has one electrode connected to the column signal line 213 and receives the output of the column signal line 213.

  The transistor 409 is for limiting the current flowing through the input transistors 407 and 408. The transistor 416 forms a current mirror with the drive current supply circuit 401. The transistors 410 and 411 are transistors for receiving the power down signal SPD from the power down control unit and cutting off the current supply from the drive current supply circuit 401 to the comparator. Note that the comparator 209 is not limited to the configuration illustrated in FIG. 4 and may be any configuration having a similar function. For example, the transistor 411 is connected in series to the drain side of the P-type transistor 416 constituting the drive current supply circuit 401 and the current mirror, but may be connected in series to the source side.

  Next, the operation of the AD conversion unit 203 related to AD conversion of the signal voltage output from the pixel 208 in the pixel row selected by the row scanning unit 202 via the column signal line 213 in the image sensor according to the present embodiment will be described. To do.

  FIG. 5 is a timing chart showing an operation example of the normal output region of the AD conversion unit 203 in the present embodiment. Here, a region where the signal value of the upper bits in the signal after AD conversion is from 0 level to a predetermined lower limit value or less (second threshold value or less) is defined as region A. Further, a range that is larger than the lower limit value and equal to or less than a predetermined upper limit value (first threshold value or less) is defined as a region B. Further, the range from the upper limit value to the maximum value that can be taken by the upper bits is defined as region C. For example, the normal output area of the AD conversion unit 203 corresponds to the area B, the low output area corresponds to the area A, and the high output area corresponds to the area C. The lower limit value corresponds to a black level that is a signal value of only a dark current component in a light-shielded state, and the upper limit value corresponds to a signal value near saturation in a JPEG signal described later. When the areas A, B, and C are described in terms of the AD conversion time of the upper bits, in the illustrated timing chart, the times t3 to t4 correspond to the area A, the times t4 to t6 correspond to the area B, and the time t6 to t7 correspond to the region C.

  In the following, after describing the processing contents of AD conversion, how to reduce power consumption in this embodiment will be described. First, a case where the output of the comparator 209 is inverted in the region B will be described with reference to FIG. In this embodiment, the number of upper bits in the digital signal after AD conversion is K bits, and the number of lower bits is L bits.

  First, the auto zero operation is performed during the auto zero period PH0 from time t1 to time t2. At time t1, the offset voltage removal and comparator inversion voltage of the comparator 209 are set. Therefore, the comparator 209 sets the memory 403 to a high level. As a result, one terminal is connected between the capacitor 412 connected to the lower bit conversion reference voltage (fine DAC) and the gate of the input transistor 407, and the other terminal is connected to the upper bit conversion reference voltage (course DAC). The turned-on transistor 405 is turned on.

  Further, the auto zero pulse PSET is set to the high level. Thereby, one terminal is connected between the capacitor 415 connected to the column signal line 213 and the gate of the input transistor 408, and the transistor 406 whose other terminal is connected to the output of the comparator 209 is turned on. The reference DAC coarse DAC and fine DAC are in the auto-zero level, the pixel output is in the reset level output to the column signal line 213, the auto-zero pulse PSET is set to low level, and only the transistor 406 is turned off. . By this auto-zero operation, the offset voltage of the comparator 209 is held at the capacitor 412 as a zero level at time t2.

  Next, AD conversion (first analog / digital conversion) related to the upper bits is performed in the upper bit conversion period PH1 at times t3 to t7. At time t3, the count value of the upper bit counter circuit 305 of the up / down counter 211 is reset in order to perform AD conversion of the upper bits. In the upper bit conversion period PH1, the voltage waveform of the upper bit conversion reference voltage (coarse DAC) of the reference voltage RAMP is 2 corresponding to the number of upper bits that starts from a potential higher than the inverted voltage of the comparator 209 and decreases. A staircase waveform having K power levels is generated. The comparator 209 compares the output level of the column signal line 213 with the higher-order bit conversion reference voltage (course DAC). The upper bit counter circuit 305 up-counts the upper bits while the voltage of the upper bit conversion reference voltage (course DAC) is higher than the voltage of the column signal line 213 in the upper bit conversion period PH1.

  Then, as shown at time t5 in FIG. 5, when the voltage of the upper bit conversion reference voltage (course DAC) becomes lower than the voltage of the column signal line 213, the output of the comparator 209 is inverted, and the flip-flop The output of 303 changes from high level to low level. When the output of the flip-flop 303 becomes low level, supply of the clock ADCLK to the upper bit counter circuit 305 via the AND circuit 304 is stopped. Thereby, the counting operation of the upper bits is stopped, and the count value in the upper bit up count performed in the period CNTU is held in the upper bit counter circuit 305 as an AD conversion result for the upper bits. At this time, the output inversion of the comparator 209 is stored in the memory 403 through the buffer 402, and the transistor 405 is turned off. When the transistor 405 is turned off, a potential difference between the lower bit conversion reference voltage (fine DAC) and the upper bit conversion reference voltage (course DAC) is held in the capacitor 412 connected to the input transistor 407.

  When the upper bit AD conversion is completed in the region B, it is necessary to perform the lower bit AD conversion for the reason described later. Therefore, AD conversion (second analog / digital conversion) related to the lower bits is performed in the lower bit conversion period PH2 at times t8 to t10. At time t8, the capacitor 412 already holds the potential difference for the upper bits as an offset. For this reason, the comparator 209 has an offset voltage Vof corresponding to the potential difference between the low-order bit conversion reference voltage (fine DAC) and the high-order bit conversion reference voltage (coarse DAC) held from the first auto-zero inverted potential. Looks like it ’s shifting.

  At time t8, the count value of the lower bit counter circuit 313 of the up / down counter 211 is reset to perform AD conversion of the lower bits. Thereafter, the voltage value of the lower bit conversion reference voltage (fine DAC) is changed stepwise, and the comparator 209 compares the output voltage of the column signal line 213 with the voltage of the lower bit conversion reference voltage (fine DAC). Here, the low-order bit conversion reference voltage (fine DAC) is a full-scale voltage amplitude for one step of the high-order bit conversion reference voltage (course DAC), and the voltage changes stepwise between the counts of the low-order bits. Let The count operation for the lower bits by the lower bit counter circuit 313 performs a down-count starting from the stop value of the upper bit count.

  Then, as shown at time t9 in FIG. 5, when the voltage of the lower bit conversion reference voltage (fine DAC) becomes higher than the voltage of the column signal line 213, the output of the comparator 209 is inverted, and the flip-flop The output of 303 changes from low level to high level. When the output of the flip-flop 303 becomes high level, supply of the clock ADCLK to the lower bit counter circuit 313 via the AND circuit 312 is stopped. As a result, the count operation of the lower bits is stopped, and the count value in the lower bit down count performed in the period CNTD is held in the lower bit counter circuit 313 as an AD conversion result for the lower bits. After time t10, the signal values held in the upper bit counter circuit 305 and the lower bit counter circuit 313 are read out to the memory 212, whereby the AD conversion of the output from the pixels in one row is completed. The value counted by the up / down counter 211 is read out and stored in the memory 212, and then output to the outside from the imaging unit 102 via the row output line 206.

Next, control of power supply to the comparator 209 will be described.
As described above, the voltage of the column signal line 213 and the reference voltage RAMP for comparison with the voltage of the column signal line 213 are input to the comparator 209 in the upper bit conversion period PH1 from time t3 to t7. The comparator 209 compares the voltage of the column signal line 213 with the reference voltage RAMP and outputs a comparison result. Specifically, the comparator 209 outputs a low level when the voltage of the column signal line 213 is higher than the upper bit conversion reference voltage (coarse DAC) of the reference voltage RAMP. On the other hand, the comparator 209 outputs a high level when the voltage of the column signal line 213 is lower than the upper bit conversion reference voltage (coarse DAC) of the reference voltage RAMP.

  At time t4 when the count value of the upper bit counter circuit 305 of the up / down counter 211 exceeds a predetermined lower limit value (exceeding the area A and entering the area B), the signal SLOW output from the upper bit counter circuit 305 is changed from the low level. Transition to high level. When the signal SLOW becomes high level, the output of the OR circuit 314 always becomes high level. Therefore, even if the output of the flip-flop 303 is inverted and becomes low level as the output of the comparator 209 is inverted, the outputs of the OR circuits 308, 310, and 314 are maintained at high level. As a result, the power-down signal SPD output from the power-down control unit 210 does not become low level. Thus, in the period of the region B from the time t4 to the time t6, the power supply to the comparator 209 is not stopped even if AD conversion of the upper bits is completed.

  Next, after the operation for AD conversion of the upper bits is completed at time t7, AD conversion of the lower bits starts at time t8. In the initial state of the comparator 209 at time t8, the voltage of the column signal line 213 is higher than the reference voltage RAMP, and the comparator 209 outputs a low level. From this point, the lower bit counter circuit 313 of the up / down counter 211 performs down-counting until the magnitude relationship between the voltage of the column signal line 213 and the reference voltage RAMP is inverted. At time t9, when the output of the comparator 209 is inverted and becomes high level, the output of the flip-flop 303 becomes high level, and all the inputs to the OR circuit 308 become low level. For this reason, the output of the AND circuit 311 corresponding to the power-down signal SPD output from the power-down control unit 210 becomes a low level, and the power supply to the comparator 209 is stopped.

  The above is the description regarding the control of power supply to the comparator 209. As described above, in the region B, the power consumption can be reduced by stopping the power supply to the comparator 209 immediately after the AD conversion of the lower bits is completed. Also, in the region B, when the AD conversion resolution is J bits, when AD conversion is performed once, voltage comparison of 2 times the J power is necessary, but it is divided into two as in this embodiment. In the AD conversion, the voltage can be obtained by (2 = Kth power) + (2th power L) voltage comparison (J = K + L). Therefore, the time required for AD conversion can be shortened, and power consumption can also be reduced.

  Next, the case where the output of the comparator 209 is inverted in the areas A and C during AD conversion of the upper bits will be described. In this case, since the signal value is determined only by the AD conversion of the upper bits and the power supply to the comparator 209 is stopped by the power-down control unit 210 during the period when the AD conversion unit 203 is not used, the period is Power consumption can be reduced.

  FIG. 6 is a timing chart showing an operation example of the low output region of the AD conversion unit 203 in the present embodiment. With reference to FIG. 6, the case where the output of the comparator 209 is inverted in the range of the region A corresponding to the time t3 to t4 will be described.

  In the region A, the count value of the upper bit counter circuit 305 of the up / down counter 211 is equal to or lower than a predetermined lower limit value (lower than the second threshold value), so that the signal SLOW output from the upper bit counter circuit 305 is low level. is there. As shown at time t4 in FIG. 6, when the voltage of the upper bit conversion reference voltage (coarse DAC) becomes lower than the voltage of the column signal line 213 and the output of the comparator 209 is inverted from high level to low level, the flip-flop 303 Is inverted to low level. At this time, in response to the output inversion of the flip-flop 303, the output of the AND circuit 316 is inverted to the low level, so that all the inputs to the OR circuit 314 become the low level. For this reason, the output of the AND circuit 311 is inverted to a low level, the power-down signal SPD output from the power-down control unit 210 becomes a low level, and the power supply to the comparator 209 is stopped.

  Further, since the AND circuit 311 receives its own output, the output of the AND circuit 311 continues to maintain the low level even if the other three inputs of the AND circuit 311 become the high level. The operation after receiving the output of the power-down control unit 210 has been described with reference to FIG. As described above, when the output of the comparator 209 is inverted in the area A, the power supply to the comparator 209 is stopped during the AD conversion period of the lower bits without performing the AD conversion of the lower bits. Reduction is possible. For example, all lower bits that have not undergone AD conversion may be set to 0.

  FIG. 7 is a timing chart showing an operation example of the high output area of the AD conversion unit 203 in the present embodiment. With reference to FIG. 7, the case where the output of the comparator 209 is inverted in the range of the region C corresponding to the time t6 to t7 will be described.

  In region C, the count value of the upper bit counter circuit 305 of the up / down counter 211 exceeds a predetermined upper limit (greater than the first threshold value), so the signal SUP output from the upper bit counter circuit 305 is high. Is a level. The signal SUP is inverted and input to the OR circuit 310 and is at a low level. As shown at time t6 in FIG. 7, when the voltage of the upper bit conversion reference voltage (coarse DAC) becomes lower than the voltage of the column signal line 213 and the output of the comparator 209 is inverted from high level to low level, the flip-flop 303 Is inverted to low level. At this time, in response to the output inversion of the flip-flop 303, the output of the AND circuit 316 is inverted to the low level, so that all the inputs to the OR circuit 310 become the low level. For this reason, the output of the AND circuit 311 is inverted to a low level, the power-down signal SPD output from the power-down control unit 210 becomes a low level, and the power supply to the comparator 209 is stopped.

  Further, since the AND circuit 311 receives its own output, the output of the AND circuit 311 continues to maintain the low level even if the other three inputs of the AND circuit 311 become the high level. The operation after receiving the output of the power-down control unit 210 has been described with reference to FIG. As described above, when the output of the comparator 209 is inverted in the region C, the power supply to the comparator 209 is stopped during the AD conversion period of the lower bits without performing the AD conversion of the lower bits. Reduction is possible. For example, all lower bits that have not undergone AD conversion may be set to 0.

  Next, the reason why image quality degradation hardly occurs even if the lower bit AD conversion is not performed when the output of the comparator 209 is inverted in the region A and the region C will be described. FIG. 8 is a diagram illustrating an example of a gamma curve according to the present embodiment. In FIG. 8, the signal value width 81 is the upper bit signal accuracy, and the signal value width 82 is the lower bit signal accuracy. When converting the output of the image pickup unit 102 into an image such as JPEG, it is usual to obtain a wide dynamic range with a short bit length using a gamma curve. Here, the area A is an input signal area below the black level. In addition, the region B is a region in which the knee characteristic starts to appear from a region where the JPEG output changes linearly with respect to the input signal. Region C is a region near saturation where the JPEG output hardly changes with changes in the input signal.

  First, the region A will be described. In a CMOS image sensor, variations in the dark current component occur from pixel to pixel, resulting in variations in the black level signal value. Therefore, when the RAW signal is handled, the black level is not set to 0, but is floated about several percent with respect to the dynamic range. For example, 1024 is set to the black level for an output value of 0 to 16385 in the full range. The JPEG output when the input signal is below the black level is blacked out and does not affect the image quality even if the effective bit length is short. For this reason, in the area A, the image quality is not deteriorated even if AD conversion of lower bits is not performed in order to reduce power consumption. In the area B, since the change amount of the JPEG output is large with respect to the change amount of the input signal, if the effective bit length cannot be made long, the image quality is deteriorated. In region C, the JPEG output hardly changes with respect to the amount of change in the input signal. Therefore, even if the effective bit length is short, the image quality is not affected. For this reason, in the area C, the image quality is not deteriorated even if AD conversion of lower bits is not performed in order to suppress power consumption.

  When the upper bit AD conversion result is in region A or region C, the lower bit AD conversion is not completely stopped, but the conversion condition of the lower bit AD conversion is changed to be different from that in region B. Thus, AD conversion of the lower bits may be performed. For example, when the upper bit AD conversion result is in the area A or C, the lower bit conversion reference voltage (fine DAC) is steeped twice or four times to perform AD conversion of the lower bits. Also good. In this case, the power consumption can be reduced by reducing the AD conversion period of the lower bits to 1/2 and 1/4, respectively. If the slope of the reference voltage is changed in this way, the AD conversion result of the lower bits is different from the case where the slope is not changed. However, when the slope is doubled, the bit is shifted by 1 bit to the upper side and quadrupled. In such a case, an equivalent output can be obtained by shifting by 2 bits to the upper side. In this case, for example, 0 may be inserted in the lower bits vacated by the bit shift. The reason why an arbitrary value may be entered is that the output result of the lower bits hardly depends on the JPEG output in the area A and the area C as in the description in FIG.

  Note that when a JPEG output is obtained using a special gamma curve, a method of not performing AD conversion of lower bits only in either the area A or the area C may be used. Also, the lower bit AD conversion is performed by controlling the conversion conditions so that the slope of the lower bit conversion reference voltage (fine DAC) is sharply doubled, quadrupled, etc. in only one of the areas A and C. May be. As described above, whichever method is used, power consumption can be suppressed by performing AD conversion in two steps.

  In the configuration described above, the combination of unit devices and unit modules, which are constituent elements of the system, the scale of the set, and the like can be selected as appropriate based on the actual state of commercialization, and the imaging apparatus according to the present embodiment Includes a wide variety of variations.

  In addition, the AD conversion part in this embodiment mentioned above contains the AD conversion method which performs the following 1st-4th steps. The first step is a step of generating and outputting an upper bit conversion reference voltage for the upper bits of the digital signal to which the analog signal from the pixel is converted. In the second step, the analog signal and the upper bit conversion reference signal are compared by a comparator, and the digital value of the upper bit of the digital signal is calculated from the amount of time until the magnitude relationship between the analog signal and the upper bit conversion reference voltage is switched. This is a step for obtaining. The third step is a step of generating and outputting a lower bit conversion reference voltage for the lower bits of the digital signal. The fourth step is AD conversion of the analog signal based on the digital value of the lower bit of the digital signal obtained from the amount of time until the magnitude relationship is switched by comparing the analog signal with the lower bit conversion reference voltage. This is a step of determining a digital value when the above is performed.

  In addition, the AD conversion unit in this embodiment uses the voltage corresponding to the digital value of the upper bit obtained from the amount of time until the magnitude relationship between the analog signal and the upper bit conversion reference voltage is switched. Including an AD conversion method that the signal is an analog signal. Furthermore, the AD conversion unit in the present embodiment includes an AD conversion method having the following first element and second element. The first element is that the upper bit conversion reference voltage and the lower bit conversion reference voltage are signals whose values change stepwise. The second element is that the lower-bit conversion reference voltage is a signal whose value changes stepwise between lower-bit counts with the full-scale amplitude of the upper-bit conversion reference voltage as a unit step. .

  According to the present embodiment, in the AD conversion unit that performs AD conversion by dividing the output from one pixel into two times, when the result of AD conversion of the upper bits is in a predetermined region such as region A or region C, Stops AD conversion of bits and stops power supply to the comparator. This makes it possible to reduce power consumption without degrading the image quality.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

102: Imaging unit 103: System control unit 104: CPU (Central Processing Unit) 107: DSP (Digital Signal Processor) 201: Pixel array 203: AD conversion unit 208: Pixel 209: Comparator 210: Power-down control unit 211: Up-down Counter 212: Memory 213: Column signal line 301: AD conversion circuit

Claims (10)

A plurality of pixels including photoelectric conversion elements arranged in a matrix;
A column signal line arranged for each column of the plurality of pixels and outputting a signal from the plurality of pixels for each column;
A reference voltage generating means for outputting a reference voltage whose voltage changes with a predetermined slope as time passes;
A signal from the pixel supplied via the column signal line, and an analog / digital conversion unit that compares the reference voltage with the signal to convert the signal into a digital signal;
The analog / digital conversion means includes:
While performing analog-digital conversion of the signal from the pixel divided into upper bits and lower bits,
Whether to perform the second analog-to-digital conversion for analog-to-digital conversion of the lower-order bits is switched according to the result of the first analog-to-digital conversion for analog-to-digital conversion of the upper bits. Image sensor.   2. The image sensor according to claim 1, wherein the second analog-to-digital conversion is not performed when a value of the upper bit obtained by the first analog-to-digital conversion is larger than a first threshold value. .   3. The second analog / digital conversion is not performed when the value of the upper bit obtained by the first analog / digital conversion is equal to or less than a second threshold value. Image sensor. The analog / digital conversion means includes:
Comparing means for comparing a signal from the pixel supplied via the column signal line with the reference voltage;
When the second analog-to-digital conversion is not performed, according to the magnitude relationship between the signal from the pixel and the reference voltage being inverted in the first analog-to-digital conversion, the comparison means is supplied. The image pickup device according to claim 2, wherein the power supply is stopped.   When the second analog-digital conversion is performed, the comparison to the comparison unit is performed in accordance with the magnitude relationship between the signal from the pixel and the reference voltage being inverted in the second analog-digital conversion. The image sensor according to claim 4, wherein power supply is stopped. A plurality of pixels including photoelectric conversion elements arranged in a matrix;
A column signal line arranged for each column of the plurality of pixels and outputting a signal from the plurality of pixels for each column;
A reference voltage generating means for outputting a reference voltage whose voltage changes with a predetermined slope as time passes;
A signal from the pixel supplied via the column signal line, and an analog / digital conversion unit that compares the reference voltage with the signal to convert the signal into a digital signal;
The analog / digital conversion means includes:
While performing analog-digital conversion of the signal from the pixel divided into upper bits and lower bits,
An imaging method for controlling a conversion condition of a second analog / digital conversion for converting the lower bit into an analog-to-digital conversion according to a result of the first analog-to-digital conversion for converting the upper bit into an analog-to-digital conversion element.   When the value of the upper bit obtained by the first analog / digital conversion is larger than a first threshold, the slope of the reference voltage used for the second analog / digital conversion is made larger than the predetermined slope. The imaging device according to claim 6.   When the value of the upper bit obtained by the first analog / digital conversion is equal to or lower than a second threshold value, the slope of the reference voltage used for the second analog / digital conversion is larger than the predetermined slope. The image pickup device according to claim 6, wherein the image pickup device is an image pickup device. The analog / digital conversion means includes:
Comparing means for comparing a signal from the pixel supplied via the column signal line with the reference voltage;
7. The power supply to the comparison unit is stopped in response to the magnitude relationship between the signal from the pixel and the reference voltage being inverted in the second analog / digital conversion. The imaging device according to any one of 8. The image sensor according to any one of claims 1 to 9,
An image pickup apparatus comprising: control means including signal processing means for performing signal processing on an image pickup signal output from the image pickup element.

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