JP2011066773A - Analog-digital conversion circuit and imaging apparatus mounted with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten conversion time while suppressing increase of circuit scale in an A/D conversion circuit of single slope type. <P>SOLUTION: An inclination adjustment circuit 10 receives ramp wave voltage whose voltage level rises or falls with a fixed inclination, and adjusts the inclination of the ramp wave voltage to be output. A comparator CP compares analog voltage which should be converted into a digital value with the ramp wave voltage which is input from the inclination adjustment circuit 10. A digital processing circuit 20 determines the digital value corresponding to the analog voltage according to timing in which output of the comparator CP is reversed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an analog-to-digital conversion circuit that converts an analog voltage output from an imaging element or the like into a digital value, and an imaging apparatus equipped with the analog-to-digital conversion circuit.

  An analog-digital conversion circuit (hereinafter referred to as an A / D conversion circuit as appropriate) is widely used in various fields as a basic element of an LSI. There are various types of A / D conversion circuits, one of which is a single slope type A / D conversion circuit. The single slope type A / D conversion circuit includes a comparator and a storage unit. The comparator compares the input analog voltage with a reference voltage that monotonously increases or monotonously decreases in synchronization with the clock. The storage unit stores information (for example, the number of clocks) when the comparison result is inverted as a digital value corresponding to the input analog voltage.

  Single-slope A / D converters are simple in structure, and can easily compensate for the effects of offsets with subsequent digital circuits. Therefore, CCD (Charge Coupled Devices) sensors, CMOS (Complementary Metal Oxide Semiconductor) image sensors, etc. It is widely used for solid-state imaging devices.

  FIG. 1 is a diagram showing a configuration of a single slope type A / D conversion circuit 500 according to prior art 1. As shown in FIG. FIG. 2 is a diagram illustrating an operation example of the single slope type A / D conversion circuit 500 according to the related art 1. In the single slope type A / D converter circuit 500 according to the prior art 1, the input signal ΔV is input to the inverting input terminal of the comparison circuit (hereinafter, referred to as a comparator as appropriate) CP through the capacitor C. A ramp wave Vrp having the number of step stages corresponding to the resolution is input to the inverting input terminal. The comparator CP sequentially compares the input signal ΔV and the ramp wave Vrp, and inverts the output signal Vout when the magnitude relationship is inverted. Data at the moment when the output signal Vout is inverted is stored in a memory (not shown) in the subsequent stage and digitally processed.

  FIG. 3 is a diagram showing a configuration of a single slope type A / D conversion circuit 600 according to the related art 2. As shown in FIG. FIG. 4 is a diagram for explaining the ramp wave ramp supplied to the single slope type A / D conversion circuit 600 according to the related art 2. The single slope type A / D conversion circuit 600 according to the prior art 2 has a configuration in which a plurality of types of ramp waves can be input to the inverting input terminal of each comparator. Here, the conversion period is divided into two phases, and only one type of ramp wave ramp1 is used in the first phase, but a plurality of types of ramp waves ramp1, 2, 3,... With different initial levels are used in the second phase. Among these, one is selected according to the conversion result in the first phase.

M.F.Snoeij etc. "A CMOS Image Sensor with a Column-Level Multiple-Ramp Single-Slope ADC" 2007 IEEE international Solid-State Circuits Conference p.506-507,618

  In the single slope type A / D conversion circuit according to the above-described prior art 1, the number of steps of the ramp wave increases as the resolution increases, and the conversion time also increases accordingly. For example, a ramp wave having a resolution of 10 bits requires 1024 steps, and a ramp wave having a resolution of 12 bits requires 4096 steps. In this way, when the resolution is increased by 2 bits, the number of step stages is quadrupled and the conversion time is also quadrupled.

  In the single slope type A / D conversion circuit according to the above-described conventional technique 2, the conversion time is shortened by dividing the ramp wave into two stages. For example, by dividing 10 bits (the number of step stages = 1024) into 4 bits (the number of step stages = 16) and 6 bits (the number of step stages = 64), the number of step stages can be reduced from 1024 to 80. However, since it is necessary to generate a plurality of types of ramp waves, the circuit scale tends to increase. In addition, when the variation between the ramp waves is large, there is a possibility that the conversion accuracy may be lowered.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a technique for shortening the conversion time while suppressing an increase in circuit scale in a single slope A / D conversion circuit.

  An analog-digital conversion circuit according to an aspect of the present invention receives a ramp wave voltage whose voltage level rises or falls with a fixed slope, adjusts the slope of the ramp wave voltage, and outputs it, and converts it to a digital value A comparison circuit that compares the analog voltage to be compared with the ramp wave voltage input from the slope adjustment circuit, and a digital processing circuit that determines a digital value corresponding to the analog voltage according to the timing at which the output of the comparison circuit is inverted .

  Another aspect of the present invention is an imaging apparatus. This apparatus includes an image sensor and the above-described analog-digital conversion circuit that converts an analog voltage output from the image sensor into a digital value.

  According to the present invention, it is possible to shorten the conversion time while suppressing an increase in circuit scale in the single slope type A / D conversion circuit.

It is a figure which shows the structure of the single slope type A / D conversion circuit which concerns on the prior art 1. FIG. It is a figure which shows the operation example of the single slope type A / D conversion circuit which concerns on the prior art 1. FIG. It is a figure which shows the structure of the single slope type | mold A / D conversion circuit which concerns on the prior art 2. FIG. It is a figure for demonstrating the ramp wave supplied to the single slope type | mold A / D conversion circuit which concerns on the prior art 2. FIG. It is a figure which shows the structure of the single slope type A / D conversion circuit which concerns on embodiment of this invention. It is a figure which shows the detailed structure of an inclination adjustment circuit. It is a figure which shows five types of ramp waves from which inclination differs. It is a figure which shows an example of the process which converts an analog signal value into a 10-bit digital signal value using five types of ramp waves from which the inclination shown in FIG. 7 differs. It is a figure which shows an example of the process which converts an analog signal value into a 10-bit digital signal value using three types of ramp waves from which inclination differs. It is a figure which shows the modification of the process which converts an analog signal value into a 10-bit digital signal value using five types of ramp waves from which inclination differs. It is a figure which shows the structure of the imaging device carrying the single slope type | mold A / D conversion circuit which concerns on embodiment.

  FIG. 5 is a diagram showing a configuration of the single slope type A / D conversion circuit 100 according to the embodiment of the present invention. The A / D conversion circuit 100 includes a comparator CP, a first capacitor C1, a short-circuit switch SW1, a slope adjustment circuit 10, and a digital processing circuit 20.

  The comparator CP compares the analog voltage to be converted into a digital value and the ramp wave voltage input from the slope adjustment circuit 10 and outputs the comparison result to the digital processing circuit 20. The inverting input terminal of the comparator CP is connected to the first capacitor C1, the non-inverting input terminal of the comparator CP is connected to the slope adjustment circuit 10, and the output terminal of the comparator CP is connected to the digital processing circuit 20. The non-inverting input terminal and output terminal of the comparator CP are connected via a short-circuit switch SW1.

  The first capacitor C1 samples the input analog signal Vin at its input terminal. The output terminal of the first capacitor C1 is connected to the inverting input terminal of the comparator CP. The analog voltage input to the inverting input terminal of the comparator CP may be the voltage of the input analog signal Vin input to the input terminal of the first capacitor C1, or a predetermined reset voltage and the input analog signal. It may be a differential voltage with respect to the voltage of the signal Vin.

  By turning on the short-circuit switch SW1, the comparator CP can be brought into a unity gain buffer state. Thus, before the input analog signal Vin is sampled at the input terminal of the first capacitor C1, the offset voltage of the comparator CP can be stored in the first capacitor C1, and when the comparator CP is amplified (= compared). The offset voltage can be canceled automatically.

  The slope adjustment circuit 10 receives a ramp wave voltage whose voltage level sequentially rises or falls with a fixed slope from a ramp wave generation circuit (not shown), adjusts the slope of the ramp wave voltage, and outputs a non-inverting input terminal of the comparator CP. Output to. The detailed configuration of the inclination adjustment circuit 10 will be described later. As the ramp wave generating circuit, a general circuit configured by counting up or down according to a clock can be used. In the present embodiment, the ramp wave generation circuit has a simple configuration in which the ramp wave slope and step width are fixed.

  The digital processing circuit 20 determines a digital value corresponding to the analog voltage to be converted according to the timing at which the output of the comparator CP is inverted. The digital processing circuit 20 can be configured by any combination of various logic circuits and memories. A processor may be included.

  When the A / D conversion is executed in a single phase, the digital processing circuit 20 stores a digital value corresponding to the ramp voltage at the timing when the output of the comparator CP is inverted in the memory. When A / D conversion is executed in a plurality of phases, a digital value corresponding to the ramp wave voltage at the timing when the output of the comparator CP is inverted in the last phase is stored in the memory.

  When the A / D conversion is executed in a plurality of phases, the digital processing circuit 20 controls the various switches included in the inclination adjustment circuit 10 to thereby adjust the inclination of the ramp wave to be adjusted by the inclination adjustment circuit 10 and the The initial voltage level of the ramp wave in the second and subsequent phases is set. Details of this processing will be described later.

  FIG. 6 is a diagram showing a detailed configuration of the inclination adjustment circuit 10. The inclination adjustment circuit 10 includes a resistance ladder 15 and a second capacitor C2. In the slope adjustment circuit 10, the slope of the ramp wave voltage is adjusted by adjusting the voltage dividing ratio of the plurality of resistors included in the resistor ladder 15.

  Hereinafter, the resistance ladder 15 will be described more specifically. In this embodiment, a voltage addition type R-2R resistor ladder is used. Five 2R resistors (2Ra, 2Rb, 2Rc, 2Rd, 2Re) are connected in parallel to the input terminal receiving the fixed ramp voltage Vrp via five ladder control switches (SW2a, SW2b, SW2c, SW2d, SW2e), respectively. Connected to. Five R resistors (Ra, Rb, Rc, Rd, Re) are connected in series between the inverting input terminal and the ground terminal of the comparator CP.

  The comparator CP side terminal of the 2R resistor (2Ra) is connected to the comparator CP side terminal of the R resistor (Ra), and the comparator CP side terminal of the 2R resistor (2Rb) is connected to the comparator CP side terminal of the R resistor (Rb). The comparator CP side terminal of the 2R resistor (2Rc) is connected to the comparator CP side terminal of the R resistor (Rc), and the comparator CP side terminal of the 2R resistor (2Rd) is connected to the comparator CP side terminal of the R resistor (Rd). The comparator CP side terminal of the 2R resistor (2Re) is connected to the ground side terminal of the R resistor (Rd).

  The resistance value of the 2R resistor is twice the resistance value of the R resistor. Therefore, in this R-2R resistance ladder, the resistance value is 2 / 3R from any connection point on the series circuit composed of four R resistances (Ra, Rb, Rc, Rd). Assuming that the current flowing through these connection points is I, a voltage of I · 2 / 3R = V is generated at each connection point.

  Therefore, when only the first-stage ladder control switch SW2a is turned on, the output voltage of the R-2R resistor ladder becomes V, and when only the second-stage ladder control switch SW2b is turned on, the R-2R resistor When the ladder output voltage is 1 / 2V and only the third-stage ladder control switch SW2c is turned on, the output voltage of the R-2R resistor ladder becomes 1 / 4V, and only the fourth-stage ladder control switch SW2d is turned on. When turned on, the output voltage of the R-2R resistor ladder becomes 1 / 8V, and when only the fifth ladder control switch SW2e is turned on, the output voltage of the R-2R resistor ladder becomes 1 / 16V. .

  When the first and second ladder control switches SW2a and SW2b are turned on, the output voltage of the R-2R resistor ladder is V + 1 / 2V = 3 / 2V, and the first, second and third stages. When the ladder control switches SW2a, SW2b, and SW2c at the stage are turned on, the output voltage of the R-2R resistor ladder is V + 1 / 2V + 1 / 4V = 7 / 4V.

  As described above, by turning on / off the five ladder control switches (SW2a, SW2b, SW2c, SW2d, SW2e), the voltage dividing ratio of the R-2R resistor ladder can be adjusted, and the input ramp wave voltage Vrp Can be adjusted. When one step period of the ramp wave is the same, a ramp wave having a larger step width (ie, lower resolution) is obtained as the slope is increased, and a smaller step width (ie, resolution is obtained as the slope is reduced). Is high).

  The on / off control of the five ladder control switches (SW2a, SW2b, SW2c, SW2d, SW2e) may be executed by a control unit (not shown) or may be executed by the digital processing circuit 20. An example of the former is a case where the resolution needs to be changed at the request of the application. For example, in a digital movie camera, processing such as setting the resolution when shooting a still image higher than the resolution when shooting a moving image and switching the resolution depending on the shooting mode can be considered.

  The second capacitor C2 is an essential configuration when the A / D conversion circuit 100 converts an analog voltage into a digital value in a plurality of phases. Conversely, when the A / D conversion circuit 100 converts an analog voltage into a digital value in a single phase, it is not an essential configuration.

  The second capacitor C2 is connected between the output terminal of the resistance ladder 15 and the inverting input terminal of the comparator CP. By adjusting the level of the reference DC voltage supplied to both terminals of the second capacitor C2, the initial voltage level of the ramp voltage input to the comparator CP is adjusted.

  More specific description will be given below. The input terminal of the second capacitor C2 is configured to be able to apply n (n is a natural number) types of DC voltages (Vdc1, Vdc2,..., Vdcn). Similarly, n types of DC voltages (Vdc1, Vdc2,..., Vdcn) can be applied to the output terminal of the second capacitor C2.

  The n types of DC voltages (Vdc1, Vdc2,..., Vdcn) are DC voltages that cover all initial voltage level candidates of the ramp wave in each phase. For example, when A / D conversion is performed in two phases, it is determined whether the voltage value to be converted exists in the upper half or the lower half of the full range in the first phase, and in the second phase. Consider a configuration in which the existing range is the search range. In this case, two types of DC voltages are required, ie, the lowest reference voltage (for example, ground voltage) in the full range and an intermediate voltage that is half the full range. When the voltage value to be converted exists in the upper half of the full range in the first phase, the DC voltage corresponding to the intermediate voltage is used as the initial voltage level in the second phase. On the other hand, when the voltage value to be converted exists in the lower half in the first phase, the DC voltage corresponding to the lowest reference voltage is used as the initial voltage level in the second phase. Note that the highest reference voltage (for example, power supply voltage) may be used instead of the lowest reference voltage.

  Between each voltage source that generates n types of DC voltages (Vdc1, Vdc2,..., Vdcn) and the input terminal of the second capacitor C2, input side control switches (SW31b, SW32b,...,. SW3nb) are connected to each other. Similarly, output control switches (SW31a, SW32a,...) Are connected between each voltage source for generating n types of DC voltages (Vdc1, Vdc2,..., Vdcn) and the output terminal of the second capacitor C2. .., SW3na) are connected to each other.

  For example, when the DC voltage Vdc1 is determined as the initial voltage, for each step of the ramp voltage Vrp, first, the output side control switch SW31a is turned on and the input side control switch SW31b is turned off, and the voltage of the target step is the second voltage. Stored in the capacitor C2. Next, the output side control switch SW31a is turned off and the input side control switch SW31b is turned on, and the voltage stored in the second capacitor C2 is output to the non-inverting input terminal of the comparator CP. As described above, the start voltage level of the ramp wave voltage can be varied by the configuration in which n types of DC voltages (Vdc1, Vdc2,..., Vdcn) can be applied to both the input terminal and the output terminal of the second capacitor C2. Can be set to any position.

  The on / off control of the output side control switches (SW31a, SW32a,..., SW3na) and the input side control switches (SW31b, SW32b,..., SW3nb) may be executed by a control unit (not shown) or digitally. It may be executed by the processing circuit 20.

  Next, processing when the A / D conversion circuit 100 converts an analog voltage into a digital value in a plurality of phases will be described. Hereinafter, an example of converting an analog voltage into a 10-bit digital value will be described. In order to convert the digital value into a 10-bit digital value by the A / D conversion circuit 500 according to the related art 1 shown in FIG. 1, a ramp wave having 1024 step stages is required. In the following example, it is divided into five phases, the first one bit in the first phase, the next one bit in the second phase, the next one bit in the third phase, the next one bit in the fourth phase , And the lower 6 bits are converted in the fifth phase. A ramp wave having a different slope is used in each phase. That is, five types of ramp waves having different inclinations are used.

  FIG. 7 is a diagram showing five types of ramp waves having different inclinations. In the first phase, a ramp wave having a step width of ½ of the full range is used. In the second phase, a ramp wave having a step width of 1/4 of the full range is used. In the third phase, a ramp wave having a step width of 1/8 of the full range is used. In the fourth phase, a ramp wave having a step width of 1/16 of the full range is used. In the fifth phase, a ramp wave having a step width of 1/1024 of the full range is used. The ramp wave of the fifth phase is drawn with a straight line for convenience. Thus, as the phase progresses, the slope of the ramp wave changes slightly. That is, the search is sequentially switched from the search in the coarser range to the search in the finer range.

  FIG. 8 is a diagram illustrating an example of processing in which an analog signal value is converted into a 10-bit digital signal value using the five types of ramp waves having different inclinations illustrated in FIG. 7. In the first phase, the digital processing circuit 20 determines the initial voltage level of the second phase according to the position within the full range where the output of the comparator CP is inverted. Here, since the output of the comparator CP is inverted in the lower half of the full range, the initial voltage level in the second phase is the lowest reference voltage in the full range.

  The digital processing circuit 20 sets an output side control switch (SW31a, SW32a,..., SW3na) and an input side control switch (SW31b, SW32b,...) In the slope adjustment circuit 10 to set the determined initial voltage range. , SW3nb). In addition, the ladder control switches (SW2a, SW2b, SW2c, SW2d, SW2e) in the inclination adjustment circuit 10 are controlled to switch the slope of the ramp wave to the slope of the second phase.

  In the second phase, the digital processing circuit 20 determines the initial voltage level of the third phase according to the position in the lower half range of the full range where the output of the comparator CP is inverted. Here, since the output of the comparator CP is inverted in the range of the upper half range of the lower half range, the initial voltage level in the third phase is a quarter voltage of the full range. The digital processing circuit 20 controls the inclination adjustment circuit 10 in order to set the determined initial voltage range. Thereafter, by repeating the same processing, the digital value corresponding to the position where the output of the comparator CP is inverted in the fifth phase is set as the final result.

  In the above processing, the number of step stages is 2 in the first phase, the number of step stages is 2 in the second phase, the number of step stages is 2 in the third phase, the number of step stages is 2 in the 4th phase, and the number of step stages is 64 in the 5th phase. This is necessary, and the total number of steps is 72. As described above, in order to convert the analog voltage into a 10-bit digital value, the A / D conversion circuit 500 according to the related art 1 requires 1024 step stages. In the D conversion circuit 500, 72 is sufficient.

  Next, an example in which an analog voltage is converted into a 10-bit digital value in three phases will be described. The upper 2 bits are converted in the first phase, the next 2 bits in the second phase, and the lower 6 bits in the third phase. A ramp wave having a different slope is used in each phase. That is, three types of ramp waves having different inclinations are used.

  FIG. 9 is a diagram illustrating an example of processing for converting an analog signal value into a 10-bit digital signal value using three types of ramp waves having different inclinations. In this example, the number of step stages is 4 in the first phase, the number of step stages is 4 in the second phase, and the number of step stages is 64 in the third phase, and the total number of step stages is 72. In this example as well, 72 steps are sufficient as in the example shown in FIG.

  Thus, the number of phases (that is, the type of ramp wave) and the slope of each ramp wave can be freely changed. That is, it is possible to arbitrarily set how to distribute the number of bits. For example, to convert an analog voltage into a 10-bit digital signal value, it is divided into three phases, the upper 2 bits in the first phase, the next 2 bits in the second phase, and the lower 6 bits in the third phase May be converted respectively. Alternatively, the upper 1 bit may be converted in the first phase, the next 3 bits in the second phase, and the lower 6 bits in the third phase. Further, it may be divided into two stages, and the upper 4 bits may be converted in the first phase and the lower 6 bits may be converted in the second phase.

  Note that the control unit (not shown) or the digital processing circuit 20 may adaptively change the number of phases and the slope of each ramp wave according to a request from the application.

  FIG. 10 is a diagram illustrating a modification of the process of converting an analog signal value into a 10-bit digital signal value using five types of ramp waves having different inclinations. This modification is an example in which the initial voltage level of the ramp wave in the last phase is offset compared to the basic example shown in FIG. In FIG. 10, the starting point (small) in the last phase is the starting point of the basic example shown in FIG. 8, and the starting point (large) in the last phase is the starting point of this modification. That is, the starting point is set at a position shifted from the original starting point (that is, the initial voltage level) in a direction opposite to the direction in which the ramp wave voltage increases or decreases.

  In FIG. 10, the resolution of the ramp wave in the last phase is increased from the original resolution. In the basic example, the original resolution of the ramp wave in the last phase is 6 bits, but in this modification, the resolution is 7 bits. That is, the resolution is increased by 1 bit. In FIG. 10, a rising line with a dotted line indicates a ramp voltage with an increased resolution. Comparing the search voltage range R1 when the resolution is 6 bits and the search voltage range R2 when the resolution is 7 bits, it can be seen that the latter is wider.

  As described above, according to the present embodiment, by using the slope adjustment circuit 10 that can adjust the slope of the ramp wave, an increase in circuit scale is suppressed in the single slope type A / D conversion circuit. However, the conversion time can be shortened. In other words, since only one type of ramp wave is input to the inclination adjustment circuit 10, the configuration of the ramp wave generation circuit can be simplified. In addition, by configuring the slope adjustment circuit 10 with the resistor ladder 15 and the second capacitor C2, an increase in circuit scale due to the slope adjustment circuit 10 can be suppressed.

  Further, by performing A / D conversion in a plurality of phases, the conversion time can be greatly shortened. When A / D conversion is performed by dividing into a plurality of phases, a plurality of types of ramp waves having different inclinations are necessary. In this embodiment, a plurality of types of ramp waves having different inclinations are generated by the inclination adjustment circuit 10. can do. At that time, since a plurality of types of ramp waves having different inclinations are generated by the inclination adjustment circuit 10 based on one fixed type of ramp wave, compared with a case where they are generated separately by different ramp wave generation circuits, Variations between a plurality of types of ramp waves can be reduced. Therefore, a decrease in conversion accuracy can be suppressed.

  In addition, since the slope of the ramp wave can be adjusted by the slope adjustment circuit 10, the number of phases and the resolution of each phase can be flexibly changed.

  Further, by giving an offset to the initial voltage level of the ramp wave in the last phase, the signal at the boundary of the initial voltage level can also be accurately determined. Therefore, even when a determination error occurs in the phase immediately before the last phase, most of the determination error can be detected and corrected. In FIG. 10, the range of the offset was taken only to the intermediate point between the initial voltage level of the ramp wave in the last phase and the adjacent initial voltage level, but the range can be expanded to the adjacent initial voltage level. As a result, more determination errors can be detected.

  Also, the possibility of detecting the determination error can be increased by increasing the resolution of the ramp wave in the last phase. By using both together, the detection possibility of the determination error can be further enhanced.

  FIG. 11 is a diagram illustrating a configuration of an imaging apparatus 700 equipped with the single slope type A / D conversion circuit 100 according to the embodiment. The imaging device 700 may be a digital camera or a camera module mounted on a mobile phone. The imaging device 700 includes an imaging device 50, a CDS circuit 60, a single slope type A / D conversion circuit 100, and a ramp wave generation circuit 70.

  The image sensor 50 can be a CMOS image sensor or a CCD image sensor. The single slope type A / D conversion circuit 100 converts an analog voltage input from the image sensor 50 via the CDS circuit 60 into a digital value. The ramp wave generation circuit 70 generates one type of ramp wave voltage and supplies it to the single slope type A / D conversion circuit 100. According to this configuration, it is possible to construct a small imaging device with a short processing time.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications can be made to combinations of each component and each processing process. Those skilled in the art will appreciate that such modifications are also within the scope of the present invention.

  For example, the resistance ladder 15 included in the inclination adjustment circuit 10 is not limited to the voltage addition type R-2R resistance ladder, but may be a current addition type R-2R resistance ladder, or a plurality of resistors may be connected in series. It may be a connected resistor string.

  100 single slope type A / D conversion circuit, C1 first capacitor, SW1 short-circuit switch, C2 second capacitor, 10 tilt adjustment circuit, 15 resistor ladder, CP comparator, 20 digital processing circuit.

Claims (5)

A slope adjustment circuit that receives a ramp voltage whose voltage level rises or falls with a fixed slope, adjusts the slope of the ramp voltage, and outputs it;
A comparison circuit that compares an analog voltage to be converted into a digital value with a ramp voltage input from the slope adjustment circuit;
A digital processing circuit that determines a digital value corresponding to the analog voltage according to the timing at which the output of the comparison circuit is inverted;
An analog-digital conversion circuit comprising: The tilt adjustment circuit includes a resistance ladder,
The analog-digital conversion circuit according to claim 1, wherein the slope of the ramp wave voltage is adjusted by adjusting a voltage dividing ratio of a plurality of resistors included in the resistor ladder. The inclination adjustment circuit further includes a capacitor,
The capacitor is connected between an output terminal of the resistance ladder and an input terminal of the comparison circuit,
The initial voltage level of the ramp wave voltage input to the comparison circuit is adjusted by adjusting the level of the reference DC voltage supplied to both terminals of the capacitor. Analog-digital conversion circuit. The analog-to-digital conversion circuit divides the analog voltage into a plurality of phases and converts it into the digital value,
4. The analog-digital conversion circuit according to claim 1, wherein the slope adjustment circuit changes the slope of the ramp wave voltage to a smaller one as the phase progresses. 5. An image sensor;
The analog-to-digital conversion circuit according to any one of claims 1 to 4, which converts an analog voltage output from the image sensor into a digital value;
An imaging apparatus comprising:

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