WO2016021413A1

WO2016021413A1 - Solid-state image pickup element and solid-state image pickup device

Info

Publication number: WO2016021413A1
Application number: PCT/JP2015/070925
Authority: WO
Inventors: 直史大西
Original assignee: ソニー株式会社
Priority date: 2014-08-06
Filing date: 2015-07-23
Publication date: 2016-02-11

Abstract

This disclosure relates to a solid-state image pickup element and a solid-state image pickup device which enable unintended data output to be suppressed by the smallest possible circuit change. A counter performs counter output of upper two bits (for example, 13^th bit and 14^th bit) to a logical circuit. The logical circuit performs a logical computation using the counter output from the counter and a control pulse from a sensor controller, and outputs a counter stop signal to a counting operation enable control circuit when the output is one. This disclosure is applicable, for example, to a solid-state image pickup device such as a camera.

Description

Solid-state imaging device and solid-state imaging device

The present disclosure relates to a solid-state imaging device and a solid-state imaging device, and more particularly, to a solid-state imaging device and a solid-state imaging device that can suppress unintended data output with minimal circuit changes.

In the solid-state imaging device, a counter that continues to count during the AD period is provided to convert an analog value, which is a signal from the pixel array unit, into a digital value. The counter data space necessary for this counter is determined by the counter mounting bit, and it is assumed that the counter is used in a range that fits in the data space.

However, depending on the driving method, there are cases where the data space is exceeded, and unintended data (for example, white should be black) is output. This is because the counter counts too much, and the following can be considered as countermeasures.

Measure 1: Limit drive method Measure 2: Install bit shift function Measure 3: Increase the number of bits

Note that Patent Document 1 and the like have been proposed as a technique related to the counter.

JP 2007-316961 A

However, in the case of measure 1, the customer request is not satisfied. In the case of measure 2, the circuit area increases. In the case of measure 3, in addition to an increase in circuit area, current consumption increases. As described above, the demerits are large in any case, and it is difficult to consider measures for these demerits without significant changes.

The present disclosure has been made in view of such a situation, and can suppress unintended data output with a minimum circuit change.

A solid-state imaging device according to an aspect of the present technology performs a logical calculation based on a counter that counts during an AD period and a threshold of the counter data space defined by the output of the upper 2 bits of the counter, and outputs a result. A logic circuit; and a counter stop circuit that outputs a signal for stopping the counter based on a result output from the logic circuit.

A controller that outputs the control pulse to the logic circuit in a predetermined period; the logic circuit performs a logic calculation based on a threshold of the data space of the counter and the control pulse input in the predetermined period; The result can be output.

The logic circuit includes a register for changing the threshold value of the data section of the counter.

A solid-state imaging device according to one aspect of the present technology performs a logical calculation based on a counter that counts during an AD period and a threshold of the counter data space defined by the output of the upper 2 bits of the counter, and outputs the result. A solid-state image sensor comprising a logic circuit and a counter stop circuit that outputs a signal for stopping the counter based on a result output from the logic circuit, and a signal for processing an output signal output from the solid-state image sensor A processing circuit; and an optical system that makes incident light incident on the solid-state imaging device.

In one aspect of the present technology, a logical calculation is performed based on a threshold of the counter data space defined by the output of the upper 2 bits of the counter that counts during the AD period, and the result is output. Based on the output result, a signal for stopping the counter is output.

This technology can suppress unintended data output with minimal circuit changes.

Note that the effects described in the present specification are merely examples, and the effects of the present technology are not limited to the effects described in the present specification, and may have additional effects.

It is a block diagram which shows the schematic structural example of the solid-state imaging device to which this technique is applied. It is a figure explaining the outline of an overflow drive. It is a figure which shows the example of the counter data in D phase count. It is a block diagram which shows the structural example of a counter circuit. It is a figure which shows the structural example of a logic circuit. It is a figure which shows the example of a threshold value. It is a figure which shows the example of a control pulse. It is a block diagram which shows the other example of a structure of a counter circuit. It is a block diagram which shows the structural example of the electronic device to which this technique is applied.

Hereinafter, modes for carrying out the present disclosure (hereinafter referred to as embodiments) will be described.

<Schematic configuration example of solid-state imaging device>
FIG. 1 shows a schematic configuration example of an example of a CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging device applied to each embodiment of the present technology.

As shown in FIG. 1, the solid-state imaging device (image sensor) 1 mainly includes a pixel array unit 11, a low current circuit 12, a comparator (comparator) 13, a counter circuit 14, a DA converter 15, an address decoder 16, It comprises a pixel drive timing drive circuit 17 and a sensor controller 18.

The pixel array unit 11 is configured by regularly and two-dimensionally arranging pixels including a plurality of photoelectric conversion elements, and the photoelectrically converted charges propagate through the vertical signal lines.

The pixel includes a photoelectric conversion element (for example, a photodiode) and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplifying transistor, and can further be constituted by four transistors by adding a selection transistor. Since the equivalent circuit of each pixel 2 (unit pixel) is the same as a general one, detailed description thereof is omitted here.

Also, the pixels can have a pixel sharing structure. The pixel sharing structure includes a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and one other pixel transistor that is shared.

The low current circuit 12 forms a load MOS portion of the source follower circuit. The comparator 13 compares the vertical signal line potential with the potential of the DA converter 15. The counter circuit 14 continues to count during the AD period in order to convert the analog value into a digital value. The DA converter 15 is, for example, a single slope type DA converter for analog-digital conversion of the vertical signal line potential.

The address decoder 16 outputs a control signal for controlling access to the pixel array unit 11 in the vertical direction to the pixel drive timing drive circuit 17. The pixel drive timing drive circuit 17 drives the pixels of the pixel array unit 11 from the logical sum of the control signal from the address decoder 16 and the pixel drive pulse. The sensor controller 18 controls driving of the entire solid-state imaging device 1.

<Description of counter circuit overflow drive>
FIG. 2 is a diagram showing an outline of overflow driving in the counter circuit 14. Normal drive is P phase and D phase once, but as shown in Fig. 2, when driving P phase and D phase twice each, the intended data (white in the example of Fig. 2) is not output There is.

In the example of FIG. 2, an example of driving P phase and D phase twice is shown, and below that, a counter level diagram (data space that the counter circuit 14 can take) is shown. The P phase is driven once (counted), driven twice (counted), and then simultaneously reversed. Next, the D phase is driven (counted), the D phase is driven twice (counted), and then simultaneously reversed. Since it is white before inversion, it should be white data even if it is inverted. However, if the counter circuit 14 is rotated too much, it becomes black as shown in FIG. 2 depending on the position where the counter is stopped. May have.

<Overview of circuit change>
FIG. 3 is a diagram illustrating an example of counter data during D-phase counting. In the counter data during the D-phase count, 7FFFh is the counter value at the timing canceled for the P-phase, and outputs black data. 5FFFh is an approximate boundary between black data and white data, and white data is output when the count is around 5FFFh. However, as described above with reference to FIG. Can end up.

Here, 3FFFh (14-bit MAX) to 1FFFh among 5FFFh and later are areas that you want to stick to white because the counting operation will be strange if black appears during D-phase counting. , Defined as a clip area.

In the lower part of the figure, [hex] and [bin] at the end of the D-phase count and their inversion (that is, counter final data) [bin] are shown. The clip area described above is 3FFFh (100000000000000) to 1FFFh (101111111111111) after inversion, and indicates 4000h (011111111111111) to 5FFFh (010000000000000) before inversion, that is, at the end of the D-phase count.

That is, the clip area is in the range of the 14th bit (most significant) = 0 and the 13th bit = 1 at the end of the D-phase count, and can be determined by the upper 2 bits of the counter circuit 14. Therefore, during the D-phase counting, what kind of output the upper 2 bits are output is set as a threshold value, and when the set threshold value is exceeded, the operation of the counter circuit 14 may be stopped.

In particular, since the second phase of D phase is overcounted, it is possible to stop counting when the threshold is exceeded in this section by applying a control pulse from sensor controller 18 at the second timing of D phase. become. If the threshold value is exceeded in this section, the count is stopped, so that even if it is reversed, the movement is in the white area.

From the above, in this technology, when the count data exceeds 14 bits at the time of CDS (Correlated Double Sampling), that is, at the D phase, that is, the 14th bit (the most significant) = 0, 13 When the bit number = 1, the counter circuit 14 stops counting.

That is, in the present technology, when the count data is 14th bit (most significant) = 0 and 13th bit = 1, a function for stopping the count is provided for each column.

However, since the count data may enter this area even during the P-phase counting, a control pulse and enable (signal generation) function in the D-phase are provided as will be described later.

<Configuration example of counter circuit>
FIG. 4 is a diagram illustrating a configuration example of the counter circuit. This counter circuit is an example of a 15-bit counter.

4, the counter circuit 14 is configured to include a counter 51, a logic circuit 52, and a count operation enable control circuit 53.

The counter 51 performs counting in order to convert an analog value into a digital value. Further, the counter 51 outputs to the logic circuit 52 the counter bit of the bit required as a threshold value, and in the case of the example of FIG. 4, the upper 2 bits (the 13th bit and the 14th bit).

The logic circuit 52 performs logic calculation using the counter output from the counter 51 and the control pulse from the sensor controller 18, and outputs a counter stop signal to the count operation enable control circuit 53 when the output is 1. When receiving a counter stop signal from the logic circuit 52, the count operation enable control circuit 53 stops the count operation of the counter 51.

<Configuration example of logic circuit>
FIG. 5 is a diagram illustrating a configuration example of a logic circuit. When the count shown in FIG. 6 is reached during the D-phase count, that is, 010000000000000h (8192) to 01111111111111h (16383), which are the above clip areas, the counter 51 is stopped. At this time, the output of the 0th to 12th bits from the counter 51 is unquestioned, the output of the 13th bit is 1, and the output of the 14th bit is 0.

The logic circuit 52 includes a NOT gate 71, a NAND gate 72, and an OR gate 73.

The 14th bit output from the counter 51 is input to the NOT gate 71. The 13th bit output (for example, 1) from the counter 51 is input to the NAND gate 72. Further, since it is determined by the count number of the D phase before inversion from the sensor controller 18, a control pulse as shown in FIG. 7 is input to the OR gate 73 only in the last (second) D phase period.

The NOT gate 71 inverts the 14th bit output (for example, 0) from the counter 51 and outputs it to the NAND gate 72.

The NAND gate 72 inputs an inversion of the 14th bit output (for example, 1) and an output of the 13th bit (for example, 1), calculates a logical product, and inverts the result (for example, 1) , And output to the OR gate 73.

The OR gate 73 inputs the inversion (for example, 0) of the calculation result of the NAND gate 72 and the control pulse, calculates a logical sum, and outputs the result to the count operation enable control circuit 53. That is, the control pulse (= 1) as shown in FIG. 7 is input to the OR gate 73 only in the second (last one) D-phase period. At this time, when the calculation result of the NAND gate 72 is inverted (for example, 0) with the threshold (condition) shown in FIG. 6, the output of the OR gate 73 becomes 1, and the counter operation stop signal is sent to the count operation enable control circuit 53. Is output.

Actually, even if the counter stop signal is output due to the influence of the internal delay, the counter 51 does not stop immediately, and thus + α with respect to the expected value. However, it is only necessary to recognize white.

As described above, in the count circuit 14, the upper 2 bits of the logic threshold value are defined, and the count is stopped when the threshold value is exceeded during the last one count period of the D phase. In addition, since only the upper 2 bits of logic are determined by the D-phase count, the operation stops even if the threshold is exceeded during the P-phase period. Therefore, the count is stopped in the period intended by the logic of the upper 2 bits and the control pulse.

As described above, according to the present technology, even when driving beyond the data space, there is no need for significant circuit correction such as bit addition or bit shift, and unintended data output can be suppressed. In addition, since this technology can be handled with minimal circuit changes, it is less affected by increased area and current consumption, and can be easily expanded to future types.

In the above description, an example of driving P phase and D phase twice has been described, but the driving is not limited to P phase and D phase twice. That is, the present technology is also applied to the case of driving three times for the P phase and the D phase, and driving the P phase and the D phase for a plurality of times. Also in these cases, the control pulse is inputted three times for the D phase three times, and every n times for the D phase (n-1) time, that is, the last D phase.

In the above description, since the upper 2 bits are set as the logical threshold value, changing the threshold value involves a circuit change.

<Configuration example of counter circuit>
FIG. 8 is a diagram illustrating another example of the configuration of the counter circuit. This counter circuit is an example of an n-bit counter. In addition, a threshold setting register signal for enabling the threshold to be changed is input from the sensor controller 18 to the counter circuit in the example of FIG.

8 is common to the counter circuit 14 of FIG. 4 in that it includes a count operation enable control circuit 53. The counter circuit 14 of FIG. 8 is different from the counter circuit 14 of FIG. 4 in that the counter 51 is replaced with a counter 101 that is an n-bit counter and the logic circuit 52 is replaced with a logic circuit 102.

The counter 101 performs counting in order to convert an analog value into a digital value. Further, the counter 101 outputs to the logic circuit 102 a counter output of at least two bits among the 0th to (n-1) th bits.

The logic circuit 102 includes a register 111 for changing the threshold value. The register 111 uses the threshold setting register signal from the sensor controller 18 to set a threshold for stopping counting. The logic circuit 102 performs logic calculation based on the counter output from the counter 101 and the threshold set by the register 111, and outputs a counter stop signal to the count operation enable control circuit 53 when the output is 1. When receiving the counter stop signal from the logic circuit 52, the count operation enable control circuit 53 stops the count operation of the counter 101.

Note that the logic circuit 102 is configured according to a threshold set by a threshold setting register signal.

As described above, versatility can be expanded by using a circuit configuration in which the threshold value can be changed by a register.

In the above description, the configuration in which the present technology is applied to the CMOS solid-state imaging device has been described. However, the present technology may be applied to a solid-state imaging device such as a CCD (Charge Coupled Device) solid-state imaging device.

In addition, the present technology can be applied to any back-illuminated type or front-illuminated type CMOS solid-state image sensor as long as it is a CMOS solid-state image sensor.

In addition, the present technology is not limited to application to a solid-state imaging device, but can also be applied to a solid-state imaging device. Here, the solid-state imaging device refers to a camera system such as a digital still camera or a digital video camera, or an electronic device having an imaging function such as a mobile phone. In some cases, a module form mounted on an electronic device, that is, a camera module is a solid-state imaging device.

<Configuration example of electronic equipment>
FIG. 9 is a block diagram illustrating a configuration example of a camera device (solid-state imaging device) as an electronic apparatus to which the present technology is applied.

9 includes an optical unit 601 including a lens group, a solid-state imaging device (imaging device) 602 employing each structure of the present technology, and a DSP circuit 603 that is a camera signal processing circuit. The camera device 600 also includes a frame memory 604, a display unit 605, a recording unit 606, an operation unit 607, and a power supply unit 608. The DSP circuit 603, the frame memory 604, the display unit 605, the recording unit 606, the operation unit 607, and the power supply unit 608 are connected to each other via a bus line 609.

The optical unit 601 takes in incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging device 602. The solid-state imaging device 602 converts the amount of incident light imaged on the imaging surface by the optical unit 601 into an electrical signal for each pixel and outputs the electrical signal as a pixel signal. As the solid-state imaging device 602, the solid-state imaging device 1 according to the above-described embodiment can be used.

The display unit 605 includes, for example, a panel type display device such as a liquid crystal panel or an organic El (Electro Luminescence) panel, and displays a moving image or a still image captured by the solid-state image sensor 602. The recording unit 606 records a moving image or a still image captured by the solid-state imaging device 602 on a recording medium such as a video tape or a DVD (Digital Versatile Disk).

The operation unit 607 issues operation commands for various functions of the camera device 600 under the operation of the user. The power supply unit 608 appropriately supplies various power sources serving as operation power sources for the DSP circuit 603, the frame memory 604, the display unit 605, the recording unit 606, and the operation unit 607 to these supply targets.

Note that the embodiments in the present disclosure are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present disclosure.

Also, in the above, the configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units). Conversely, the configurations described above as a plurality of devices (or processing units) may be combined into a single device (or processing unit). Of course, a configuration other than that described above may be added to the configuration of each device (or each processing unit). Furthermore, if the configuration and operation of the entire system are substantially the same, a part of the configuration of a certain device (or processing unit) may be included in the configuration of another device (or other processing unit). . That is, the present technology is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present technology.

The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, but the disclosure is not limited to such examples. It is obvious that various changes and modifications can be conceived within the scope of the technical idea described in the claims if the person has ordinary knowledge in the technical field to which the present disclosure belongs. Of course, it is understood that it belongs to the technical scope of the present disclosure.

In addition, this technique can also take the following structures.
(1) a counter that counts during the AD period;
A logic circuit that performs a logical calculation based on a threshold of the data space of the counter defined by the output of the upper 2 bits of the counter and outputs a result;
A solid-state imaging device comprising: a counter stop circuit that outputs a signal for stopping the counter based on a result output by the logic circuit.
(2) a controller for outputting the control pulse to the logic circuit during a predetermined period;
The solid-state imaging device according to (1), wherein the logic circuit performs a logical calculation based on a threshold of the data space of the counter and a control pulse input during the predetermined period, and outputs a result.
(3) The solid-state imaging device according to (1) or (2), wherein the logic circuit includes a register for changing a threshold value of a data section of the counter.
(4) a counter that counts during the AD period;
A logic circuit that performs a logical calculation based on a threshold of the data space of the counter defined by the output of the upper 2 bits of the counter and outputs a result;
A solid-state imaging device comprising: a counter stop circuit that outputs a signal for stopping the counter based on a result output by the logic circuit;
A signal processing circuit for processing an output signal output from the solid-state imaging device;
A solid-state imaging device comprising: an optical system that makes incident light incident on the solid-state imaging device.
(5) a controller for outputting the control pulse to the logic circuit during a predetermined period;
The solid-state imaging device according to (4), wherein the logic circuit performs a logical calculation based on a threshold of the data space of the counter and a control pulse input during the predetermined period, and outputs a result.
(6) The solid-state imaging device according to (4) or (5), wherein the logic circuit includes a register for changing a threshold value of a data section of the counter.

1 solid-state imaging device, 11 pixel array section, 14 counter circuit, 18 sensor controller, 51 counter, 52 logic circuit, 53 count operation enable control circuit, 71 NOT gate, 72 NAND gate, 73 OR gate, 101 counter, 102 logic circuit , 111 registers, 600 electronic devices, 601 solid-state imaging device

Claims

A counter that counts during the AD period;
A logic circuit that performs a logical calculation based on a threshold of the data space of the counter defined by the output of the upper 2 bits of the counter and outputs a result;
A solid-state imaging device comprising: a counter stop circuit that outputs a signal for stopping the counter based on a result output by the logic circuit.
A controller that outputs the control pulse to the logic circuit during a predetermined period;
The solid-state imaging device according to claim 1, wherein the logic circuit performs a logic calculation based on a threshold of the data space of the counter and a control pulse input during the predetermined period, and outputs a result.
The solid-state imaging device according to claim 1, wherein the logic circuit includes a register for changing a threshold value of a data section of the counter.
A counter that counts during the AD period;
A logic circuit that performs a logical calculation based on a threshold of the data space of the counter defined by the output of the upper 2 bits of the counter and outputs a result;
A solid-state imaging device comprising: a counter stop circuit that outputs a signal for stopping the counter based on a result output by the logic circuit;
A signal processing circuit for processing an output signal output from the solid-state imaging device;
A solid-state imaging device comprising: an optical system that makes incident light incident on the solid-state imaging device.
A controller that outputs the control pulse to the logic circuit during a predetermined period;
5. The solid-state imaging device according to claim 4, wherein the logic circuit performs a logical calculation based on a threshold of the data space of the counter and a control pulse input during the predetermined period, and outputs a result.
The solid-state imaging device according to claim 4, wherein the logic circuit includes a register for changing a threshold value of a data section of the counter.