JPH01259627A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To attain conversion without causing the complication of structure even in case of enhancing resolution by adding the output of a parallel-type analog/digital converter to the one input of an adder and supplying the contents of a register shifted by (N-1) bits to the other input of the adder. CONSTITUTION:The title converter is equipped with a parallel-type A/D converter 100 whose resolution is 4 bits, an arithmetic means 300 to subtract an analog voltage equivalent to a 1LSB small value from the result of the conversion of the input signal of the parallel-type A/D converter 100 and multiply the value by 2<3>, and a means to add the result of the conversion of the input signal and a result of an conversion with the result of the operation as an input and output it. In this case, as adding means, an adder 210 and a register to write the result of the addition of the adder 210 are provided, the output of the parallel-type A/D converter 100 is added to one input of the adder 210 and the contents of the register 220 are inputted to a position shifted by three bits to the other input of the adder 210. Thus, the resolution can be enhanced and an A/D conversion can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an analog/digital conversion device, and particularly to an analog/digital conversion device that converts an analog voltage into a digital value with high resolution.

[Conventional technology]

Parallel analog with resolution N (N is a positive integer) bits/
A digital (A/D) converter and a parallel A/D converter from the input signal.
It has a calculation means that multiplies the value obtained by subtracting the LSB smaller value from the conversion result of the D converter by 2N-1, and converts the result of converting the input signal and the calculation result again with the parallel A/D converter. Regarding the conversion principle of an A/D converter that adds and outputs
No. 04).

Based on this conversion principle, it is possible to improve the resolution during A/D conversion. The outline is as follows.

That is, in such an A/D converter, the upper bit Do is obtained by parallel A/'D conversion of the first input signal, and then the upper bit Do is calculated from the input signal. The result of subtracting the value smaller than ILSB and multiplying it by 2N-1 is input to a parallel A/D converter, and the lower bit D obtained by performing parallel A/D conversion is added to produce an output code. get. From the input to the second parallel A/D converter, subtract a value I LSB smaller than the second conversion result and multiply it by 2N-1.The result is then further parallelized. By performing conversion using a type A/D converter and adding the results, the resolution of the A/D converter can be increased. By repeating the same process, performing the first parallel A/D conversion, and adding the first N-bit code obtained from each conversion, +MN-(M-1)
) bit output code is obtained. This is because the result of one conversion and the result of conversion of the next lower bit overlap by 1 bit. Therefore, in order to obtain the final output code, a means is required to add the upper bits and lower bits with 1-bit overlap.

Although the above-mentioned earlier application does not specifically mention the addition means, it can be assumed that the addition means has the configuration as shown in FIG. 4 in the conventional general technology.

In FIG. 4, reference numerals A, -A, -2 indicate adders, and in the illustrated case, more than four adders are specifically used as the adders.

In the (M-1)th adder, the previous stage addition result ((M-1
)N-(M-2)) bit code and the M-th conversion result N bits are added with l-bit overlap to obtain an addition result of (MN-(M-1>) bits).

[Problem to be solved by the invention]

However, with such a configuration, there are the following difficulties in increasing the resolution.

In other words, since (M-1) adders are used as the adding means to add the results of the initial N-bit parallel A/D conversion to obtain the final output code, the resolution is If the number of times of processing described above, that is, M, is increased in order to increase the number of times, the number of adders used will also increase in proportion to it.

For example, when M=2, it can be configured with one adder that adds two outputs, but in order to further improve the resolution, M
As we increase , the number of adders required for it also increases, and (
M-1) adders are required.

As described above, in a system based on the idea shown in Fig. 4, as M increases, the number of adders increases, and the size and power consumption of the A/D converter itself increase accordingly. occurs.

An object of the present invention is to provide an analog/digital conversion device that can increase resolution without complicating the configuration.

[Means to solve the problem]

The analog/digital converter of the present invention has a resolution N (N
is a positive integer), and from the input signal to the parallel analog/digital converter, an analog signal corresponding to a value I LSB smaller than the conversion result of the input signal of the parallel analog/digital converter. a calculation means for subtracting the signal and multiplying it by 2N-1; adding the conversion result of the input signal and the result of converting the calculation result of the calculation means as input to the parallel analog/digital converter; An analog/digital converter Wa W comprising an adding means for outputting, the adding means comprising an adder and a register into which the addition result of the adder is written, and the adding means is provided with an adder and a register for writing the addition result of the adder, and the adder is provided with an adder and a register for writing the addition result of the adder. The output of the parallel analog/digital converter is added, and the contents of the register are input to the other input of the adder.
N-1) It is characterized in that it is supplied in a bit-shifted state.

[Effect]

In the present invention, even when the resolution of the adding means is increased, it is sufficient to use the adder once, and the adding means can be configured by providing one adder and one register. Reducing the number of adders used is effective for miniaturization, lower power consumption, and higher integration, and reducing the number of components also helps increase reliability.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the invention. This embodiment includes a parallel A/D converter 100, arithmetic means 300, and addition means 2.
00. The parallel type A/D converter 100 has a resolution of N bits, and the calculation means 300 is a parallel type A/D converter.
Parallel type A/D converter 1 from the input signal of D conversion 25100
This calculation means subtracts an analog voltage corresponding to a value 1 LSB smaller than the conversion result of an input signal of 00, and multiplies the value by 2N-1.

The adding means 200 is means for adding and outputting the result of converting the input signal and the result of converting the result of the operation as input to the parallel A/D converter 100, and the adder 210
and a register 220 into which the addition result of the adder 210 is written.
It is equipped with

The output code of the parallel A/D converter 100 is sent to the adder 210.
is input to one input of The output of register 220 is added to the other input of adder 210. In this case, as will be explained in detail in FIG. 2 later, the other input of the adder 210 is input with the contents of the register 220 shifted to the left by (N-1) bits. Configure it to do so.

The input signal is provided to input signal terminal 1 and the output code is retrieved from register 220.

In FIG. 1, I2 is the input terminal of the parallel A/D converter 100, I3 is the output terminal of the calculation result of the calculation means 300, and St and S2 each represent a switch.

Specifically, the adding means 200 can have the following configuration.

FIG. 2 extracts and shows the adding means 200 in detail, and shows the parallel A/D converter 10 shown in FIG.
This is an example where the resolution of 0 is 4 bits, conversion is performed three times, and the results are added to obtain a result of 3X4-2=10 bits.

As shown in FIG. 2, one input of the adder 210 is the output (4 bits) of the parallel A/D converter 100.

Of the 10 bits output from register 220, the fourth and subsequent bits counting from the MSB are given as the other input to adder 210.

Note that when writing the addition result to the register 220, it is necessary to prevent the other input of the adder 210 from changing. For that purpose - as an example, register 220 may be
A master-slave type circuit as shown in the figure may be used for one bit of the register.

The operation of this embodiment will be described below with reference to FIG. 2.

The first 4-bit conversion result of the parallel A/D converter 100. is input to adder 210. Adder 21 at this time
The other input of 0 is set to zero. To do this, prepare a clock that becomes "0" only when the first conversion result is output, and apply an AND gate with that clock to the adder 210.
It may be provided at the other input of the . As a result, Do is written into the register 220 as is.

Next, when the second conversion result is input, the adder 2
The other input of 10 receives the contents of register 220 at a position shifted 3 bits to the left. in this case,
The lower 3 bits are considered 0.

As a result, the first conversion result is the upper 4 bits, and the 2nd
The result of the second conversion is taken as the lower 4 bits, and with 1 bit overlap, the upper bit and lower bit are added to obtain a 7-bin addition result. The result of this addition becomes the new content DIll of the register 220.

When the third parallel A/D conversion result D2 is input, the register 22 is input in the same way as when Do and Dl are added.
A code obtained by shifting the content DR+ of 0 by 3 bits to the left is input to the other input terminal of the adder 210 and added to D2. The 10-bit result obtained thereby becomes the new contents of the register 220 DR□. DR□ seeks 1
This is a 0 bit output code.

In this way, the analog voltage is converted into a digital value.

In other words, a parallel A/D converter 100 with a resolution of 4 bits.
and 111 from the input signal of the parallel A/D converter 25100.
a calculation means 300 that subtracts an analog voltage corresponding to a value 1 LSB smaller than the conversion result of the input signal of the parallel A/D converter 100 and multiplies that value by 23; Said parallel type Δ/D variation I#!
In the A/D converter, the output of the adder format A/D converter 100 is added as the adding means, and the output of the adder size A/D converter 100 is added to the output of the adder format A/D converter 100. By inputting the contents of the register 220 to the other input of the register 210 at a position shifted by 3 bits to the left, A/D conversion can be performed with increased resolution.

According to the above-described configuration, even when obtaining high resolution, the addition means 200 can be adjusted by simply providing one adder and one register.
Since the configuration can be made simple, the amount of hardware can be significantly reduced compared to the means that can be analogized with the prior art explained in FIG.

Therefore, the A/D converter itself can be made smaller, providing advantages such as lower power consumption and higher integration.

[Effects of the Invention] As described above, according to the present invention, the addition means can be configured with a simple configuration, and the amount of hardware can be significantly reduced. Along with this, the area and power consumption of the A/D converter itself has been reduced,
High integration becomes possible, and reliability can also be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a specific example of the adding means, FIG. 3 is a diagram showing an example of one bit of a register, and FIG. 4 is a diagram based on the conventional technology. It is a figure which shows the example of the addition means which can be inferred. Engineering...Input signal terminal 100...N-bit parallel A/D converter 200...
Adding means 210...Adder 220...Register 300...Calculating unit I2...Input terminal I3 of parallel A/D converter...Output terminal of calculation result Agent Patent Attorney Yoshiyuki Iwasa 1-～---
Input signal terminal I2-...-Input terminal I3- of parallel type A/DIfti device
...-Output terminal of Hama'i result Fig. 1 Fig. 3

Claims (1)

[Claims] (1) Parallel analog/digital converter with resolution N (N is a positive integer) and 1 LSB from the input signal to the parallel analog/digital converter, from the conversion result of the input signal of the parallel analog/digital converter. arithmetic means for subtracting an analog signal corresponding to a small value and multiplying it by 2^N^-^1; An analog/digital conversion device comprising an addition means for adding a converted result as an input and outputting the result, the addition means comprising an adder and a register for writing the addition result of the adder, The output of the parallel analog/digital converter is added to one input of the adder, and the contents of the register shifted by (N-1) bits are supplied to the other input of the adder. Characteristic analog/digital conversion device.