JPH0621820A - Sign magnitude outputting device - Google Patents

Abstract

PURPOSE:To realize the sign magnitude output device outputting a waveform signal with excellent S/N and less cross distortion by means of one system of parallel/serial converter by applying D/A conversion to digital waveform data separately for its positive range and its negative range and mixing analog signals obtained as the result at an analog circuit. CONSTITUTION:A computing element 101 outputs waveform data X as they are when the data are positive and outputs the result of subtraction of a value of a least significant bit digit from a value '1' when the data are negative. A parallel serial converter 102 converts parallel waveform data comprising other bits than a most significant bit of parallel waveform data PDT outputted from the computing element 101 into serial waveform data. Then a data converter 103 applies logic arithmetic operation to the serial waveform data to generate outputs 1, 2 for 1st and 2nd D/A converters.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention divides digital waveform data into a positive range and a negative range and performs D / A conversion separately,
The present invention relates to a sine magnitude output device that outputs a waveform signal with excellent cross distortion and S / N by mixing the resulting analog signal in an analog circuit.

[0002]

2. Description of the Related Art When outputting digital waveform data as an analog waveform signal, such as in the case of producing digital musical tone waveform data as a musical tone signal in an electronic musical instrument, the number of quantization bits in D / A conversion is, for example, 16 If you want to increase from 17 bits to 17 bits, D of 17 bits
The use of two 16-bit D / A converters makes it possible to construct the entire apparatus at a lower cost than the use of one A / A converter.

As described above, as a method of outputting digital waveform data using two D / A converters, a method called a sine magnitude output method is known.
This method can reduce cross distortion in an analog waveform signal and improve S / N.

The basic configuration of the sine magnitude output device will be described with reference to FIG. In FIG. 8, waveform data, which is digital parallel data, is first input to the sine magnitude arithmetic circuit 801. here,
Parallel waveform data is divided into positive side and negative side,
The sine magnitude calculation described later is performed on each range. The waveform data on the positive side and the waveform on the negative side that have been subjected to the sine magnitude calculation are converted into output 1 and output 2 which are serial data, respectively, and are output to D / A converters (DAC) 802 and 803, respectively.

D / A converters (DAC) 802, 803
Converts each of the above outputs into an analog signal and outputs the analog signal to the operational amplifier 804 via the variable resistors R1 and R3. The operational amplifier 804 subtracts the output voltage value of the resistor R3 (corresponding to the output 2) from the output voltage value of the resistor R1 (corresponding to the output 1) and outputs a waveform signal. Here, the zero point of the output of the operational amplifier 804 is determined by the amplification factor of the operational amplifier 804 and the resistors R1, R2, R3, and R4. Therefore, when the amplitude value of the input waveform data is “0”, the output of the operational amplifier 804 becomes “0”.
The resistance value of the variable resistor R1 is adjusted.

Next, the operation principle of the sine magnitude output device of FIG. 8 will be described with reference to the waveform diagram of FIG.
First, in the N + 1-bit (for example, 17-bit) data expressing the value on the positive side of the input waveform from 0 to (+ MAX) (A in FIG. 9 (a)), the lower order except the MSB sign bit The N bits include a sign bit representing a value in the range from the minimum value (-MAX) to the maximum value (+ MAX) shown by A'in FIG. 9B in the sign magnitude arithmetic circuit 801 in FIG. Bits (eg 16 bits)
Is converted into data and output as output 1. At the same time, as output 2, N-bit data including a code bit representing the minimum value (-MAX) shown in C of FIG. 9C is output.

On the other hand, the sign bit of the MSB of N + 1 bits (for example, 17 bits) of data representing the value in the negative range (B in FIG. 9A) from 0 to (-MAX) of the input waveform. The lower N bits except for include a sign bit expressing a value in the range of the minimum value (-MAX) to (+ MAX) shown by B'in FIG. 9 (c) in the sine magnitude arithmetic circuit 801 of FIG. N bits (eg 16 bits)
Data and output as output 2. In this case, the conversion is performed so that the unevenness of the waveform is reversed. At the same time, as output 1, N-bit data including a code bit representing the minimum value (-MAX) shown by D in FIG. 9B is output.

Output 1 and output 2, which are N-bit data including the above-mentioned sign bit, are respectively D / A converters 802.
And 803 D / A converted. Then, as described above, in the operational amplifier 804, the analog signal corresponding to the output 2 of FIG. 9 (c) is subtracted from the analog signal corresponding to the output 1 of FIG. 9 (b) to obtain the output shown in FIG. 9 (d). The waveform is obtained. The S / N of this output waveform is the same as the S / N when the original N + 1-bit input waveform is D / A converted as it is.

As described above, the value in the negative side range and the value in the positive side range of the waveform data are separately converted into analog signals by the N-bit D / A converter and then combined by the analog circuit. By doing so, the entire apparatus can be made cheaper in comparison with the case where the value in the range on the negative side of the waveform data to the value in the positive side is converted into analog data by one N + 1-bit D / A converter. Can be configured.

Further, in the above sine magnitude output method, the zero point of the input waveform does not correspond to the zero point in the D / A converter, so that the occurrence of cross distortion in the D / A converter can be suppressed.

FIG. 10 is a basic configuration diagram of a conventional example of the sine magnitude arithmetic circuit 801 in the sine magnitude output device of FIG. The calculator 1001 determines whether the waveform data is positive or negative, and for each range of the positive side range and the negative side range, the above-mentioned FIG. 9 (a) → (b) or FIG.
The conversion operation shown in (a) → (c) is performed, and each conversion result is output to the positive side parallel-serial converter 1002 and the negative side parallel-serial converter 1003.

The positive-side parallel-serial converter 1002 and the negative-side parallel-serial converter 1003 respectively convert the conversion output, which is parallel data, into serial data, and each D / D in FIG.
It outputs to the A converters 802 and 803.

[0013]

However, the above-mentioned FIG.
In the conventional example related to the sine magnitude arithmetic circuit 801 of FIG.
Since a serial converter is required, the scale of the circuit becomes large, which causes a problem of cost increase.

An object of the present invention is to enable the sine magnitude calculation to be executed by one system of parallel-serial converter.

[0015]

The first aspect of the present invention is as follows.
It has the following configuration. First, regarding input parallel waveform data such as tone waveform data consisting of a predetermined number of bits,
If the input parallel waveform data has a positive sign, it is output as it is, and if the input parallel waveform data has a negative sign, the value “1” is subtracted from the digit of the least significant bit, and It has a calculation means for outputting the subtraction result. This means is realized by a general-purpose processor or a dedicated hardware circuit.

Next, a parallel / parallel converter for converting parallel waveform data composed of bits other than the most significant bit of the parallel waveform data output from the arithmetic means into serial waveform data.
It has a serial conversion means. This means is, for example, a parallel input / serial output type shift register.

Further, when the input parallel waveform data has a positive sign, of each bit of the serial waveform data output from the parallel / serial conversion means, it is one bit lower than the most significant bit of the input parallel waveform data. For the bit corresponding to the bit, the value is inverted and the first
Output serial waveform data, and the bits other than that bit are sequentially output as they are as the first output serial waveform data. When the input parallel waveform data has a negative sign, it is output as the first output serial waveform data. A first output means for sequentially outputting each bit in which the bit corresponding to the bit one bit lower than the most significant bit of the input parallel waveform data has the value "1" and the other bits have the value "0" Have. This means uses, for example, a logic circuit that operates based on the value of the most significant bit indicating the sign of the input parallel waveform data and the timing signal indicating each bit position of the serial waveform data output from the parallel / serial conversion means. Will be realized.

In contrast to this, when the input parallel waveform data has a negative sign, all the bits of the serial waveform data output from the parallel / serial conversion means are sequentially inverted, and then the inverted serial waveform data is inverted. For each bit corresponding to the bit one bit lower than the most significant bit of the input parallel waveform data, the value is inverted and output as the second output serial waveform data, and the other bits are left as they are. When the input parallel waveform data is sequentially output as the second output serial waveform data and the input parallel waveform data has a positive sign, the second output serial waveform data corresponds to a bit one bit lower than the most significant bit of the input parallel waveform data. The bits that have the value "1" and the other bits have the value "0" are sequentially output. That a second output means. This means is realized by, for example, a logic circuit similar to the first output means.

Further, it has a first digital / analog converting means for converting the first output serial waveform data into a first analog waveform signal. Paired with this, a second output serial waveform data is converted into a second analog waveform signal by a second
It has digital / analog conversion means.

Then, from the first analog waveform signal to the second
Of analog waveform signals and outputs the result of the subtraction as an output analog waveform signal. This means is realized, for example, by an operational amplifier.

Next, the second aspect of the present invention has the following configuration. First, for input parallel waveform data such as tone waveform data consisting of a predetermined number of bits, if the input parallel waveform data has a positive sign, it is output as it is, and the input parallel waveform data has a negative sign. In some cases, it has a calculating means for inverting the sign of the negative input parallel waveform data and calculating and outputting parallel waveform data having a positive sign having the same amplitude as that.
This means is realized by a general-purpose processor or a dedicated hardware circuit.

Next, the parallel / parallel data for converting the parallel waveform data composed of bits other than the most significant bit of the parallel waveform data output from the arithmetic means into serial waveform data.
It has a serial conversion means.

Of the bits of the serial waveform data output from the parallel / serial conversion means, the bit corresponding to the bit one bit lower than the most significant bit of the input parallel waveform data is inverted and output. However, it has a logical operation means for sequentially outputting the bits other than that bit as they are.

Further, when the input parallel waveform data has a positive sign, each bit of the serial waveform data output from the logical operation means is sequentially output as the first output serial waveform data, and the input parallel waveform data becomes When it has a negative sign, the bit corresponding to the bit one bit lower than the most significant bit of the input parallel waveform data as the first output serial waveform data is the value "1" and the other bits are the values. It has a first output means for sequentially outputting each bit which is "0".

On the other hand, when the input parallel waveform data has a positive sign, it is 1 from the most significant bit of the input parallel waveform data as the second output serial waveform data.
When the bits corresponding to the lower bits of the bits have the value “1” and the bits other than the bits have the value “0” are sequentially output, and the input parallel waveform data has a negative sign, Second output means for sequentially outputting each bit of the serial waveform data output from the logical operation means as the second output serial waveform data.

Then, a first similar to the first aspect of the present invention
And a second digital / analog converting means and an analog waveform calculating means.

[0027]

In the sine magnitude operation, when the input parallel waveform data has a negative sign, the sign of the negative input parallel waveform data is inverted and the parallel waveform data having a positive sign having the same amplitude as that is calculated. However, in the first aspect of the present invention, the value “1” is subtracted from the digit of the least significant bit of the negative input parallel waveform data which is a part of the above-described operation, and the subtraction result is output. By performing the operation before the parallel / serial conversion processing, and in the second aspect of the present invention, by performing all the above-described operations before the parallel / serial conversion processing, The number of parallel / serial conversion means required in the configuration can be reduced to one.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. <Structure of Embodiment> First, the basic structure of the sine magnitude output device is the same as that of FIG. 8 described above, and the operating principle thereof is also the same as that of FIG. 9 described above.

Next, FIG. 1 is a block diagram of an embodiment of the sine magnitude arithmetic circuit 801 of FIG. 8 according to the present invention. In FIG. 1, first, in the waveform data X input as parallel digital data, the arithmetic unit 101 determines whether the amplitude of the waveform is positive or negative. For the waveform data X whose amplitude is determined to be negative, the value “1” is subtracted at the digit of the least significant bit of the data for the reason described later.

Next, the parallel data PDT obtained as a result of processing the waveform data X by the arithmetic unit 101 is a parallel-serial converter (hereinafter referred to as a parallel-serial converter) 10
It is converted into serial data at 2 and further data converter 1
Data conversion is performed by 03 as described later. As a result, the outputs 1 and 2 shown in FIGS. 9B and 9C are output to the D / A converters 802 and 803 of FIG. 8, respectively.

FIG. 2 is a circuit configuration diagram of the parts of the parallel-serial converter 102 and the data converter 103 of FIG. 1, and the parts other than the parallel-serial converter 102 are the data converter 103 of FIG.
Corresponding to. The arithmetic unit 101 of FIG. 1 includes a parallel-serial converter 102 of FIG. 2 and a D flip-flop (DFF) 2
Although it is provided before 01, it is not shown in the figure because it is realized by a general-purpose microprocessor.

First, the waveform data X is the arithmetic unit 101 of FIG.
M of parallel data PDT output as a result of being processed by
SB (most significant bit) is taken into the DFF 201. On the other hand, the parallel data PDT (MSB-
1) The data consisting of N bits from the 1st bit onward is converted into serial data by the parallel-serial converter 102 and sequentially output as the output Y.

The output of the DFF 201 is the NOR circuit (NO
R) 203 and the inverter 205, and the serial data output Y from the parallel-serial converter 102 is input to the inverter 202 and the NOR 206.

The output Z of the NOR 203 is input to the exclusive OR circuit (EOR) 204, and the output W of the NOR 206 is
Input to EOR207. From the signal generation circuit (not shown) in the sine magnitude calculation circuit 801, D
The clock MSBCK is input to the FF 201, the control signal LDB and the clock PSCK are input to the parallel-serial converter 102, and the control signal MSBINV is input to the EORs 204 and 207. <Operation of the Embodiment> The operation of the embodiment of the present invention having the configuration of FIGS. 1 and 2 described above will be described with reference to the operation flowchart of FIG. The operation flowchart of FIG. 3 is realized as an operation executed by each part of FIGS. 1 and 2.

First, one sample of the waveform data X (N +
1 bit) is input to the arithmetic unit 101 in the sine magnitude arithmetic circuit 801 (step S301). Next, in the arithmetic unit 101, whether the sign of the waveform data X is positive or negative is determined by the sign of the MSB (most significant bit) (step S302).

If the sign of the waveform data X is positive (MSB = 0) as a result of the determination in step S302, the calculator 10
1 outputs the waveform data X as it is as parallel data PDT.

When the sign of the waveform data X is negative (MSB = 1) as a result of the determination in step S302, the calculator 10
1 subtracts the value "1" at the digit of the least significant bit of the waveform data X, and outputs the subtraction result as parallel data PDT (step S303). Next, parallel data PD
The MSB of T is a clock MS that indicates the output timing of the MSB, as shown in the operation timing chart of FIG.
At the rising timing of BCK, it is separated from other bits and taken into the DFF 201 (step S30).
4). Therefore, the DFF 201 outputs "0" when the MSB is positive and outputs "1" when the MSB is negative. According to the output value of the DFF 201, the (MSB-1) th bit or less (MSB-) of the parallel data PDT
1), (MSB-2), ..., (MSB-N), which will be described later, are executed to control the data conversion operation performed on the N-bit data.

On the other hand, the above-mentioned (M
SB-1) The data consisting of N bits below the 1st bit is
The parallel-serial converter 102 converts the serial data into serial data (step S305). That is, the parallel-serial converter 102
As shown in the operation timing chart of FIG.
The clock P within the period when the control signal LDB is at the low level
Parallel data PD at the rising edge of SCK
N bits below the (MSB-1) th bit of T are taken in at the same time, and at each rising timing of the clock PSCK within the period when the control signal LDB is at a high level thereafter, each bit of the above taken data is serially output as serial data. Output as Y.

The above-mentioned number of bits N is the same as D / A in FIG.
It is equal to the number of conversion bits in the converters 802 and 803. In this way, from the parallel-serial converter 102, not the MSB bit or less of the parallel data PDT, but (MSB-1)
The data below the first bit is output as serial data.

Next, the data output Y of the parallel-serial converter 102 is a DF indicating the sign of the MSB of the parallel data PDT.
Depending on the output of F201 and the value of the control signal MSBINV,
As described below, the outputs Z and W of the NOR circuits 203 and 206 and the outputs 1 and 2 of the EXORs 204 and 207 are converted. Here, FIG. 5 is a truth table showing the state of each signal at that time. Operation when the sign of the waveform data X is positive First, for the waveform data X with a positive sign, as shown by the processing route of steps S302 → S304 of FIG. 3, the arithmetic unit 101 of FIG. Is not processed and is output as it is from the arithmetic unit 101 as parallel data PDT, and then the process corresponding to step S306 in FIG. 3 is performed.

When the sign of the parallel data PDT is positive, the output of the DFF 201 becomes "0". In this case, NO
R203 functions as an inverter. Therefore, the inverter 202 and the NOR 203 form the parallel-serial converter 10
The output Z of the NOR 203 becomes the same as the output Y as shown in FIGS. 5 (a) to 5 (d).

The parallel data PDT (MSB
-1) At the timing when the serial data Y corresponding to the 1st bit is output, as described above, the control signal MSB
Since INV becomes “1” (see FIG. 3), EOR204
Functions as an inverter. Therefore, at the timing when the serial data Y corresponding to the (MSB-1) th bit of the parallel data PDX having a positive sign is output, the circuit portion including the inverter 202, the NOR 203, and the EOR 204 functions as an inverter as a whole, As the output 1, as shown in FIGS. 5A and 5B, the signal in which the (MSB-1) th bit is inverted is output.

Further, the parallel data PDT (MSB-
2) Serial data Y corresponding to the bits below the 1st bit
At the timing when is output, the control signal MSBINV becomes "0" as described above (see FIG. 3).
The OR 204 is a circuit that simply passes a signal. Therefore, the parallel data PDX (MSB-
2) Serial data Y corresponding to the bits below the 1st bit
Is output at the timing when the inverter 202, NO
The circuit portion composed of R203 and EOR204 is a circuit that simply allows a signal to pass, and as an output 1,
As shown in FIGS. 5 (c) and 5 (d), the above (MSB-2)
Each bit from the bit onward is output as it is.

On the other hand, when the sign of the parallel data PDT is positive and the output of the DFF 201 is "0", the inverter 2
The output of 05 becomes "1", and the output W of NOR 206 is
As shown in FIGS. 5 (a) to 5 (d), it is always "0".

Therefore, the parallel data PDT (MSB
-1) At the timing when the serial data Y corresponding to the 1st bit is output and the control signal MSBINV becomes “1”,
The output 2 from the EOR 207 becomes "1" as shown in FIGS. 5 (a) and 5 (b).

In addition, the parallel data PDT (MSB-
2) Serial data Y corresponding to the bits below the 1st bit
Is output and the control signal MSBINV becomes “0”, the output 2 from the EOR 207 is as shown in FIGS.
As shown in FIG.

The above operation is summarized as follows. Now, the waveform data X is, as shown in FIG.
It is assumed that a value in the range of (−MAX) ≦ X <(+ MAX) can be taken, and each value is represented by N + 1 bits (for example, 17 bits) including the sign bit of MSB.

The sign of the waveform data X is positive and its M
When SB is “0”, the waveform data X is as shown in FIG.
As shown in A of (a), the value can be in the range of 0 ≦ X <(+ MAX). When the (MSB-1) th bit changes from "0" to "1", the range of the value of the waveform data X is from (less than + MAX / 2) to (+ MAX / 2 or more).
Changes to.

Therefore, after the MSB has been separated, (MS
When the (B-1) th bit is "0", it is inverted to "1" to be a sign bit, and each bit from the (MSB-2) th bit and thereafter is output as it is. Of the N + 1-bit data expressing the value of X in the range of 0 ≦ X <(+ MAX / 2), the lower N bits excluding the sign bit of the MSB have a value in the range of (−MAX) ≦ X <0. N bits (for example, 16 bits) including the sign bit to be expressed
Bit) data.

Similarly, after the MSB has been separated, (MS
When the (B-1) th bit is "1", it is inverted to "0" to be a sign bit, and each bit from the (MSB-2) th bit and thereafter is output as it is. Of the N + 1-bit data representing the value of X in the range of (+ MAX / 2) ≦ X <(+ MAX), the lower N bits excluding the sign bit of the MSB are 0 ≦ X <(+ MA
X) is converted into N-bit data including a sign bit expressing a value in the range.

As described above, the lower N bits excluding the sign bit of the MSB in the N + 1-bit data expressing the positive range (A in FIG. 9 (a)) of the waveform data X are:
The data is converted into N-bit data including a code bit that represents the value in the range indicated by A'in FIG. In this case, of the N + 1-bit data of the waveform data X, the information represented by the lower N bits excluding the MSB code bit is stored as it is as the information represented by the N bits including the code bit representing the output 1. The information represented by the sign bit of the MSB is stored as the information for selecting the output 1. Therefore, in the above conversion operation, the information amount of the original waveform data X is not lost.

Along with the above conversion operation, the output 2 is
The (MSB-1) th bit is the code bit "1",
Since the bits from the (MSB-2) th bit onward are output as "0", the minimum value (-MAX) is output as N-bit data including the sign bit (FIG. 9 (c)).
C). Operation when the sign of the waveform data X is negative Next, for the waveform data X with a negative sign, as shown as the processing route of steps S302 → S303 → S304 of FIG. At 101, the value “1” is subtracted at the least significant bit of the waveform data X,
The subtraction result is output as parallel data PDT.

When the sign of the parallel data PDT is negative, the output of the DFF 201 becomes "1". In this case, NO
The R206 functions as an inverter, and the output W of the NOR206 becomes an inverted version of the serial data output Y from the parallel-serial converter 102 as shown in FIGS. 5 (e) to (f) (step S307).

The subtraction operation in the arithmetic unit 101 and N
The operation of inverting all the bits in the OR 206 realizes the operation of converting the value of the waveform data X whose sign is negative into a positive value whose absolute value is equal to that.

After the above operation, step S308 in FIG.
The process corresponding to is performed. First, parallel data PD
At the timing at which the serial data Y corresponding to the (MSB-1) th bit of T is output, the control signal MSBINV becomes "1" as described above (see FIG. 3).
The OR 207 functions as an inverter. Therefore, at the timing when the serial data Y corresponding to the (MSB-1) th bit of the parallel data PDX having a negative sign is output, as the output 2, as shown in FIGS. 5 (a) and 5 (b), Output W of NOR 206 corresponding to serial data Y
Is further inverted and the signal is output.

Further, the parallel data PDT (MSB-
2) Serial data Y corresponding to the bits below the 1st bit
At the timing when is output, the control signal MSBINV becomes "0" as described above (see FIG. 3).
The OR 207 is a circuit that simply passes the signal. Therefore, the parallel data PDX with a negative sign (MSB-
2) Serial data Y corresponding to the bits below the 1st bit
At the timing when is output, the output 2 is shown in FIG.
As shown in (h), the output W of the NOR 206 is output as it is. On the other hand, when the sign of the parallel data PDT is negative and the output of the DFF 201 is “1”, the NOR 20
The output Z of 3 is always "0" as shown in FIGS. 5 (e) to 5 (h).

Therefore, the parallel data PDT (MSB
-1) At the timing when the serial data Y corresponding to the 1st bit is output and the control signal MSBINV becomes “1”,
The output 1 from the EOR 204 becomes "1" as shown in FIGS. 5 (e) and 5 (f).

In addition, the parallel data PDT (MSB-
2) Serial data Y corresponding to the bits below the 1st bit
Is output and the control signal MSBINV becomes “0”, the output 1 from the EOR 204 is as shown in FIGS.
As shown in FIG.

The above operation is summarized as follows. Now, the waveform data X is, as shown in FIG.
It is assumed that a value in the range of (−MAX) ≦ X <(+ MAX) can be taken, and each value is represented by N + 1 bits (for example, 17 bits) including the sign bit of MSB.

The sign of the waveform data X is negative and its M
When SB is “1”, the waveform data X is as shown in FIG.
As shown in B of (a), a value in the range of (−MAX) ≦ X <0 can be taken.

The (MSB-1) th bit is "1".
When changing from "0" to "0", the original data value is (-MAX
From> / 2) to (-MAX / 2 or less). Therefore, after being decremented by the arithmetic unit 101 to separate the MSB and all the bits below the (MSB-1) th bit are inverted, the (MSB-1) th bit of the original waveform data X is "0". In the case of, the above-mentioned inverted (MSB-
1) The 1st bit "1" is further inverted to "0" to be a sign bit, and the above-mentioned inverted (MSB-2) th bit and the following bits are output as they are. Of the N + 1-bit data representing the value in the range of 0>X> (-MAX / 2), the lower N bits excluding the sign bit of the MSB are (-MAX) <X <while the unevenness of the waveform is inverted. It is converted into N-bit (for example, 16-bit) data including a sign bit that represents a value in the range of 0.

Similarly, -1 is subtracted by the arithmetic unit 101,
After the MSB is separated and all bits from the (MSB-1) th bit onward are inverted, (M
When the (SB-1) th bit is "1", the above-mentioned inverted "MSB-1" th bit "0" is further inverted to "1" to be a sign bit, and the above-mentioned inverted (MSB
-2) Each bit from the bit onward is output as it is, so that (-MAX / 2) ≧ X ≧ (− of the waveform data X.
The lower N bits excluding the sign bit of the MSB of the N + 1 bit data representing the value in the range of (MAX) are the codes expressing the value in the range of 0 ≦ X ≦ (+ MAX) while the unevenness of the waveform is inverted. Converted to N-bit data including bits.

As described above, the lower N bits excluding the sign bit of the MSB of the N + 1 bit data representing the value on the negative side of the waveform data X (B in FIG. 9A) are:
While the unevenness of the waveform is inverted, it is converted into N-bit data including the sign bit expressing the value in the range shown by B'in FIG. 9 (c) and output as the output 2. Also in this case, as in the case of the processing on the positive side of the waveform data X, the information represented by the lower N bits of the N + 1 bit data of the waveform data X excluding the MSB code bit is the code representing the output 2. The information represented by the N bits including the bits is stored as it is, and the information represented by the MSB code bit is stored as the information for selecting the output 2. Therefore, in the above conversion operation, the information amount of the original waveform data X is not lost.

With the above conversion operation, the output 1 is
The (MSB-1) th bit is the code bit "1",
Each bit from the (MSB-2) th bit onward is output as "0", so that the minimum value (-MAX) is output as N-bit data including the sign bit (FIG. 9 (b)).
D). Specific Example FIG. 6 is a diagram showing an example of the waveform data X before data conversion by the sine magnitude arithmetic circuit 801 and the output 1 or output 2 after conversion as described above. In this example, for simplicity of explanation, the number of bits N + 1 of the waveform data X before conversion is 6 bits, and the number of bits N of the output 1 or output 2 after conversion is 5 bits.

For example, when the value of the waveform data X is +5 (decimal display), the binary display is "0101.0".
0 "and MSB is" 0 ". This waveform data X
Is output from the arithmetic unit 101 as it is as parallel data PDT.

Incidentally, "." Indicates the boundary between the integer part and the decimal part, but the position of the decimal point is for convenience depending on the characteristics of the D / A converter. In this case, the parallel-to-serial converter 102 of FIG.
Data "1" excluding "0" of MSB out of "1.00"
01.00 "is output. Therefore, the parallel-serial converter 1
From 02, the serial data output Y is "1",
"0", "1", "0", and "0" are sequentially output.

When the data of the output 1 is obtained according to the truth table of FIG. 5, the first "1" corresponding to the (MSB-1) th bit of the waveform data X among the data "101.00" of the output Y is obtained. "" Is inverted to "0" based on "1" of the control signal MSBINV and output as output 1. In addition, the data string “01.00” of the (MSB−2) th bit or less of the waveform data X is “0” of the control signal MSBINV.
Based on the above, it is output as the output 1 without change from "01.00". As a result, the value of the waveform data X + 5.0 (“010
1.00 ”) is the value of output 1 +2 (“ 0010.0 ”)
Is converted to. The position of the decimal point is determined according to the D / A converter 802 (see FIG. 8) to which the output 1 is input.

In the above case, the output 2 is (M
Data "1000.SB" in which only the 1st bit of SB-1 is "1" and each bit of (MSB-2) th bit and below is "0".
0 "=-8 (decimal display), that is, (-MAX) is output.

When the value of the waveform data X is -7 (displayed in decimal), the binary display is "1001.00".
And the MSB is “1”. Therefore, the arithmetic unit 101
Subtracts the value “1” at the least significant bit digit of the waveform data X = “1001.00”. As a result, the parallel data PDT output from the arithmetic unit 101 is “1000.1
1 ″ = − 7.25 (decimal display).

In this case, the parallel-serial converter 102 shown in FIG. 2 has the parallel data PDT "1000.11"
Data "000.11" excluding "1" of MSB is output. Therefore, from the serial-serial converter 102, as serial data output Y, "0", "0", "0",
"1" and "1" are sequentially output.

When the data of the output 1 is obtained according to the truth table of FIG. 5, the first "0" corresponding to the (MSB-1) th bit of the waveform data X among the data "000.11" of the output Y is obtained. “” Is first inverted to “1” by the NOR 206 (see FIG. 2), and then the control signal MSBINV is set to “1”.
Is further inverted to "0" based on the above, and is output as output 2. In addition, the data string “00.11” of the (MSB−2) th bit or less of the waveform data X is inverted to “11.00” by the NOR 206 (see FIG. 2) and then the control signal MSB.
Output as "11.00" based on "0" of INV 2
Is output as. As a result, the value of the waveform data X-7.
0 (“1001.00”) is the value of output 2 +6.0
Is converted to (“0110.0”). In this case as well, the position of the decimal point is determined according to the D / A converter 803 (see FIG. 8) to which the output 2 is input.

In the above case, the output 1 is (M
Data "1000.SB" in which only the 1st bit of SB-1 is "1" and each bit of (MSB-2) th bit and below is "0".
0 "=-8 (decimal display), that is, (-MAX) is output.

FIG. 7 is a diagram showing waveforms before and after conversion by the sine magnitude calculation method, and corresponds to FIG. Figure 7
, A, A ′, B, B ′, C, and D respectively correspond to the ranges with the same symbols in FIG. 9.

As described above, in the embodiment of the present invention, one parallel-serial converter 102 shown in FIG.
1, inverters 202, 205, NOR 203, 20
6, and a simple data converter 103 composed of EORs 204, 207, etc., can constitute the main part of the sine magnitude arithmetic circuit. <Other Embodiments> In the above embodiments, the arithmetic unit 101 of FIG.
Is realized by a general-purpose microprocessor, but may be realized by a dedicated hardware circuit.

Further, as still another embodiment, the following configuration may be realized. That is, first, the arithmetic unit 10 of FIG.
1 outputs the waveform data X as it is when the MSB is “0”, and inverts the sign of the waveform data X when the MSB is “1” and outputs a positive sign having the same amplitude as that. The parallel data PDT that it has is calculated and output.

The parallel-serial converter 102 converts the data consisting of the (MSB-1) th bit or less of the parallel data PDT output from the arithmetic unit 101 into serial data.

The logical operation circuit in the data converter 103 is
Of each bit of the serial data output from the parallel / serial converter 102, the bit corresponding to the (MSB-1) th bit of the waveform data X is inverted and output, and the (MSB-2) bit is output. The bits corresponding to the bits below the eye are sequentially output as they are.

The first output circuit in the data converter 103 outputs 1 when the MSB of the waveform data X is "0".
As the output of each bit of the serial data output from the above logical operation circuit. When the MSB of the waveform data X is "1", the output 1 is the (MS
Bits corresponding to the (B-1) th bit have a value of "1", and bits corresponding to the (MSB-2) th bit and below of the waveform data X have a value of "0".

The second output circuit in the data converter 103 outputs the output 2 when the MSB of the waveform data X is "0".
, The bit corresponding to the (MSB-1) th bit of the waveform data X has the value "1" and the (MSB-
2) The bit corresponding to the bits below the second bit has the value “0”
Is sequentially output, and when the MSB of the waveform data X is "1", each bit of the serial data output from the above-described logical operation circuit is sequentially output as the output 2.

With the embodiment having such a structure, the same effect as that of the above-described embodiment (see FIG. 2) can be realized by only one para / serial converter 102.

[0081]

In the sine magnitude calculation, when the input parallel waveform data has a negative sign, the sign of the negative input parallel waveform data is inverted and the parallel waveform data having a positive sign having the same amplitude as that is calculated. However, according to the first aspect of the present invention,
By performing the operation of subtracting the value “1” at the least significant bit digit of the negative input parallel waveform data, which is a part of the above operation, and outputting the subtraction result before the parallel / serial conversion processing, It is possible to reduce the number of parallel / serial conversion means required in the configuration for sine magnitude calculation to one.

Further, according to the second aspect of the present invention, all the above-mentioned operations are performed before the parallel / serial conversion process, so that the parallel / serial conversion means also necessary in the configuration for the sine magnitude operation. The number of can be 1.

As a result, the circuit scale can be reduced and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a sine magnitude arithmetic circuit according to the present invention.

FIG. 2 is a circuit configuration diagram of an embodiment of a sine magnitude arithmetic circuit according to the present invention.

FIG. 3 is an operation flowchart related to sine magnitude calculation.

FIG. 4 is an operation timing chart of a sine magnitude arithmetic circuit.

FIG. 5 is a truth table showing signal states of respective parts of the sine magnitude arithmetic circuit.

FIG. 6 is a diagram showing an example of waveform data X before conversion and output 1 or output 2 after conversion by a sine magnitude calculation method.

FIG. 7 is a waveform diagram before and after conversion by a sine magnitude calculation method.

FIG. 8 is a basic configuration diagram of a sine magnitude output device.

FIG. 9 is a waveform diagram showing the operating principle of the sine magnitude output device.

FIG. 10 is a basic configuration diagram of a conventional sine magnitude arithmetic circuit.

[Explanation of symbols]

 101 arithmetic unit 102 parallel-serial converter 103 data converter 201 D-flip-flop (DFF) 202, 205 inverters 203, 206 NOR circuit (NOR) 204, 207 exclusive OR circuit (EOR) 801 sine magnitude arithmetic circuit 802, 803 D / A converter 804 operational amplifier R1 variable resistor R2, R3, R4 resistor

Claims (4)

[Claims] 1. For input parallel waveform data consisting of a predetermined number of bits, when the input parallel waveform data has a positive sign, the input parallel waveform data is output as it is, and the input parallel waveform data has a negative sign. And a means for subtracting the value “1” at the least significant bit digit from the input parallel waveform data and outputting the subtraction result, other than the most significant bit of the parallel waveform data output from the arithmetic means. Parallel / serial conversion means for converting parallel waveform data composed of bits into serial waveform data; and, if the input parallel waveform data has a positive sign, the serial waveform data output from the parallel / serial conversion means. Bit of each bit of the input parallel waveform data that is one bit lower than the most significant bit The value of the corresponding bit is inverted and output as the first output serial waveform data, bits other than the bit are sequentially output as they are as the first output serial waveform data, and the input parallel waveform data is negative. If it has a sign, the bit corresponding to the bit one bit lower than the most significant bit of the input parallel waveform data as the first output serial waveform data has the value “1” and the other bits have the value. First output means for sequentially outputting each bit that is "0", and when the input parallel waveform data has a negative sign, all bits of the serial waveform data output from the parallel / serial conversion means Of each bit of the inverted serial waveform data after being sequentially inverted, the most significant bit of the input parallel waveform data. For the bit corresponding to the bit lower by one bit, the value is inverted and output as the second output serial waveform data, and the bits other than the bit are sequentially output as they are as the second output serial waveform data. When the input parallel waveform data has a positive sign, the bit corresponding to the bit one bit lower than the most significant bit of the input parallel waveform data is the value “1” as the second output serial waveform data. Bits other than the bit have a value of "0", second output means for sequentially outputting the respective bits, and first digital / analog conversion for converting the first output serial waveform data into a first analog waveform signal. Means, second digital / analog conversion means for converting the second output serial waveform data into a second analog waveform signal, and the second Sign Magnitude output apparatus characterized by having an analog waveform calculation means, the said analog waveform signal second subtracts the analog waveform signal and outputs the subtraction result as an output analog waveform signal. 2. With respect to input parallel waveform data consisting of a predetermined number of bits, when the input parallel waveform data has a positive sign, the input parallel waveform data is output as it is, and the input parallel waveform data has a negative sign. And the arithmetic circuit that subtracts the value “1” from the input parallel waveform data at the least significant bit digit and outputs the subtraction result, other than the most significant bit of the parallel waveform data output from the arithmetic means. A parallel / serial conversion circuit for converting parallel waveform data composed of bits into serial waveform data, and while the parallel / serial conversion means outputs the serial waveform data corresponding to the input parallel waveform data for one sample. , A flip-flop that holds the most significant bit of the parallel waveform data output from the arithmetic means. A circuit, a first inverter circuit that sequentially inverts each bit of the serial waveform data output from the parallel / serial conversion means, and an output of the flip-flop circuit as a first input, the first inverter circuit The output of is the second input
NOR circuit, a second inverter circuit that inverts the output of the flip-flop circuit, an output of the second inverter circuit as a first input, and an output of the parallel / serial conversion means as a second input. And a second NOR circuit for outputting a bit corresponding to a bit one bit lower than the most significant bit of the input parallel waveform data as the serial waveform data from the parallel / serial conversion means. A first exclusive-OR circuit having a control signal that becomes a low level at the timing when the bit of is output as a first input and an output of the first NOR circuit as a second input; A second exclusive OR circuit having an input of 1 and an output of the second NOR circuit as a second input; and a system output from the first exclusive OR circuit. A first digital / analog converter for converting the analog waveform data into a first analog waveform signal, and a second digital / analog converter for converting the serial waveform data output from the second exclusive OR circuit into a second analog waveform signal. A digital / analog converter, and an analog waveform arithmetic circuit that subtracts the second analog waveform signal from the first analog waveform signal and outputs the subtraction result as an output analog waveform signal. Sign magnitude output device. 3. For input parallel waveform data consisting of a predetermined number of bits, when the input parallel waveform data has a positive sign, the input parallel waveform data is output as it is, and the input parallel waveform data has a negative sign. In the case of the above, the calculation means for inverting the sign of the negative input parallel waveform data and calculating and outputting the parallel waveform data having the positive sign having the same amplitude as that, and the parallel waveform data output from the calculation means. Parallel / serial conversion means for converting parallel waveform data composed of bits other than the most significant bit into serial waveform data, and the input parallel waveform data of each bit of the serial waveform data output from the parallel / serial conversion means The bit corresponding to the bit one bit lower than the most significant bit of Is inverted and output, and bits other than the bit are sequentially output as they are, and when the input parallel waveform data has a positive sign, the logical operation means outputs first output serial waveform data as the first output serial waveform data. Each bit of the output serial waveform data is sequentially output, and when the input parallel waveform data has a negative sign, the first output serial waveform data is 1 bit from the most significant bit of the input parallel waveform data. First output means for sequentially outputting each bit in which the bit corresponding to the lower bit has a value "1" and the bits other than the bit have a value "0"; and the input parallel waveform data has a positive sign. If it has, it corresponds to a bit one bit lower than the most significant bit of the input parallel waveform data as the second output serial waveform data. The bits having the value "1" and the bits other than the bits having the value "0" are sequentially output, and when the input parallel waveform data has a negative sign, the second output serial waveform Second output means for sequentially outputting each bit of the serial waveform data output from the logical operation means as data, and a first digital / digital converter for converting the first output serial waveform data into a first analog waveform signal. Analog conversion means, second digital / analog conversion means for converting the second output serial waveform data into a second analog waveform signal, and subtracting the second analog waveform signal from the first analog waveform signal And a sine magnitude output device comprising: an analog waveform calculation means for outputting the subtraction result as an output analog waveform signal. 4. The sine magnitude output device according to claim 1, wherein the input parallel waveform data is tone waveform data.