JPH0448253B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multiplication circuit, and is used, for example, to generate envelope waveforms for digital filters and electronic musical instruments in which the multiplication output is fed back to the input side of the multiplication circuit and is repeatedly calculated. This can be applied to circuit reverberation effect devices, etc.

[Summary of the invention]

In the present invention, in a multiplication circuit, a 1 addition control signal, which is generated with a probability corresponding to the value of the lower bit data, is added to the upper bit data of the product data obtained by multiplying the input data by the multiplication data. By setting the multiplication output data as the multiplication output data, multiplication output data of a predetermined number of bits with a small error can be obtained.

[Conventional technology]

Conventionally, for example, second-order IIR (infinite impulse
Multiplication circuits are used in digital filters such as response) filters and latex filters, envelope generation circuits for electronic musical instruments, reverberation effect devices, and the like.

In such a device, product data indicating a multiplication result from a multiplication circuit is processed by a data processing circuit, and then fed back as multiplication input data to the multiplication circuit,
In this way, the multiplication circuit is used to perform repeated operations. Therefore, in order to prevent the product data from diverging due to repeated calculations, the multiplication data to be multiplied by the input data is selected to be smaller than "1".

Therefore, for example, when input data consisting of M-bit integer part data is multiplied by multiplication data consisting of N-bit fractional part data in a multiplication circuit, the result of the multiplication is that the integer part is M bits and the whole is Product data MUL of maximum M+N bits can be obtained.

By the way, using the multiplication circuit as described above,
As a method of generating a waveform signal representing an envelope waveform of an electronic musical instrument, a function signal generating circuit as shown in FIG. 8 has been proposed (Japanese Patent Publication No. 39434/1983).

This function signal generation circuit feeds back the current value data S _b obtained at the output end of the shift register 1 to the subtracter 2 and subtracts it from the target value data S _a .
Minimal coefficient data having a value of 1 or less (for example, 2 ^-8 ) in the multiplier 3 for the subtracted output D ₁
Multiply by S _c . Thus, the data D ₂ obtained at the output end of the multiplier 3 becomes minute value data having a size corresponding to the difference between the target value data S _a and the current value data S _b .

This minute value data _D2 is applied to the adder 5 as one addition input via the gate circuit 4 at the timing of the clock signal CK. Adder 5 has
The current value data S _b is given as the other addition input, and by adding the minute value data D ₂ to the current value data S _b at the output terminal of the adder 5 at the timing of the clock signal CK. An addition output D ₃ is obtained that increases or decreases by the minute value data D ₂ as time passes, and this addition output D ₃ is input to the shift register 1 as new current value data.

In the configuration shown in FIG. 8, the shift register 1 operates as a delay circuit, and each time the delay time elapses, new current value data S _b is sent to the subtracter 2, so that the target value data S _a and the current value Value data S _b
The minute value data D ₂ corresponding to the difference between the two values is repeatedly added to the current value data S _b . In this way, as shown in FIG. 9 or FIG. 10, a function signal representing a rising or falling waveform that increases or decreases as time approaches the target value S _a is generated. can do.

[Problem that the invention seeks to solve]

However, in the function signal generation circuit with this configuration, as the current value data S _b approaches the target value data S _a , the multiplication result of the multiplier 3 becomes a very small value, and the value of the minute value data D ₂ becomes the value of the adder. 5, the adder 5 discards this value, which becomes an error, and the current value data S _b cannot reach the target value data S _a .

In practice, if we consider that the value of the addition input data (which is assumed to be an integer value for convenience) on which the adder 5 can perform the addition operation is limited, the addition input data having a value below the decimal point (i.e., a decimal number) cannot be added. If the micro value data D ₂ which is the output of the multiplier 3 is a value below the decimal point, it will be truncated.

Therefore, as shown in FIGS. 9 and 10, when the current value S _b approaches the target value, the minute value data D ₂ cannot be added to the adder 5, and errors ΔE ₁ and ΔE ₂ are generated in the function signal. There is a risk that it will remain.

In short, the lower bits (data in the decimal part) of the multiplication result of the multiplier 3 are discarded, and only the upper bits (data in the integer part) are used as multiplication output data in the adder circuit 5 at the next stage.

Therefore, if you want to truncate the decimal part of the data,
It may be possible to round off the value to the nearest whole number. However, if you try to round off the binary coded data, the structure becomes very complicated.

This invention was made in consideration of the above points, and when the lower bits of the multiplication result are rounded down and the remaining upper bits are used as the actual multiplication output data, the error in the multiplication output data is kept as small as possible. The purpose of this paper is to provide a multiplication circuit that can perform the following functions.

[Means for solving problems]

In order to solve this problem _, in the present invention, as shown in the principle configuration in _FIG . A carry control means CAR generates a 1 addition control signal _S6 with a probability corresponding to the value of lower bit data _S4 of a predetermined number of bits out of ₃ , and adds 1 to upper bit data _S5 of product data _S3 . and an addition means ADD for adding the control signal _S6 , and the added value in the addition means ADD is made to be the multiplication output data _S7 .

[Effect]

In FIG. 11, the carry control means CAR is
A 1 addition control signal _S6 is generated that rises to the logic "1" level with a probability corresponding to the value of the decimal part data _S4 of the product data _S3 of the multiplication means MUL. Generally, a decimal value is a ratio of 1 (e.g. a percentage)
Therefore, the decimal value represents the probability that the integer value is "1". Therefore, the fractional data S ₄
represents the time required to reach the integer value "1" when this is repeatedly added, and the decimal part data
If the value of S ₄ is small, the probability becomes small, and therefore, when the decimal part data S ₄ is repeatedly added, it takes a long time to reach the integer value "1". On the other hand, if the value of the decimal part data S ₄ is large, the time until the integer value "1" is reached when the decimal part data S ₄ is repeatedly added becomes shorter.

Thus, the 1 addition control signal S ₆ is applied to the addition means ADD.
The frequency at which is given corresponds to the numerical value of the decimal part data _S4 , and as a result, the addition means ADD adds "+1" to the integer part data _S5 by the 1 addition control signal _S6 based on the decimal part data _S4 . ” Output data _S7 of the added value is obtained.

As a result, "+1" is added to the integer part of the multiplication result of the multiplication means MUL with a probability corresponding to the value of the decimal part, and as a result, the expected value of the multiplication output data _S7 which selected the integer part is the multiplication result. is equal to
Errors caused by truncating the decimal part can be reduced.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a function signal generation circuit used, for example, in an envelope signal formation circuit of an electronic musical instrument will be described in detail with reference to the drawings.

In FIG. 1, 11 indicates the function signal generation circuit as a whole, and an adder 12 (adding means in FIG. 11)
For example 8 obtained at the output end of (corresponding to ADD)
Current value data S _PRX consisting of bit parallel data
is sent out as the output S _OUT of the function signal generation circuit 11, and is also fed back to the subtraction input terminal of the subtracter 14 via the delay circuit 13.

The subtracter 14 subtracts this current value data _SPR from the target value data _STA consisting of 8-bit parallel data, and the subtracted output data _SSB consisting of 8-bit parallel data obtained at the output terminal is sent to the multiplier 15.
(corresponding to the multiplication means MUL in FIG. 11).

The multiplier 15 outputs minute coefficient data _SMI , which is 8-bit parallel data, to the subtracted output data _SSB .
The product data _SMU consisting of 16-bit parallel data is sent out.

Here, the minute coefficient data S _MI is the subtracted output data
S _SB is multiplied by a value less than 1, for example, a minute coefficient of 2 ^{- 8} , to produce 16-bit product data S _MU consisting of 8-bit integer part data S _IT and 8-bit decimal part data S _DC . Send out.

Of the product data S _MU , the integer part data S _IT is given as the first addition input of the adder 12, and is added to the current value data S _PR obtained at the output terminal of the delay circuit 13, and the addition result S _PRX is sent out via the delay circuit 13 as new current value data S _PR .

On the other hand, the decimal part data S _DC of the product data S _MU is given to the carry control circuit 16 (corresponding to the carry control means CAR in FIG. 11), and
The 1 addition control signal _SCR obtained at the output terminal of this carry control circuit 16 is applied to the carry input terminal CI of the adder 12.
given to.

The carry control circuit 16, as shown in FIG.
8-bit data a0 to a7 constituting the 8 bits constituting the decimal part data _SDC are received at terminals _{T00 to T07} and input to corresponding AND circuits _{AD0 to AD7 .}

In addition, the carry control circuit 16 has a probability generation circuit 21, which generates probability outputs consisting of eight probability outputs _b0 to _b7 corresponding to each bit of data _a0 to _a7 of the fractional part data _SDC . Data S _PRO is generated and each probability output data b ₀ to b ₇ is input to the corresponding AND circuits AD ₀ to _{AD 7} .

The output of AND circuit AD ₀ to _{AD 7} is OR circuit OR ₁
It is sent as the 1 addition control signal _SCR through

Here, the probability output data b ₀ to b ₇ are 2 bits of 8 bits.
It is a pulse output representing a base number ²⁰ to ²⁷ , and rises to the logic "1" level with a probability corresponding to the weighting of the corresponding bit data _a0 to _a7 of the decimal part data S _DC as time passes. The data is
Each of them is formed by a probability generation circuit 21 configured as shown in FIGS. 3 to 5.

As shown in FIG. 3, the probability generation circuit 21 has 8
bit counter 25, priority selection encoder 26,
It has a decoder 27. The 8-bit counter 25 counts the clock signal φ of a predetermined period, and
The output power S _BIN is output to the input terminal of the priority selection encoder 26.

The priority selection encoder 26 inputs the 8-bit count output S _BIN to the input terminal T ₄₀ as shown in FIG.
~ _T47 , a logic circuit consisting of inverters _IN11 ~ _IN14 , AND circuits _AD11 ~ _AD15 , and OR circuits _OR11 ~ _OR13 sets the priority selection encoder 26 in FIG. As shown, input terminal T ₄₀ ~
Out of _T47 , the terminal number whose logic is "1" first when viewed from the lower bit side is selected preferentially, and a predetermined binary code is encoded and output S _PRE to the corresponding output terminals _T50 to _T52 . Send out.

In this way, the output terminal T ₃₀ of the 0th bit of the 8-bit counter 25 and the output terminal of the 1st bit
T ₃₁ , the output terminal T ₃₂ of the second bit...the output terminal T ₃₇ of the seventh bit are at the logic "1" level, and the probability that the lower bit thereof is at the logic "0" level is sequentially 1 /2 ¹ = 1/2, 1/2 ² = 1/
4. 1/2 ³ = 1/8...1/2 ⁸ = 1/256.

In this embodiment, the priority selection encoder 26 sets the logic "1" to the seventh bit.
It is possible to output a probability output of 1/128 as a probability output of "0".

This means that for a given computation time T _REF , for example
Based on the arrival time of 128 clock pulses, the output terminal of the priority selection encoder 26
The timing at which the output of logic "111" is obtained at T ₅₂ , T ₅₁ , and T ₅₀ is during 1/2 of the predetermined calculation time T _REF , and therefore, during the calculation time T _REF .
The output of logic "111" will be obtained 64 times.

Similarly, the output terminal of the priority selection encoder 26
Logic "110", "101" for T ₅₂ , T ₅₁ , T ₅₀ ...
The timing at which "001" and "000" are obtained is sequentially 1/4 time (corresponding to 32 pulses), 1/4 time
8 time (equivalent to 16 pulses)...1/
128 times (equivalent to 1 pulse), 1/128
(corresponding to one pulse), thus the probability is 1/2, 1/
4, 1/8...Data representing 1/128, 1/128 is sent to the output terminal T ₅₂ of the priority selection encoder 26,
This can be obtained by the encoded output _SPRE sent from T ₅₁ and T ₅₀ .

The decoder 27 receives the encoded output _SPRE and outputs logic "1" level data from one of the output terminals _T70 to _T77 in accordance with the code of the encoded output _SPRE . Thus, the probabilities that the output terminals T ₇₇ , T ₇₆ , T ₇₅ ...T ₇₁ , T ₇₀ of the decoder 27 become logic "1" are 1/2, 1/4, and 1/4, respectively.
1/8...1/128, 1/128.

This means that the output terminals T ₇₇ of the decoder 27,
T ₇₆ , T ₇₅ ...... The period at which T ₇₁ and T ₇₀ become logic "1" is 2 ¹ times, 2 ² times ... based on the period of terminal T ₇₇ .
It means that it will increase ²⁷ times, ²⁷ times.

Output terminals T ₇₇ , T ₇₆ , T ₇₅ ... of this decoder 27
...The probability outputs obtained at T ₇₁ and T ₇₀ are sent to the AND circuits AD ₀ , AD ₁ , AD ₂ ...AD ₇ (Fig. 2) as probability output data S _PRO of the probability generation circuit 21, respectively (Fig. 2), and The output is sent from the carry control circuit 16 to the adder 12 as a 1 addition control signal _SCR through the OR circuit _OR1 .

In the above configuration, when the function signal generation circuit 11 starts the calculation operation at time t ₀ in FIG.
The subtracter 14 sends the target value data _STA , which is an integer, to the multiplier 15 as subtraction output data _SSB , and the multiplier 15 multiplies the subtraction output data _SSB by 8-bit minute coefficient data _SMI . .

As a result, 16-bit product data S _MU consisting of the upper 8 bits of integer part data S _IT and the lower 8 bits of decimal part data S _DC is obtained at the output terminal of the multiplier 15, and the integer part data S _IT is added to the current value data S _PR in the adder 12, and the decimal part data
The carry control circuit 16 converts S _DC into a 1 addition control signal S _CR .

Here, the carry control circuit 16 controls the decimal part data.
8-bit data _a0 to _a7 that make up S _DC (Figure 2)
Among them, by giving data at the logic "1" level as the first input condition of the corresponding AND circuits AD ₀ to _{AD 7} , the probability output b ₀ constituting the probability output data S _PRO of the probability generation circuit 21 is generated. The data corresponding to ~ _b7 is extracted and sent as the ₁ addition control signal _SCR via the OR circuit OR1.

For example, 8-bit data of decimal part data S _DC
Assuming that a ₇ to _{a 0} are "01000010", the data a ₆ of the 6th bit and the data a ₁ of the 1st bit become logic "1", and the other 7th bit, 5th to 2nd bit Since the data a ₇ , a ₅ to a ₂ , a ₀ of the 0th bit are logic "0", the AND circuit AD ₆ corresponds to the data a ₆ and a ₁ which are logic "1".
and AD ₁ , only the probability outputs b ₆ and b ₁ are extracted and sent as the 1-addition control signal S _CR .

By the way, the probability outputs b ₆ and b ₁ of the 6th bit and the 1st bit have probabilities of 1/4 and 1/128, respectively (Figure 5), which means that the probability output b ₆ is logical This means that the period at which the probability output b1 of the first bit becomes logic "1" is 4 clock cycles, while the period at which the probability output _b1 of the first bit becomes logic "1" is 128 clock cycles. As a result, the 1 addition control signal S _CR becomes logic "1", and the adder 12 becomes "+1".
The timing of adding “+1” to the integer part data S _IT by adding operation is the decimal part data.
S _DC occurs every 4 clock pulses for the 6th bit of data a ₆ and every 128 clock pulses for the 1st bit of data a ₁ .

In this way, the adder 12 selects the product data _SMU from the product data SMU.
Similarly, for 8-bit integer part data S _IT , 8
By adding the current value data S _PR consisting of bit integer part data, new 8-bit current value data S _PR can be obtained. At the same time,
For the 8-bit integer part data S _IT , a 1 addition control signal S _CR whose content is an integer value "1" is generated for each period corresponding to the probability corresponding to the value of the decimal part data S _DC .
Send out.

In this way, the adder 12 can obtain the addition output S _PRX in consideration of the value of the decimal part data by adding "+1" to the integer part data S _IT with a probability corresponding to the value of the decimal part data S _DC . become.

To obtain such a result, the adder 12 uses the same number of bits as the integer part data S _IT , that is, 8 bits.
It is sufficient to configure the adder 12 with a bit adding circuit, thus making it possible to avoid complicating the configuration of the adder 12.

According to experiments, as shown in FIG. 7, the function signal KO in the conventional case has an error with respect to the target value _STA , but according to the present invention, as shown by the symbol K1,
We were able to generate a function signal with no residual error.

In addition, in the above embodiment, the function signal output
When calculating S _OUT , we have described the case where parallel calculations are performed using parallel data, but instead of this, the same effect as in the above case can be obtained by performing serial calculations using serial data. be able to.

In addition, in the above embodiment, an example was described in which one series of function signals S _OUT is obtained, but for example, when assigning different envelopes to multiple musical tones, multiple series of function signals S OUT are obtained. If necessary, the calculation of the function signal of each series may be performed in a time-sharing manner.

Further, in the above-described embodiment, the present invention is applied to a function generating circuit used in an envelope signal forming circuit of an electronic musical instrument that performs repeated calculations, but the present invention is not limited to this, for example. The present invention can be widely applied to various circuits that use the upper bits of the multiplication result as actual multiplication output data, such as digital filters and reverberation effects of electronic musical instruments.

〔Effect of the invention〕

As described above, according to the present invention, the lower bit information that is discarded when the multiplication output data is sent out is changed to
Since it is included in the multiplication output data as an addition signal, it is possible to easily obtain a multiplication circuit that can reduce errors in the multiplication output data.

[Brief explanation of drawings]

FIG. 1 shows a connection section of a function signal generation circuit to which an embodiment of the multiplication circuit according to the present invention is applied; FIGS. 2 to 5 are connection diagrams and charts showing the detailed configuration of the carry control circuit 16; Fig. 6 is a characteristic curve diagram for explaining the operation of Fig. 1, Fig. 7 is a characteristic curve diagram showing experimental results, Fig. 8 is a connection diagram showing a conventional function signal generation circuit, and Figs. 9 and 10. 11 is a characteristic curve diagram for explaining the problem, and FIG. 11 is a block diagram showing the basic structure of the present invention. 11...Function signal generation circuit, 12...Adder,
13... Delay circuit, 14... Subtractor, 15... Multiplier, 16... Carry control circuit.

Claims (1)

[Claims] 1. Multiplying means for multiplying input data by multiplier data, and generating a 1 addition control signal with a probability corresponding to the value of lower bit data of a predetermined number of bits of the product data output from the multiplication means. and an addition means for adding the upper bit data of the product data and the 1 addition control signal, and the added value in the addition means is used as multiplication output data. A multiplication circuit.