JPS607815B2 - Overflow detection and correction circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to overflow detection and correction circuits.

Outside of the secondary cyclic digital filter, overflow occurring in the output of the adder may cause an oscillation phenomenon called a limit cycle, which poses a problem.

Therefore, it is necessary to perform overflow detection and overflow correction to prevent limit cycles from occurring. In the following explanation, all input and output data will be expressed as 2 bucket numbers, and the data will be in a serial data format in which the least weighted bit (hereinafter abbreviated as LSB) comes first in time.

FIG. 1 shows an example of a conventional overflow detection circuit.

Two data X and Y to be added are input to terminals 1 and 2, and data Z=X+Y after addition is input to terminal 3.

Furthermore, a timing pulse indicating the position of a sign (polarity) bit (hereinafter abbreviated as MSB) is input to the terminal 4. The two input data to be added ×, the sign (polarity) of Y are both negative 1”) and the sign (polarity) of data Z after addition
is positive (''0''), the output of the NAND element 10 becomes "1" and is output to the terminal 100, indicating that a negative overflow has occurred. If the signs of input data x and Y are both positive (''0''), and the sign of data Z after addition is negative (``1''),
The output of NAND element 020 becomes “1” and terminal 200
1 is output, indicating that a positive overflow has occurred.

FIG. 2 shows an example of a conventional overflow correction circuit.

Information indicating that a positive overflow has been detected is input to terminals 1 and 2, and information indicating that a negative overflow has been detected is input to terminals 3 and 4.

Here, it is assumed that there are two sets of overflow detection circuits.

Further, the positive number with the maximum absolute value is input to the terminal 5, and the negative number with the maximum absolute value is input to the terminal 6.

If overflow occurs due to the above configuration,
The maximum number of absolute values depending on the sign is available at terminal 8. Further, when no overflow occurs, the data Z input to the terminal 7 is output to the terminal 8 as is. FIG. 3 is a block diagram of an overflow detection and correction circuit constructed by combining the overflow detection circuit shown in FIG. 1 and the overflow correction circuit shown in FIG. 2.

Reference numeral 1 means the overflow detection circuit shown in Figure 1, reference numerals 20 and 30 refer to flip-flops, reference numeral 40 represents the positive and negative maximum value generation circuit, reference numeral 50 represents the overflow detection circuit shown in Figure 2. The circuit, reference numeral 60, is a one word length shift register.

As shown in FIG. 1, two data to be added are input to terminals 1 and 2, and data after addition is input to terminal 3.

Also, when a positive overflow occurs, terminal 11 becomes "1" at the MSB, and when a negative overflow occurs, the MSB
At the time point, the terminal 12 becomes "1". Therefore, in order to correct data that has caused overflow, flip-flop 2
It is necessary to hold information for one word length as to whether or not overflow has occurred using 0 and 21. Furthermore, the data after the addition is given to 6 shift registers, and the length is 1 word (1 data).
output 61 delayed by minutes and positive and negative maximum number generation circuit 4
0 outputs 41 and 42 and the output 2 of flip-flop 20
1 and the output 31 of the flip-flop 30 are input to the overflow correction circuit 50, output data with overflow corrected is obtained at the terminal 4. As mentioned above, the conventional overflow detection circuit and overflow correction circuit have SS1
(Small sized integrated circuit) is used, so there is a disadvantage that the number of ICs is large and the hardware scale increases.

An object of the present invention is to provide an overflow detection and correction circuit that integrates an overflow detection circuit and an overflow correction circuit and has a simplified configuration.

Another object of the present invention is to provide an overflow detection and correction circuit with a small circuit scale.

The overflow detection and correction circuit of the present invention includes a read-only memory, a shift register, and three first, second, and third flip-flops, and has two types of outputs: the outputs of the three flip-flops and the output of the shift register. The timing pulse and three types of serial data X, Y, and Z are used as 9 inputs of the above-mentioned input-only memory, and 2 outputs out of 3 outputs of the above-mentioned input-only memory are connected to the first and second flip-flops, respectively. It is characterized in that the serial data Z is configured to be used as a 0 input to the third flip-flop and the shift register.

First, before explaining the present invention, the relationship between the number of bits of one word length and overflow will be described. Let the data word length be M bits, and consider it as (M-2) bits below the decimal point. In this case, the value of the data x that can be displayed is -2mi x<2. Now, assume that the two data to be added are X and Y, and the data of their sum is Z. However, Z=X0Y, and
, Y, and Z are all expressed in M bits. It is also assumed that the input data X and Y are in the range of -2x<2, -2SY<2, and the output Z satisfies the condition -ISZ<1. Therefore, Z becomes -4SZ<4, and -ISZ<
Z that does not satisfy condition 1 is considered to have caused an overflow. Therefore, cases where overflow occurs are limited to the following two cases. First, Z is -2miZ<-1,1miZ
<2.

At this time, overflow can be detected by determining whether the upper two bits match or do not match. In addition, the true code that does not cause overflow at this time (synchronization) coincides with the MSB of Z.
The second case is when Z is in the range of -4SZ<-2, 2miZ<4. At this time, overflow can be detected because input data x and Y have the same sign, and Z has a different sign. Further, the true sign (polarity) that does not cause overflow at this time matches the MSB of input data x or Y. As described above, overflow is limited to the first case and the second case, so overflow detection and overflow correction can be performed for the above two cases. Next, the present invention will be explained in detail with reference to the drawings.

FIG. 4 is a diagram showing one embodiment of the present invention. This is a diagram. Reference numeral 3 is a 512 word x 3 bit ROM, reference numerals 1, 4 and 5 are flip-flops, and reference numeral Z is a shift register. The contents written to the ROMI in FIG. 4 are shown in Tables 1, 2, and 3. Table 1 Table 2 In Tables 1, 2 and 3, the symbol OFn-,,
sn-,, Zn, Zn-,, ×, y and di indicate input bits, symbols OFn, sn and d.

indicates an output bit. Also, the symbol 0/1 is “0” or “
Table 1 shows the contents of the ROM 3 when the timing pulse indicating the position of the MSD is "1".

When the output bit OFn is "1", it indicates that an overflow has occurred, and when it is "0", it indicates that an overflow has not occurred. For example, Zn="0", Zn-,="1", x
When ="0" and y="0", the MSB of sum Z is Zn=
“0”, and the bit 1 bit before the MSB is Zn-
, = "1", it is regarded as an overflow in the first case described above, and the output bit OFn = "1". Also, Zn=“0”, Zm=“0”, ×=“1” and Y=
When it is “1”, the MSB of the sum Z is Zn="0", and the MSB of the input x, Y at this time is X="1", Y="1", so the above second In this case, it is considered that there is an overflow, and the output bit OFn is set to "1". Output bit sn has meaning only when output bit OFn is "1", and outputs the same sign as the true addition result when overflow does not occur. For example, in the above example, Zn="0",
When Zn-, = “1”, X = “0” and Y = “0”, the true addition result without overflow is positive, so sn
= “0”. Also, Zn="0", Zn-,="0"
”, X=“1” and Y: “1”, the true addition result without overflow is negative, so sn=“1”. Output bit d. is the same as the input bit di when the output bit OFn is “0”, and when the output bit OFn is “1”
”, the content is opposite to that of the input bit Sn-.Table 2 shows the contents when both the timing pulse indicating the MSB position and the timing pulse indicating the layer 2 bits before the MSB are “0”. This shows the contents of ROM3.

Input bit OFn- and output bit OFn have exactly the same content, and input bit sn- and output bit sn also have exactly the same content. Furthermore, the output bit d. has the same content as the input bit di when the output bit OFn is "0", and has the opposite content as the input bit sn- when the output bit OFn is "1". Table 3 shows M
The timing pulse indicating the position 2 bits before SB is '
This shows the contents of the ROM3 when the value is '1'.

Input bit OFM and output bit OFn have exactly the same contents, but input bit sn- and output bit sn have opposite contents. Also, output bit d. When the output bit OFn is "0", it has the same content as the input bit di, and when the output bit OFn is "1", it has the same content as the input bit sn-. Input bits x, y, and Zn of Tables 1, 2, and 3 appear at input terminals 300, 400, and 600, respectively, of FIG. 4.

Also, the input bits OFm, sn-, , Zn-, and d
i are inputs 40, 50, 10 and 2 of ROM3, respectively
It corresponds to 0. Furthermore, Tables 1, 2 and 3
Table output bits OFn, sn and d. are the fourth
This corresponds to outputs 30, 31 and 32 in the figure. In FIG. 4, terminals 100 and 200' are respectively M
A timing pulse indicating the position of the SB and a timing pulse indicating the position 2 bits before the MSB are input. Now, when the MSB of three serial data X, Y and Z are input to terminals 300, 400 and 50 respectively,
Output bit O read from ROM3 according to Table 1
Fn, sn and d.

occur as outputs 30, 31 and 32. Outputs 30 and 31 of ROM3 corresponding to output bits OFn and sn are set to 1 by flip-flops 4 and 5, respectively.
After being bit delayed, it is fed back to the input 40 (O
F town) and 40 (sn-,). The ROM 3 outputs bits OFm sn and d according to Table 2 until the timing pulse indicating the position 2 bits before the MSB becomes "1".

Read out. Next, when the timing pulse indicating the position 2 bits before the MSB is "1", the ROM 3 outputs bits OFm sn and d according to Table 3. Read out.
Finally, at one bit before the MSB, ROM3 outputs bits OFn, sn, and d according to Table 2.

Read out. The operation for removing the ROM3 repeats the above-described operation.

The shift register 2 in FIG. 3 has (M-1) bits.
Next, the operation of the present invention will be explained using a specific example.

Let the data word length (M) be 5 bits and consider the following addition. However, $B represents the least weight bit.

In the above formula, what is inside the brackets is the binary code shown on the left expressed in decimal notation.

In the above operation, if the addition result Z is expressed in 6 bits, it becomes 011,010 (13.25), which is the true addition result, but like the inputs X and Y, Z is also expressed in 5 bits. Therefore, it is considered as 11,010 (-0.750). That is, overflow occurs. If the above equation is calculated using the present invention, the following will be obtained.

The bits corresponding to the 5 bits from BB to MSB are named clocks 0, 1, 2, 3 and 4. In terms of time, the clocks change in the order of 0, 1, 2, 3, and 4, and they are repeated. Between clocks 0 and 3, the output bits OFn, sn and d of ROM 3 in FIG. is reading the previous data output. At clock 4, it is detected whether overflow has occurred.

At this time, Zn="1", Zn-,="1", x="0"
, y=“0” and d'=“0” are RO in FIG.
It is input to the input terminals C, D, A, 8 and E of M3, and according to Table 1, OFn="1", sn="0" and d. =“
1'' are given to outputs 30, 31 and 32 of ROM 3, respectively.However, since shift register 2 in FIG. 4 has 4 bits, at clock 4, di is LS of Z.
B, that is, di="0". Next, at clock 0, OFn-, = "1", sn-, = "0" and di
="1" is input, and according to Table 2 OFn="1'',
sn-,=“0” and d. ="1" is output. Similarly, at clock 1, OFn-,="1", during s="
0” and di="0" are input, and according to Table 2, OF
n=“1”, sn=“0” and d. ="1" is output. At the time of clock 2, it is 2 bits before the MSB, so OFn-, = "1", sn-, = "0" and dF
“1” is input, OFn="1", sn according to Table 3
= “1” and d. ="0" is output. At clock 3, OFn-,=“1'', sn-, signal “1” and di=“1” are input, and according to Table 2, OFn=“
1", sn="1" and d.="0" are output. Therefore, di is "1" from clock 4 to clock 3.
, “1”, “1”, “0”, “0” in the order of RO in Figure 4.
It will be applied to the output 32 of M3.

Therefore, the value of input data Z is 00,111 (100.87
5), the overflow is corrected and the terminal 600 in Figure 4 is
is output to. However, the output data is the input data Z
It is output with a delay of 4 bits ((M-1) bits) compared to . Also, as is clear from Tables 1, 2, and 3, when overflow does not occur, dFd.

Therefore, the addition result Z is directly output to the terminal 600 in FIG. 3 with a delay of 4 bits. FIG. 5 is a timing chart for explaining the circuit operation of FIG. 4.

The reference letter a is a timing pulse that indicates the position of the MSB, and the reference letter b is a timing pulse that indicates the position 2 bits before the MSB. Reference letters c, d and e indicate data X, Y and Z in the above example, respectively. Reference letter f is data Z delayed by one bit, and indicates the output 10 of flip-flop 1 in FIG. Reference alphabet g
is the data Z delayed by 4 bits, and shows the output 20 of the shift register 2 in FIG. Reference alphabet h
, i and i are the output 30 of ROM3 in FIG. 4, respectively.
31 and 32 are shown. Reference letter k indicates a clock. As described above, according to the present invention, it is possible to provide an overflow detection and correction circuit with a simple and small circuit hardware scale using a ROM, a flip-flop, and a shift register.

[Brief explanation of the drawing]

Figure 1 shows an example of a conventional overflow detection circuit; Figure 2 shows an example of a conventional overflow detection circuit;
The figure shows an example of a secondary overflow correction circuit, FIG. 3 is a block diagram of a conventional overflow detection and correction circuit that combines FIGS. 1 and 2, and FIG. A block diagram showing one embodiment and FIGS. 5a to 5k are diagrams for explaining the circuit operation of FIG. 4. In Fig. 4, 1, 4, 5... flip-flop, 2
...Shift register, 3...ROM. Hair 3 figures Younger brother 〆 figure 2 Boar 4 figures Pig J figure

Claims (1)

[Claims] 1 Two serial data X and Y to be added, serial data Z_n after addition, serial data Z_n_-_1 obtained by delaying the serial data Z_n by 1 bit, output OF_n_-_1 of the first flip-flop, and output OF_n_-_1 of the second flip-flop. output s_n_-_1 and the serial data X, Y and Z
A first timing pulse indicating the position of the polarity display bit of _n, a second timing pulse indicating the position 2 bits before the polarity display bit, and serial data obtained by delaying the series data Z_n by one data are input. An output OF_n indicating an overflow of the serial data Z_n, an output s_n for correcting the data Z_n when an overflow occurs in the serial data Z_n, and an output d_o representing the content of correcting the overflow of the serial data Z_n. an overflow detection circuit comprising: a read-only memory that generates a digit; the first flip-flop to which the output OF_n of the memory is input; and the second flip-flop to which the output s_n of the memory is input. and correction circuit.