JPH0265527A - Adaptive delta modulation coder - Google Patents

Abstract

PURPOSE:To realize low cost through the elimination of a D/A converter or an A/D converter by obtaining an analog local decoding signal and comparing the signal with an analog input signal at the existing sampling so as to apply coding at the existing sampling. CONSTITUTION:While a gate signal having a pulse width proportional to a step width at the existing sampling based on a past code pattern is generated by a gate signal generating means and inputted to a gate terminal of a 3-state gate buffer, a code at the just preceding sampling is inputted to an input terminal of the 3-state gate buffer. When the code is a code representing it that the analog input signal is larger than a local decode signal, a pulse signal with a high level having a pulse width proportional to the step width is outputted and when the code is a code representing it that the analog input signal is smaller than a local decode signal, a pulse signal with a low level having a pulse width proportional to the step width is outputted. The signal outputted from the 3-state gate buffer is integrated by an analog integration device and a local decoding signal having a level difference proportional to the step width is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to an adaptive delta modulation encoding device for encoding various analog input signals.

<Prior art> When encoding various analog input signals, a pulse signal with a unit time width is input to an integrator, and the locally decoded value is changed by a certain step width according to the value integrated with this pulse signal. There is a delta modulation coding method in which the locally decoded value follows the peak value of the input signal by increasing or decreasing the value.

However, in the above-mentioned delta modulation encoding method, when the peak value of the analog input signal changes rapidly, the decoded waveform cannot sufficiently follow it, and a slope overload occurs.

Therefore, there is an adaptive delta modulation encoding method that adaptively increases or decreases the step width during encoding based on past encoding results.

Conventionally, there is an adaptive delta modulation and coding device as shown in FIG. 4 that implements the above adaptive delta modulation and coding method.

This adaptive delta modulation encoding device, at the time of encoding,
An analog input signal input from an input terminal 101 passes through a low-pass filter 102 to remove aliasing noise. The human horn signal that has passed through the low-pass filter 102 is connected to a coupling capacitor 103. Resistance +04
and a resistor of 1°5. This circuit sets the DC bias of the analog input signal, and outputs the level-set analog input signal X to the signal line 106. Let the peak value of this analog input signal X at the time of the first sampling be Xj. The analog input signal Xt is input to a child terminal of the comparator 108 and compared with the local decoded value i input to one terminal of the comparator 108. As a result, if the analog input signal Xi is greater than the local decoding circuit, the comparator 108
The analog input signal x (
is smaller than the local decoded value i, "0" is output.

The output signal from the comparator 108 is input to the shift register +10, and shifted by the sampling clock signal input from the clock terminal 111. The output signal from each flip-flop of the shift register 110 is input to the local decoding circuit 112. This local decoding circuit I12 is constituted by a digital circuit, and outputs a local decoded value Xt of a digital value as will be described in detail later. The locally decoded value i of this digital value is D
/A converter 109 and converted into an analog value. The converted analog signal is then output to the signal line 107 and input to one terminal of the comparator 108 as described above.

Then, the output signal from the last flip-flop of the shift register 110 is sequentially stored in the storage device 114 as a code.

Further, during decoding, the code stored in the storage device +14 is read out and decoded using the same operation procedure j as that of the local decoding circuits 1 and 2 in the above-described encoding. That is, the code read from the storage device 114 is input to the shift register +15, and the values set in each flip-flop are sequentially shifted based on the sampling clock signal, and the values set in the flip-flops are shifted to the first flip-flop of the shift register +15. Set. The output signal from each flip-flop of shift register 115 is input to local decoding circuit i17. Then, the local decoded value of the digital value output from the local decoding circuit 117 is converted into an analog signal by the D/A converter 118, and the low-pass filter +1
9 and is output to the output terminal 120. Here, the soft register 115 local decoding circuit +17. D/A converter+
18 and low-pass filter +19 are the shift register 1103 local decoding circuit +12. D/
It operates in the same way as the A converter 109 and the low-pass filter +02.

Next, the contents of processing by the local decoding circuits 112 and 117 will be described in detail.

If the peak value of the input signal is X(, the local decoding value is quality, and the encoding code is C(, and the step width is ΔL, then local decoding circuit 1
The processing contents of 12 and 117 are to obtain the value of the step width Δt using the following equation (1), and to calculate the next locally decoded value i++ using the value of this step width Δt.

Δ - "(Δt-1, Ct, Ct-1,"', Ct-T
) −(+)xl≧equity((471), 'i+I
= i+Δtx(<5(C(=0), when +1=
'i-Δt.

Here, the step width Δt expressed by equation (1) is adapted using the following three methods according to Table 1.

Table 1 Exponential companding method shows past code patterns CL-2, Ct-1
This is a method of multiplying p or q obtained based on =Ct by the previous step width Δt-1. Further, the constant method is a method in which a value Ai determined by past code patterns Ct-2, Ct-1=ct is used as the step width ΔL.

Further, in the constant addition method, a constant U is added to the previous step width ΔL-1 based on the past code patterns Ct-2 and CL+Ct.
This is a method of adding or subtracting.

That is, when calculating the local decoding circuit +1 in the above conventional example, after adding the step width Δt obtained as a digital value to the digital local decoding circuit, D/
The A converter 109 converts it into an analog value. In this case, as another method for calculating local decoded values different from the above, there is a method in which an analog input signal is first converted into a digital signal by an A/D converter, and then the subsequent calculation of local decoded values is performed entirely by digital processing. be.

<tsts to be solved by the invention> However, the conventional adaptive delta modulation encoding device described above is mainly configured with digital circuits, and in particular, the local decoding circuit outputs locally decoded values using digital values.
In order to compare this local decoded value and an analog input signal using a comparator, it is necessary to convert the local decoded value, which is a digital value, to an analog value, or to convert the input signal, which is an analog value, to a digital value. Therefore, there is a problem in that an expensive A/A converter (or A/D converter) is required, resulting in high costs.

Therefore, an object of the present invention is to provide a D/A converter (or
An object of the present invention is to provide an adaptive delta modulation and coding device that can be realized at low cost by omitting an A/'D converter.

Means for Solving the Problems To achieve the above object, the present invention compares an analog input signal with a locally decoded signal obtained by adaptively changing the step width based on past code patterns. , when the analog input signal is larger than the local decoded signal, outputs either "bi" or "0", while when the analog input signal is smaller than the local decoded signal, the "bi" and "0" codes are output. In an adaptive delta modulation encoding device that encodes an analog input signal by outputting either the other signal of “0”, the pulse width is proportional to the step width at the current sampling time, based on at least a past code pattern. a gate signal generating means for generating a gate signal having a gate signal having three states, a state of outputting two high and low potentials, and a state of high impedance, and having the gate signal inputted to the gate terminal and the gate signal inputted to the input terminal. If the code at the time of direct sampling is one of the above codes, a high potential pulse signal having a pulse width proportional to the step width is output based on the code at the time of the immediately preceding sampling. In the case of the code at the time of sampling or the other code, a 3-state gate buffer outputs a low-potential pulse signal having a pulse width proportional to the step width, and the step width output from the 3-state gate buffer. The present invention is characterized by comprising an analog integrator that integrates a high-potential or low-potential pulse signal having a pulse width proportional to the step width and outputs the locally decoded signal having a level difference proportional to the step width.

Effect> A gate signal having a pulse width proportional to the step width at the current sampling time is created by the gate signal creation means based on the past code pattern. This gate signal is input to the gate terminal of the 3-state gate buffer, while the code at the time of the previous sampling is input to the input terminal of the 3-state gate buffer.

Then, if the code at the time of the previous sampling is either "bi" or "0" indicating that the analog input signal is larger than the locally decoded signal, then the pulse width proportional to the step width is A high potential pulse signal having a high potential is output.

On the other hand, if the code at the time of the previous sampling is the other of the above "bi" or "0", which indicates that the analog input signal is smaller than the locally decoded signal, the pulse width is proportional to the step width. A low potential pulse signal having .

A high potential or low potential pulse signal having a pulse width proportional to the step width output from the three-state gate buffer is input to the analog integrator. Then, the analog integrator integrates the pulse signal and outputs the locally decoded signal having a level difference proportional to the step width.

Therefore, based on the past code pattern of digital values and the code at the previous sampling time,
Locally decoded signals with analog values can be obtained. Then, this locally decoded signal is compared with the input analog input signal at the time of the current sampling, and encoding at the time of the current sampling is performed.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

FIG. 1 is a block diagram of an adaptive delta modulation encoding device using a constant method local decoding circuit.

This adaptive delta modulation encoding device, at the time of encoding,
An analog input signal input from an input terminal 201 passes through a low-pass filter 202 to remove aliasing noise, sets a level by a circuit consisting of a coupling capacitor 203, a resistor 204, and a resistor 205, and is output to a signal line 206. . Here, the peak value of the analog input signal output to the signal line 206 at the time of sampling is assumed to be Xj. This analog input signal xt is input to the child terminal of the converter L/-208,
It is compared with the local decoded value i-1 inputted to one terminal of 08. As a result, the analog input signal χt has a locally decoded value of 5−
If the analog input signal Cl is the sampling clock signal CK input from the clock terminal 2+1
I inputs and sets the value set in each flip-flop to the first flip-flop of the shift register 210 after being shifted. Then, the output signal from the last flip-flop of the shift register 230 is stored in the storage device 214 as a code obtained by encoding the input signal.

When calculating the local decoded value i by the constant method, the output signals Ct, Ct-1, and Ct-2 from each flip-flop of the shift register 210 are input to the address line of the ROM (read-only memory) 231. .

The ROM 231 stores the values A, At, Aff, A of the step width ΔL in the constant method shown in Table 1. However, in that case, A + , A t , A 3
, A The value of A4 is multiplied by an appropriate constant, quantized, and converted to an integer value, and the number of consecutive "
B has been written. For example, Al-0,5,A,=
1.0. A,=1.4. In the case of A, = 2.3, multiply by 2 and round off to get A I = I, A t
=2A3=3. Set A to an integer value of =5. and,
A.

In the case of A, one "bi" is stored, in the case of A, two consecutive "bis" are stored, in the case of A3, three consecutive "bis" are stored, and in the case of A4. is 5 consecutive “
B is memorized. Then, the output signal Ai of ROM23+
If ° is 8 bits, ``two legs A + , A t
, A s , corresponding to A 4, AI”-”100
ooooo", At'="l 1000000", A3
-I 1100000', A, °="11111000
” is output.

From the ROM 231 as described above, the first
As shown in the table, (Ct, C(-4, Ct-2) = (0
, 0, 0), output signal A4° is output, and in the same manner (Ct, Ct-1=Ct-2) = (1, 0,
In case I), the output signal A,° is output. This R.O.
The output signal from M23+ is set in the shift] register 232 according to the set clock CK2 from the terminal 233. Then, in accordance with the shift clock signal CK3 applied to the terminal 234, the value (A, ', A, ', A
, ', A, °) is output.

The output signal ΔL' from this shift register 232 is input to the gate terminal of a three-state gate buffer 235, while the input terminal of this gate buffer 235 is connected to the output signal from the first flip 70 of the shift register 210 (i.e. , code (4) is input. That is,
The gate buffer 235 outputs an output signal yt corresponding to the value of C( to the output line 236 when the output signal Δt° from the shift register 232 is “Bi”, and when the output signal Δt° is “0”, the gate buffer 235 Output line 23 of
6 becomes high impedance, and no output current flows through the output line 236. Therefore, the output signal yt output to the output line 236 becomes a high-potential or low-potential pulse signal having a pulse width corresponding to the value Ai of the step width Δt.

The signal yt is input to an analog integrator 237. Then, the signal yt having a pulse width corresponding to the value A1 of the step width Δt is integrated by the analog integrator 237 to obtain a signal having a level difference corresponding to the value Ai of the step width Δ[. This signal is then output to one terminal of the comparator 208 as a local decoding circuit.

The comparator 208 has a step width Δ input to one terminal.
It is input from the local decoding circuit having a level difference corresponding to the value Ai of t and the input terminal 201 and is passed through the low-pass filter 202.
Analog input signal Q+1 at the next sampling time after passing through
If Xt The clock pulse signal CK supplied to the terminal 211
I is loaded into the first flip-flop of shift register 210. In this way, adaptive delta modulation encoding is performed.

FIG. 2 shows each sampling clock signal CKI.

Set clock signal GK2. Shift block signal CK3
and a timing chart of each signal Ct, Δt', and yt. The pulse width of the output signal Δt' from the shift register 232 is proportional to the value Ai of the step width Δt shown in Table 1, which is determined based on the past code pattern as described above. Therefore, the pulse width of the output signal yt from the gate buffer 235 obtained from the output signal Δt' from the shift register 232 and the code data (4) is proportional to the value Ai of the step width Δt. That is, the output signal yt The level difference between i-1 and i in the local decoded value i obtained by integrating is determined by the pulse width of the output signal Yt (that is, the step width Δ determined by the past code pattern).
(equivalent to the value Ai of t). As a result, if the same sign continues three times in the past, the step value Δ
(is set large and the local decoding properties change greatly,
Thereafter, the step value Δt is similarly set based on the past code pattern, and the local decoding characteristics are changed.

Next, at the time of decoding, the code stored in the storage device 214 at the time of encoding is read out, and the code stored in the storage device 214 at the time of encoding is read out, using a procedure that is exactly the same as the processing procedure performed by the local decoding circuit in the case of encoding described above. Decrypted.

That is, the code read from the storage device 214 is input to the shift register 215, and the code set in each frisive flop is shifted according to the clock signal CKI input from the clock terminal 216. is set to the first frisib flop. The output signals Ct, Ct-1, and Ct-2 from each flip-flop of the shift register 2+5 are stored in the ROM 241.
is input to the address line of This ROM241 has Ai
' is stored, and a value of Ai' is output according to the values of the signals Ct, Ct-t, and Ct-2 input to the address lines.

The output signal (8 bits in this embodiment) from the ROM 24+ is set bit by bit in each corresponding flip-flop of the shift register 242 in accordance with the set clock signal CK2 from the clock terminal 243. Then, the shift clock signal C from the clock terminal 244
It is softed to the left according to K3, and the shift register 24
The output signal Δt' from 2 is input to the gate terminal of a 3-state gate buffer 245. On the other hand, the input terminal of the gate buffer 245 receives the output signal from the first flip-flop of the soft register 215 (i.e., code C
1) is input. Then, the gate buffer 245
outputs a signal yt corresponding to the value of C() to the output line 246 only when the output signal ΔL′ from the shift register 242 is “B”. Therefore, the output signal yt has a step width Δ
It has a pulse width corresponding to the value Ai of t.

The value Ai of the step width Δt output to the output line 246
A signal yL having a pulse width corresponding to yL is input to an analog integrator 247 and integrated. Therefore, the level difference between the correction -1 and the quality in the local decoded signal i output from the analog integrator 247 corresponds to the pulse width of the output signal yt (i.e., the value Ai of the step width Δt determined by the past code pattern). ) is a value proportional to That is, the waveform of the output signal from the analog integrator 247 is the same as the waveform of the local decoding circuit shown in FIG. The local decoding circuit output from this analog integrator 247 passes through a low-pass filter 219 and is output as a decoded signal from an output terminal 220.

That is, in the adaptive delta modulation coding device using the constant method of this embodiment, the gate buffer 2 of 3 statuses is used.
The past code patterns c t, c t-+ are represented by digital values by 35,245.

A signal y( having a pulse width that adaptively changes according to C(-2) is generated. Then, by integrating this signal yt by an analog integrator, the past code patterns c t, c t-1, It is possible to output an analog local decoding circuit whose level difference changes according to c t-2.Therefore, without using a D/A converter or an A/D converter, it is possible to output an analog local decoding circuit whose level difference changes according to c t-2. Therefore, it is possible to generate an analog locally decoded signal i whose level difference changes over time.

Next, an adaptive delta modulation encoding device using local decoding circuits using the exponential companding method and the constant addition method will be described.

The above-described local composite circuit of the constant method differs from the local decoding circuit of the exponential companding method and the constant addition method in the following points. That is, in the constant method, the value of the step width Δt is determined by the past code pattern regardless of the value of a single step width Δt1, whereas in the exponential companding method and the constant addition method, The value of the step width Δt is determined by the step width Δt~1 of one building and the past code pattern.

FIG. 3 is a block diagram of an adaptive delta modulation encoding device using local decoding circuits of the exponential companding method and the constant addition method. In this adaptive delta modulation and coding apparatus, a low-pass filter 402. Coupling capacitor 403.
Resistance 404. Resistor 405, comparator 408. Shift register 410° storage device 4I4. shift register 41
5. C7-Bass filter 419. shift register 13
2, gate buffer 435. Analog integrator 437.
Shift register 442. The gate buffer 445 and the analog integrator 447 are the low-pass filter 202 and the coupling capacitor 203 . . . in FIG. 1, respectively. Resistance 204.
Resistance 205. Comparator 208. shift register 21
0. Storage device 214. Shift register 215, low pass filter 219. Shift register 232, gate buffer 235, analog integrator 237 shift register 242
．． They are exactly the same as the gate buffer 245 and the analog integrator 247, and operate in the same manner as described above, so their explanation will be omitted.

The difference between the adaptive delta modulation encoding device of this embodiment and the adaptive delta modulation encoding device of the above embodiment is that the step width Δ(
, registers 438 and 448 are newly added, and the storage contents of ROMs 431 and 441 have been changed. Hereinafter, calculation of the step width ΔE in the exponential companding method and the constant addition method will be described in detail. At this time, since the operation of the local decoding circuit in encoding and the operation of the local decoding circuit in decoding are exactly the same, they will be explained together.

First, in the case of the exponential companding method, the previous step width Δt
, 1 is expressed as follows.

Δt-1=AXα, where 8 constant number α〉■ Then, as an index representing the value of the previous step width Δt-1, the above value is added to the newly added register 43.
8,448, it is possible to know the value of the step width Δt-1 for one moe.

The above ROM431.441 contains the past code pattern C.
t, (4 to 11Ct-2) and the value of the step width Δt obtained based on the value of the above index is stored.

At that time, p (>1) and q (<1) in Table 1
The values of are expressed as p・αn, q・α1, for example, cct,
Δt as in the case ct + Ct-2) = (o, o, o)
When calculating the value of the step width Δt using = Δt-+ x p (see Table 1), Δt=J-I is quantized and converted into an integer value by multiplying it by an appropriate constant, and the number of consecutive "I"s equal to the number of integer values is stored.Similarly, (Ct
, Ct-1, Ct-2) = (1, 0, 1), when calculating the value of the step width Δt by ΔL = Δt-t x q, the value of -i+ is set to Δt = AXα. is multiplied by an appropriate constant, quantized, and converted to an integer value, and consecutive "B's as many as the number of integer values are stored. Also, R
The OMs 431 and 441 store the values of (k+n) and (k-m), which are exponents of α in the step width Δt described above.

Past code patterns Ct and Ct+Ct-2 from shift registers 410 and 415 and the value of k from registers 438 and 448 are input to the address lines of such ROMs 431 and 441. Then, the number of consecutive "bi" corresponding to the value of the step width Δt (which changes adaptively based on the input code pattern and the step width Δt−i of one plane) is output.This ROM 431 .4
The output signal Δt from terminals 433 and 443 is the clock signal GK2 . Shift register 4 by CK5
It is set to 32°442. At the same time, the above (k
+n) or (k-111) value is ROM431.4
41 and clock signal CK2 from terminals 439 and 449, the previous step width Δt-
register 438 as the new value for the index representing the value of i.
,448.

That is, in the adaptive delta modulation encoding device for the exponential companding method of this embodiment, the step width of the previous step represented by k stored in the registers 438 and 448 is determined by the three-status gate buffers 435 and 445. ΔL-
1 and past code patterns ct, ct-t, Ct-2
A signal Q having a pulse width that adaptively changes according to digital data is generated. Then, by integrating this signal y (by the analog integrator 437.447, the past code patterns Ct, Ct-1, Ct-
It is possible to output an analog locally decoded signal i whose level changes according to the step width Δ1-1 between 2 and 1.

Therefore, without using a D/A converter or an A/D converter, the past code pattern and the previous step width Δ1−
It is possible to generate an analog local decoded signal i whose level difference adaptively changes according to the +.

Next, in the case of the constant addition method, the value of the previous step width Δtl is expressed as follows.

Δ1-1=kXu+A However, A, u=constant, and by storing the above value in the registers 438 and 448 as an index representing the value of I to the step width of the previous step, It is possible to know the value of the step width Δt-1.

The above ROM431.441 contains the past code pattern c
The value of step width Δ[ obtained based on t, c t-t, c t-2 and the value of the above-mentioned index is stored.

At that time, the step width Δt is determined by ΔL−Δ1.4+u
When calculating the value of (see Table 1), Δt−ΔL−
1 +u=kXu+A+u=(k+l)u+A The value of When calculating the value of step width Δt by - Δt−i −u, ΔL=(k l)
The value of u+A is multiplied by an appropriate constant, quantized, and converted into an integer value, and 3 consecutive "bis" corresponding to the number of integer values are stored in the ROM43+441. The values of (k+1) and (k-1) are stored.

Past code patterns CL, Ct-1, and Ct-2 from shift registers 410 and 415 and the value of k from registers 438 and 448 are input to the address lines of such ROMs 431 and 441. Then, the step width Δt
(Input code pattern and previous step width Δt-
The number of consecutive beams corresponding to the value of (which adaptively changes based on i) is output. This ROM43
The output signal from 1,441 is sent to shift register 432, 441 by clock signal CK2 from terminal 433,443.
Set to 444. At the same time, based on the input past code pattern and the value of k, the above (k+1)
Alternatively, the (k-1)(1) value is output from the ROMs 431 and 441, and the clock signal C from the terminals 439 and 449
K2 causes register 438.44 to be set as a new value to the index representing the value of the previous step width Δ1-1.
Set to 8.

That is, in the adaptive delta modulation encoding device using the constant addition method of this embodiment, the step width Δ of the previous step represented by k stored in the registers 438 and 448 is determined by the three-status gate buffers 435 and 445. Tol
A signal yt having a pulse width that adaptively changes according to digital data of and past code patterns ct, Ct-1, and Ct-2 is generated. Then, by integrating this signal yt by analog integrators 437 and 447, an analog A locally decoded signal i can be output. Therefore, without using a D/A converter or an A/D converter, the past code pattern and the previous step width Δt-1 can be
This makes it possible to generate an analog locally decoded signal sound whose level difference changes adaptively depending on the situation.

In the above-mentioned adaptive delta modulation encoding device using the local decoding circuit of the exponential companding method and the constant addition method, the ROM 431, 4
41, the past code pattern and the previous step width Δt
-1, and the information representing the value of the step width ΔL set in advance according to the value is stored as a table, and the past code pattern and the value of the step width Δt-1 of one side are used as an address signal to be stored as an address signal. A gate signal having a pulse width corresponding to the step width Δ() is output based on information representing the step width Δt.However, the present invention is not limited to this.
Each constant in the table and the step width Δ (calculation rule) are stored in the storage unit, and each constant and rule stored in the table is calculated based on the past code pattern and the previous step width Δt1. Accordingly, the step width ΔL may be calculated by a calculator.

<Effects of the Invention> As is clear from the above, the adaptive delta modulation encoding device of the present invention includes a gate signal generating means, a 3-state gate buffer, and an analog integrator, and uses the present code pattern based on the past code pattern. A gate signal having a pulse width proportional to the step width at the time of sampling is created, and based on this gate signal and the sign at the time of the previous sampling, if the analog input signal at the time of the previous sampling is larger than the locally decoded signal, generates a high-potential pulse signal with a pulse width proportional to the step width at the current sampling time, while if the analog input signal at the previous sampling time is smaller than the local decoded signal, the step width at the current sampling time By generating a low-potential pulse signal with a pulse width proportional to , and integrating this pulse signal, a locally decoded signal having a level difference proportional to the step width is generated. An analog locally decoded signal can be obtained based on a digital signal such as the gate signal of the gate buffer. Therefore, D/A
Without using a converter (or A/D converter), an analog locally decoded signal that can be directly compared with the analog input signal can be obtained, and costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an adaptive delta modulation and coding device in one embodiment of the present invention, FIG. 2 is a timing chart of each output signal in the above embodiment, and FIG. 3 is an adaptive delta modulation and coding device in another embodiment. A block diagram of the device, FIG. 4 is a block diagram of a conventional example. 201.401...Input terminal, 202.219,402,419...Low pass filter, 203.403...Cub pulling capacitor, 2
04.205, 404.405...Resistance, 208.4
08...Comparator, 210.215,410,415...Shift register, 214.414...Storage device, 220.420...Output terminal, 231.241,431,441...ROM. 232.242,432,44.2...Shift register, 235.245,435,445...Gate buffer, 237.247,437,447...Analog integrator, 438.448...Register.

Claims (1)

[Claims] (1) Compare the local decoded signal obtained by adaptively changing the step width based on the past code pattern with the analog input signal, and if the analog input signal is larger than the local decoded signal, “1” ” or “0”, and when the analog input signal is smaller than the locally decoded signal, outputting the other signal of “1” or “0”;
An adaptive delta modulation encoding device for encoding an analog input signal, comprising: gate signal generation means for generating a gate signal having a pulse width proportional to a step width at the current sampling time based on at least a past code pattern; It has three states, a state of outputting two potentials and a state of high impedance, and it also has three states, a state of outputting a single potential and a state of high impedance, and it also has three states: a state of outputting a single potential, and a state of high impedance. If the code at the time of sampling is one of the above codes, a high-potential pulse signal having a pulse width proportional to the step width is output, whereas if the code at the time of the previous sampling is the other code, the step a 3-state gate buffer that outputs a low-potential pulse signal with a pulse width proportional to the step width; and a high-potential or low-potential pulse signal that outputs a low-potential pulse signal with a pulse width proportional to the step width output from the 3-state gate buffer. An adaptive delta modulation encoding device comprising an analog integrator that integrates and outputs the locally decoded signal having a level difference proportional to the step width.