JPS6096003A - Digital fm modulation circuit - Google Patents

Abstract

PURPOSE:To form a digital FM modulation signal without using an ROM and deteriorating the S/N by using a comparator circuit comparing an output data of a digital integration circuit while using a phase data of a sinusoidal wave as a reference value and an encoder. CONSTITUTION:An output data word of a digital integration circuit 5 with an output signal of 1 word N-bit is fed to 2N-1 sets of digital comparator circuits 8(1)-8(2N-1). Data words R(1), R(2)-R(2N-1) representing 2N-1 sets of levels, e.g., increased linearly and sequentially are fed to the other input terminal of the comparator circuit as reference values respectively. The comparison output is ''1'' or ''0'' depending on the difference between the reference value and the integration output data in each comparator circuit. Thus, the level of the integration output data, i.e., the phase position of a sinusoidal wave is represented by the comparison output. Then 225 sets of outputs of each comparator circuit are fed to an encoder 9. The level of the sinusoidal wave at the phase position represented by the comparison output is encoded from the comparison output at the encoder 9.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION This invention relates to a digital FM modulation circuit that converts a digital human input signal into an FM modulation signal.

BACKGROUND ART AND PROBLEMS There is a conventional digital FM modulation circuit as shown in FIG. 1 as an example. That is, this conventional circuit has terminal +1
The analog human input signal through 1 is sent to the A/D controller (2
), for example, one sample (word) is converted into an 8-bit digital signal.

The digital word from the A/D converter circuit (2) is supplied to an adder circuit (3) and added to an 8-bit word of a constant value from the carrier supply circuit (4). This constant value word is for forming a carrier for FM modulation.

The output signal of the adder circuit (3) is sent to the digital integrator circuit (5).
supplied to This digital integration circuit (5) includes an addition circuit (51) and a delay circuit (52) that delays the output of this addition circuit (51) by one word and returns it to this addition circuit (5). ). Therefore, from this integrating circuit (5), a digital signal having a value obtained by cumulatively adding sequentially input data words word by word is obtained.

The output signal of the integrating circuit (5) is supplied as an address input to the ROM (61. This ROM +6) has sine wave data written therein as shown in FIG. 2A. In this case, the 0 phase data is written to address O, and so on, and so on. Each phase of the sine wave is used as an address, and the level value of the sine wave at that phase is written to that address as data. Therefore, this The level values of the sine waveform written at the address specified by the output data from the integrating circuit (5) are sequentially read out from the ROM +61.

For example, if the analog signal passed through the input terminal (1) is a DC signal with a constant level, the A/D converter (2
) always obtains a digital word of the same value, to which a constant value from the carrier supply circuit (4) is added. Therefore, the output data word of the integrating circuit (5) increases in value by 0 to the sum of the value of the input digital word and the constant value.

For example, if the magnitude of ΔD is relatively large, the second
As shown in Figure B, the first value of decoder L' obtained from the integrating circuit (5) is al, the next value is 82, the next is B3, etc. A's IE
Digital signal At of the value marked with a circle in the sinusoidal wave
, A2, A, 3... will be read from this ROM (6). On the other hand, the change ΔD is small,
As shown in Figure 2C, b1+b2+b3. b4...
・If the address changes as shown in Figure 2 A
Level data B1 that does not have an X mark in the sine wave of
．． B2. B3. B4 . . . are sequentially read out from this ROM +6).

The reading timing of this ROM (61) is constant and is the same in the case of FIG. 2B and the case of FIG. 2C, and the timing at which output data is obtained is Like neo-Si, S2 + S3...
・It becomes. Therefore, when the address change ΔD is large as shown in Figure 2B, the output data obtained from ROM +61 converted into an analog signal is a signal with a relatively low frequency as shown in Figure 2B. become. On the other hand, as shown in Fig. 2C, if the change in ΔD of FIR is small, the output data obtained from the ROM (6) converted into an analog signal will not be shown in Fig. 2E. This results in a signal with a relatively low frequency.

As is clear from the above, the frequency of the analog human input signal decreases by one bit in the high-level portions, and the frequency decreases in the low-level portions.
OM (61), which is an FM modulated signal.Here, if the level of the human analog signal is 0, the output of the adder circuit (3) is the carrier supply circuit (4). Since the data is a constant value from f1b, the integral output is data that increases by this constant value.Therefore, ζ, a digital signal from ROM (6) that is a signal with a frequency (carrier frequency) corresponding to this constant f1b is obtained. You will get it.

In this way, a digital FM modulated signal is obtained at the output terminal (7).

By the way, in the case of this conventional digital FM modulation signal, R
OM (The data of the sine wave signal to be written to 61 may be at least +cycles from 0 degrees to 90 degrees of the sine wave input to IA, but even if such a ROM is used, This is a ROM with a comparative angler's capacity, and especially when trying to maintain the S/N of the human signal at a level above, this R
As the number of bits of the OM 161 increases, the size of this ROM occupies most of the size of the circuit, creating a problem when miniaturizing the circuit.

In addition, when this digital FM variable 1fa output (g) is passed through a transmission system with large specific noise, for example when recording and playing on a VTR, the output data of the ROM (6) is 111i bits. This is not necessary, because if noise larger than the minimum bit unit ζ occurs in the transmission system, it will no longer be possible to process the minimum bit unit, and there will be no point in setting such a high bit. be.

In such a case, the number of output bits of the ROM (61) is smaller than the number of bits of the address, for example, the output is 8 bits for 10 bits of the address.

At this time, as shown in FIG. 3, the ROM +61 is in a state where data of the same value is written in a plurality of different addresses. Therefore, the ROM usage rate becomes extremely small.

Purpose of the Invention The present invention aims to provide a digital FM modulation signal that can be formed using a conventional ROM without deteriorating the S/N ratio. .

iIJ of invention! In this invention, instead of using a ROM, each data of the output of the digital integration circuit is compared with a plurality of comparator circuits using the phase data of the sine wave as the standard E, and the difference ζ of the output is A digital FM modulation signal is obtained by detecting a phase position 1g with respect to the wave, encoding the comparison output, and obtaining the sine wave level at that phase position.

Embodiment FIG. 4 is a block diagram of an example of the present invention. In this example, the digital FM modulation 1! to be obtained as an output is shown in FIG. When the number of bits of the +l signal is divided by 1 word N pi 1-, the output data word of the digital integration circuit (5) is 2''-1 at one input terminal of the digital comparison circuits (81) to (82 town 1). supplied to

At the other input terminals of these comparison circuits ts(8x) to (82'-1), 2'-1111+
Data words Rt, Rz . . . R2 indicating a level of 1
”-i are each supplied as a reference value. In this case,
The number of bits of the output data word of the integrating circuit (5) and the number of bits of the reference data words R1, R2 . . . R2-1 are assumed to be the same.

For example, the integral output is 10 bits and the encoder output is 8 bits.
In the case of bits, the number of digital comparison circuits is 25541.
&I, the standard value is 255 levels (25 including 0 level)
6 level). When that value is expressed in 10bih, the minimum level is "4" in decimal and the maximum level is r.
' 225 standards fII) to be 1023J)
[Rx (=I'4J), R2, Ra...
R255 (= 1-1023J) is determined (5th
(see figure).

Note that these reference values R1, R2,...R255 are as follows:
As shown in FIG. 5, this corresponds to each phase of one period of a sine wave.

In the comparison circuits (81) to (8255), the output data word from the integrating circuit is compared with the respective reference value, and when the integrated output data is larger than the reference value, the comparison output is smaller, for example by 11''. It becomes "0" when Therefore, this comparison output represents the magnitude difference of the integral output data, that is, the phase position of the sine wave shown in FIG.

These 225 comparison circuits (81) to (825
Each output of 5) is supplied to an encoder (9).

In this encoder (9), from these 255 comparison outputs, the level value of the sine wave at the phase position represented by the comparison output is encoded in 8 bits.

This encoder (9) can be realized by a logic circuit.

From the above, in this encoder (9), the phase of the sine wave is specified by the integral output, just as the address of ROM (61) is specified by the integral output in the example of FIG. Since the sine wave level of the specified phase is encoded and obtained, a digital FM modulation signal of N bits - 8 bits I can be obtained from this encoder (9) as explained in Fig. 2. .

In this case, the ROM of the example shown in Fig. 1 has a lot of waste as shown in Fig. 3 when the number of °ζζ output data bits is lower than the number of input address bits, and the lJ circuit also becomes large. However, in the above case, the number of digital comparison circuits is determined by the number of output bits N, so it can be used effectively, and when the number of output bits is lower than the number of input bits, the number of digital comparison circuits is determined by the number of output bits N. Since the number of circuits depends on the number of output bits N, the circuit scale can be significantly reduced compared to the case where the number of circuits is provided for the number of input bits, resulting in a smaller size.

The above example is an example in which one period of the sine wave is encoded by the encoder (9), but paying attention to the symmetry of the sine wave, for example, ten periods may be encoded.

That is, FIG. 6 is an example of such a case. In this example, the output signal of the integrating circuit (5) is supplied to one input terminal of the exclusive or cache 1-QOI, and the carry bit CA from the integrating circuit (5) is This signal is supplied to the other input terminal of the exclusive OR gate 00). For example, if the output of the integrating circuit (5) is i-bit, the output is as shown by the solid line in Figure 7A [00...
・0] to (11...l) repeatedly,
4) The i+1th bit carry bit CA (FIG. 7B) becomes a signal whose state is inverted every repetition period. Therefore, this exclusive sob-or-gate (
10) When the signal %cA becomes 11'', a signal is obtained in which r OJ and 1'' are inverted. Then, when the number of output bits of the encoder (11) is M, the output from this OR gate α0) is connected to 2H-1 comparator circuits (8z
) (82)... In (8'2"-1), the phase corresponding to the sine wave from 0° to 180° is based on V
It is compared with the reference data Rs + R2...R6-1, which is the $ value, and from the comparison output, the level value of the phase corresponding to the sine wave's 0'-180° four-color output is determined by M bits in the encoder (11). This encoded value is taken out as an output and added to each bit of the signal C in addition to the °ζζ signal in an adder circuit (12). Therefore, the encoder (11) is obtained in a normal state as shown by the solid line in Figure 7C (however, this is shown as an analog level), but from the adder circuit (12)
In the period in which the signal CA is 11'', the polarity is inverted as shown by the broken line neo. Therefore, the number of bits of the data output obtained from the addition circuit 11'8 (12) is (M+1) bits.

In addition, the 2'-1 (lfIl) comparison circuit that compares the phase of ten cycles from 0° to 90° of the sine wave with respect to one repeated output of the integral value of the integrating circuit (5), and the A Konin coder is provided which converts the level value for 10 cycles according to the output, and using these and the MSB and carry focus of the output of the integrating circuit (5), the same result as in the case of one cycle of sine wave is provided. It can also take action.

Effects of the Invention As described above, according to the present invention, a digital comparator circuit and an encoder are used instead of using a ROM. This has the effect of reducing the circuit scale.

[Brief explanation of drawings]

Fig. 1 is a Bobronok diagram of a conventional example of a digital FM modulation circuit, Fig. 2 is a diagram for explaining digital FM modulation, Fig. 3 is a diagram for explaining the conventional example of Fig. 1, and Fig. 4 is a diagram for explaining the conventional example of Fig. 1. 5 is a block diagram of an example of the present invention, FIG. 5 is a diagram for explaining the same, FIG. 6 is a block diagram of another example of the present invention, and FIG. 7 is a diagram for explaining the same. (5) is the integral time 1, (81) (8'2) ~ (82N
-1) - Digital ratio 'Vt times 1 case, (9) and (11)
is an encoder. Figure 2 Figure 4 Figure 5

Claims (1)

[Claims] A digital integration circuit that integrates a digital input signal in units of data words, a plurality of digital comparison circuits that compare the integrated output with reference values corresponding to each phase of a trigonometric function wave given in advance, and A digital FM modulation circuit comprising an encoder that encodes digital data corresponding to the level value of the phase of the trigonometric function wave as phase information.