JPS61122581U - - Google Patents
Info
- Publication number
- JPS61122581U JPS61122581U JP487785U JP487785U JPS61122581U JP S61122581 U JPS61122581 U JP S61122581U JP 487785 U JP487785 U JP 487785U JP 487785 U JP487785 U JP 487785U JP S61122581 U JPS61122581 U JP S61122581U
- Authority
- JP
- Japan
- Prior art keywords
- reset
- circuit
- signal
- reset signal
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000004044 response Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図は本考案の一実施例のブロツク回路図、
第２図は第１図においてｎ＝２，ｍ＝２のときの
一例、第３図は第２図の回路のタイミング・チヤ
ートである。
図において、ＦＦ１，ＦＦ２…ＦＦｎ…フリツ
プ・フロツプ、ＰＬＡ…プログラマブル・ロジツ
ク・アレイ、ＣＬＯＣＫ…クロツク信号、ＲＥＳ
ＥＴ ＩＮ…リセツト入力信号、ＲＥＳＥＴ０，
ＲＥＳＥＴ、…ＲＥＳＥＴｍ…リセツト出力信号
、ＲＥＳＥＴ…通常時のリセツト出力信号、ＴＥ
ＳＴ ＲＥＳＥＴ…試験用リセツト出力信号、で
ある。
FIG. 1 is a block circuit diagram of an embodiment of the present invention.
FIG. 2 is an example when n=2 and m=2 in FIG. 1, and FIG. 3 is a timing chart of the circuit in FIG. 2. In the figure, FF1 , FF2 ...FFn...Flip-flop, PLA...Programmable logic array, CLOCK...Clock signal, RES
ET IN...Reset input signal, RESET 0 ,
RESET,...RESETm...Reset output signal, RESET...Normal reset output signal, TE
ST RESET...Test reset output signal.
Claims (1)
セツト信号を発生するデイジタル回路の試験用リ
セツト回路において、前記クロツク信号に同期し
て前記リセツト信号を記憶する記憶回路と、前記
リセツト信号と前記記憶回路の出力信号との信号
パターンに応答して前記試験用リセツト信号を含
む２以上のリセツト信号を発生する論理回路とを
含むことを特徴とするデイジタル回路の試験用リ
セツト回路。 A test reset circuit for a digital circuit that receives a clock signal and a reset signal and generates a test reset signal includes a memory circuit that stores the reset signal in synchronization with the clock signal, and an output of the reset signal and the memory circuit. 1. A test reset circuit for a digital circuit, comprising a logic circuit that generates two or more reset signals including the test reset signal in response to a signal pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985004877U JPH0733179Y2 (en) | 1985-01-18 | 1985-01-18 | Reset circuit for digital circuit test |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985004877U JPH0733179Y2 (en) | 1985-01-18 | 1985-01-18 | Reset circuit for digital circuit test |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61122581U true JPS61122581U (en) | 1986-08-01 |
| JPH0733179Y2 JPH0733179Y2 (en) | 1995-07-31 |
Family
ID=30480872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985004877U Expired - Lifetime JPH0733179Y2 (en) | 1985-01-18 | 1985-01-18 | Reset circuit for digital circuit test |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0733179Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57197480A (en) * | 1981-05-29 | 1982-12-03 | Seiko Instr & Electronics Ltd | Test circuit for integrated circuit |
-
1985
- 1985-01-18 JP JP1985004877U patent/JPH0733179Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57197480A (en) * | 1981-05-29 | 1982-12-03 | Seiko Instr & Electronics Ltd | Test circuit for integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0733179Y2 (en) | 1995-07-31 |
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