JPS6112030A - Pattern forming method using two-layer resist - Google Patents

Pattern forming method using two-layer resist

Info

Publication number
JPS6112030A
JPS6112030A JP13110384A JP13110384A JPS6112030A JP S6112030 A JPS6112030 A JP S6112030A JP 13110384 A JP13110384 A JP 13110384A JP 13110384 A JP13110384 A JP 13110384A JP S6112030 A JPS6112030 A JP S6112030A
Authority
JP
Japan
Prior art keywords
resist
layer
baking
layer resist
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13110384A
Other languages
Japanese (ja)
Inventor
Akitoshi Kumagai
熊谷 明敏
Tsukasa Tada
宰 多田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP13110384A priority Critical patent/JPS6112030A/en
Publication of JPS6112030A publication Critical patent/JPS6112030A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the dissolving speed of the resist polymer of the lower layer as well as to reduce the deterioration in quality of image due to the interaction of a pattern part by a method wherein the thin polymer resist of the upper layer is cooled quickly after baking. CONSTITUTION:The first layer of resist 3 is coated on the surface of the film 2 to be processed on a substrate 1 in sufficient thickness with which the effect of stepping can be neglected. Subsequently, said resist layer is baked at the prescribed temperature for the prescribed period of time. Then, the second layer resist 4 to be used for high resolution patterning is coated on said resist 3. Subsequently, a baking is performed again on the second layer resist 4 under the designated baking conditions, and a resist film is completed. Then, a necessary part is exposed 5 using a suitable light source of exposure. After the second layer resist is developed and the desired pattern in vertical profile is obtained on the first layer resist, a baking is performed again, and the above is immediately cooled quickly to room temperature. As a result, the solubility of the first layer resist is improved, and the range of selectivity of developing solvent is made wider, thereby enabling to control the profile properly.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は高密度半導体集積回路や高周波半導体装置など
の製造において適用される高密度ポジ型レジストの加工
方法に係わり、特にレジスト膜の形成方法に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for processing a high-density positive resist applied in the manufacture of high-density semiconductor integrated circuits, high-frequency semiconductor devices, etc., and particularly relates to a method for forming a resist film. It is something.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体集積回路や高周波半導体装置lこおいて。 For semiconductor integrated circuits and high frequency semiconductor devices.

高密度化が進められており、そのため薄膜の微細加工技
術が極めて重要な要素技術となりている。
Higher densification is progressing, and thin film microfabrication technology has become an extremely important elemental technology.

最小寸法がサブミクロン領域へ縮少されるにつれてアク
ペクト比は大きくならざるを得す、加えてより複雑な段
差構造上で寸法制御を行なわなければならないことは至
難の業といえる。また被加工表面の段差から反射光の干
渉作用や電子ビーム露光における近接効果の問題も考慮
されなければならない。これらの問題点を解決する手段
の−つとしていわゆる多重レジストプロセスが利用され
ている。その骨子は、下部に平滑化のための厚い層を、
上部にパターニング用の薄いレジスト層を設けるもので
あり、いくつかのバリエージ璽ンがあるがここでは二層
構造を念頭において説明する。
As the minimum dimension is reduced to the submicron region, the aspect ratio inevitably increases, and in addition, it is extremely difficult to control the dimensions on a more complicated step structure. In addition, interference effects of light reflected from steps on the surface of the workpiece and proximity effects in electron beam exposure must also be taken into consideration. A so-called multiple resist process is used as one means to solve these problems. Its main feature is a thick layer for smoothing at the bottom,
A thin resist layer for patterning is provided on the top, and although there are several variegation types, the two-layer structure will be explained here.

この方法によれば上層のパターンは垂直なプロファイル
が得られ所期の目的を達成することができるが、引き続
き下層のレジスト層を現像させる際に条件をうまく選ば
ないと残すべきパターン部と現像溶媒の作用によりプロ
ファイルの制御がむつかしく、せりかく上層で得られた
精度を下層で維持できないことがあった。
According to this method, the upper layer pattern has a vertical profile and the desired purpose can be achieved, but if the conditions are not selected carefully when developing the lower resist layer, the pattern portion that should be left and the developing solvent Due to this effect, it was difficult to control the profile, and the accuracy obtained in the upper layer could not be maintained in the lower layer.

〔発明の目的〕[Purpose of the invention]

本発明は上記の問題点を解決するためになされたもので
ありサブミクロン領域の微細加工に対応できる解■性を
備えしかも高密屁であるようなレジストプロセスを提供
せんとするものである。
The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a resist process that is capable of responding to microfabrication in the submicron region and is highly dense.

〔発明の概要〕[Summary of the invention]

以下、この発明を図を参照しながら説明する。 Hereinafter, the present invention will be explained with reference to the drawings.

まず第11図((転)のように基板(1)上の被加工膜
(2)の表面に段差の影響を無視できる程度に充分厚く
第一層のレジスト(3)を塗布する。しかる後、このレ
ジスト層を所定の温度、所定の時間ベーキングする。
First, as shown in FIG. 11 ((roll)), a first layer of resist (3) is applied to the surface of the film to be processed (2) on the substrate (1) with a sufficient thickness so that the effect of the step can be ignored. , this resist layer is baked at a predetermined temperature and for a predetermined time.

次にこのレジスト(3)上に高解隊性バタニーング用の
第二層レジスト(4)を薄く塗布する。この後再び第二
層レジスト(4)に指定されるベーキング条件でベーキ
ングを行ないレジスト膜を完成させる。しかるのち適当
な露光光源を用いて必要な部分を露光β)させる。第1
図ら)は第二層レジストの現数工程を断面で示したもの
であり終了後は第−曖しシスト上に所望のパターンが垂
直プロファイルで得られる。続いてこれを再びベーキン
グし、その後室温まで直ちに急冷する。このことにより
ポリマーレジストの溶解性が高められ第−慢しシストの
溶解性向上に大きく寄与している。従って現数溶媒の選
叡幅も広がりプロファイルの制御が可能である。また、
このベーキングはA二層レジストに゛とって現1象後の
ボストベークの役割を果しており、以後のプロセスにお
けるプロファイル低下を未然に防止していることになる
。以上のように、本発明は二層レジストのパターン形成
に当って第二層レジストの現像、ベーキング後これを急
冷処理して第一層レジストの現像を行なうことを主な構
成要素としている。第1図(e)は完成したレジストパ
ターンの断面を示している。なおこの急冷効果を得るた
めには第二層レジストのボストベーク温度が第一層レジ
ストのガラス転移点よりも高いものでなければならない
Next, a second layer resist (4) for highly disintegrated battanning is thinly applied onto this resist (3). Thereafter, baking is performed again under the baking conditions specified for the second layer resist (4) to complete the resist film. Thereafter, necessary portions are exposed to light β) using an appropriate exposure light source. 1st
Figures 1 and 2) are cross-sectional views of the current process of forming the second layer of resist, after which a desired pattern with a vertical profile can be obtained on the second layer of resist. This is then baked again and then quickly cooled to room temperature. This increases the solubility of the polymer resist and greatly contributes to improving the solubility of permanent cysts. Therefore, the selection range of current solvents can be expanded and the profile can be controlled. Also,
This baking serves as a post-bake for the A two-layer resist after the phenomenon occurs, and prevents profile deterioration in subsequent processes. As described above, the main component of the present invention is to develop and bake the second layer resist and then rapidly cool it to develop the first layer resist in forming a pattern of the two layer resist. FIG. 1(e) shows a cross section of the completed resist pattern. Note that in order to obtain this rapid cooling effect, the post-baking temperature of the second layer resist must be higher than the glass transition point of the first layer resist.

〔発明の効果〕〔Effect of the invention〕

本発明の方法によると二層レジストプロセスにおいて上
層の薄いポリマーレジストをベーキング後急冷させてお
り、このことによって下層レジストポリマーの溶解速度
を向上させている。従って工程時間の短縮比が可能であ
ることはもちろん。
According to the method of the present invention, in a two-layer resist process, the upper thin polymer resist is rapidly cooled after baking, thereby improving the dissolution rate of the lower resist polymer. Therefore, it is of course possible to reduce the process time.

パターン部との相互作用による晴質低下を軽減でき、さ
らには現像溶媒の選択幅が広がるためプロファイルの制
御が行ない易く上層で得られた筒密度の寸法を維持する
ことができ、実際のエツチング保護膜として高い解は性
を期待できる。
It is possible to reduce the deterioration of fineness due to interaction with the pattern area, and furthermore, because the selection range of developing solvents is expanded, it is easy to control the profile, and the dimensions of the cylindrical density obtained in the upper layer can be maintained, and the actual etching protection is achieved. A high solution as a membrane can be expected to have good properties.

なお急冷処理による溶解速度向上の効果はそのポリマー
のガラス転移it以上でベーキングすることによって得
られるものでありここでは第二層のボストベーク温度が
第−鳴しシスト、のガラス転移温度より高くなるように
選んである。
Note that the effect of improving the dissolution rate by rapid cooling treatment is obtained by baking at a temperature higher than the glass transition temperature of the polymer. has been selected.

〔発明の実施例〕[Embodiments of the invention]

シリコン基板上にポリメチルイソプロペニルケトンをス
ピンコーティングにより0.8μm享さに塗布した。続
いテ第二1としてポリメチルメタクリレートをスピンコ
ーティングにより0,3μ厚さに塗布しこの基板を15
0℃で30分間ベーキングした。次いでこのレジスト膜
の所望部分に加速電圧20KVの電子線を15μC/C
カの照射密度で照射した後メチルイノブチルケトンから
成る現像液を用いて上層のレジスト層を現像じた。その
後このレジスト@基板を120℃で30分間ベーキング
し終了後直ちにこのレジスト膜基板を冷却体と接触させ
ることにより瞬時にして室温まで冷却させる。
Polymethyl isopropenyl ketone was applied to a thickness of 0.8 μm on a silicon substrate by spin coating. Subsequently, as the second step, polymethyl methacrylate was applied to a thickness of 0.3μ by spin coating, and this substrate was coated with
Baked at 0°C for 30 minutes. Next, an electron beam with an acceleration voltage of 20 KV was applied to a desired portion of this resist film at 15 μC/C.
After irradiation at an irradiation density of 100.degree. C., the upper resist layer was developed using a developer consisting of methylinobutylketone. Thereafter, this resist@substrate is baked at 120.degree. C. for 30 minutes. Immediately after baking, this resist film substrate is brought into contact with a cooling body to instantly cool it to room temperature.

次にメチルイソブチルケトン、キシレン、およびエチル
ベンゼンから成る現像液を用いて瀉−粕しシスト層を現
像しプロファイルを完成させた。
Next, the sieved cyst layer was developed using a developer consisting of methyl isobutyl ketone, xylene, and ethylbenzene to complete the profile.

なお比較のため第二層レジストを現浬、ボストベーク後
強制冷却することなく放冷した以外は同様のプロセスを
経たサンプルを作製した。
For comparison, a sample was prepared through the same process except that the second layer resist was exposed and cooled without being forced to cool after the post-baking.

本発明方法によるサンプルではレジストの膨潤が少なく
プロファイルが垂直に近<、シかもシリコン基板との密
着性にも侵れた鮮明なレジストパターンが得られること
を確認したが比較例のような従来の一般的手法ではプロ
ファイル制御が充分ではなかった。以上の例でわかる通
り本発明方法によれば先述上た特徴を有し鮮明なるレジ
ストパターン形成が可能さなる。
It was confirmed that with the sample produced by the method of the present invention, a clear resist pattern was obtained with less swelling of the resist and a profile close to vertical, and with poor adhesion to the silicon substrate. Profile control was not sufficient with general methods. As can be seen from the above examples, according to the method of the present invention, it is possible to form a clear resist pattern having the above-mentioned features.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は1本発明の詳細な説明するための断面図である
。 】・・・基板、2・・・被加工面、3・・・第−鳩しシ
スト、4・・・第二署レジスト、5・・・電子ビーム、
X線等の照射線。 代理人弁理士  則 近 憲 佑(ばか1名)第1図 (α)      (め (C)
FIG. 1 is a sectional view for explaining the present invention in detail. ]... Substrate, 2... Processed surface, 3... First pigeon cyst, 4... Second signature resist, 5... Electron beam,
Radiation such as X-rays. Representative Patent Attorney Noriyuki Chika (1 idiot) Figure 1 (α) (Me (C)

Claims (2)

【特許請求の範囲】[Claims] (1)基板上にレジストパターンを形成させる工程にお
いてレジストを上下二層とし、上層のレジストを現像後
これをポストベークし終了後急冷により室温まで冷却し
て続いて下層のレジストを現像することを特徴とする二
層レジストを用いたパターン形成方法。
(1) In the process of forming a resist pattern on a substrate, the resist is formed into two layers, upper and lower, and after developing the upper layer resist, it is post-baked, and then cooled down to room temperature by rapid cooling, and then the lower layer resist is developed. A pattern forming method using a characteristic two-layer resist.
(2)前記、上層レジストのポストベーク温度を下層レ
ジストのガラス転移温度より高くなるように選んだこと
を特徴とする特許請求の範囲第1項記載の二層レジスト
を用いたパターン形成方法。
(2) A pattern forming method using a two-layer resist according to claim 1, characterized in that the post-bake temperature of the upper resist layer is selected to be higher than the glass transition temperature of the lower resist layer.
JP13110384A 1984-06-27 1984-06-27 Pattern forming method using two-layer resist Pending JPS6112030A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13110384A JPS6112030A (en) 1984-06-27 1984-06-27 Pattern forming method using two-layer resist

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13110384A JPS6112030A (en) 1984-06-27 1984-06-27 Pattern forming method using two-layer resist

Publications (1)

Publication Number Publication Date
JPS6112030A true JPS6112030A (en) 1986-01-20

Family

ID=15050045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13110384A Pending JPS6112030A (en) 1984-06-27 1984-06-27 Pattern forming method using two-layer resist

Country Status (1)

Country Link
JP (1) JPS6112030A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5151871A (en) * 1989-06-16 1992-09-29 Tokyo Electron Limited Method for heat-processing semiconductor device and apparatus for the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5151871A (en) * 1989-06-16 1992-09-29 Tokyo Electron Limited Method for heat-processing semiconductor device and apparatus for the same

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