JPH02252231A - Fine pattern forming method - Google Patents
Fine pattern forming methodInfo
- Publication number
- JPH02252231A JPH02252231A JP1075316A JP7531689A JPH02252231A JP H02252231 A JPH02252231 A JP H02252231A JP 1075316 A JP1075316 A JP 1075316A JP 7531689 A JP7531689 A JP 7531689A JP H02252231 A JPH02252231 A JP H02252231A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resist
- electron beam
- pattern
- treating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 27
- 238000010894 electron beam technology Methods 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims description 13
- 229920000620 organic polymer Polymers 0.000 claims description 12
- 230000001678 irradiating effect Effects 0.000 claims description 8
- 230000001133 acceleration Effects 0.000 abstract description 10
- 229920000592 inorganic polymer Polymers 0.000 abstract description 3
- 229920000642 polymer Polymers 0.000 abstract 2
- 239000010408 film Substances 0.000 description 47
- 239000010410 layer Substances 0.000 description 34
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000000609 electron-beam lithography Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 4
- 238000011109 contamination Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 3
- 229920006254 polymer film Polymers 0.000 description 3
- 239000004926 polymethyl methacrylate Substances 0.000 description 3
- NTIZESTWPVYFNL-UHFFFAOYSA-N Methyl isobutyl ketone Chemical compound CC(C)CC(C)=O NTIZESTWPVYFNL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- UIHCLUNTQKBZGK-UHFFFAOYSA-N Methyl isobutyl ketone Natural products CCC(C)C(C)=O UIHCLUNTQKBZGK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920005597 polymer membrane Polymers 0.000 description 1
- -1 polysiloxane Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
Landscapes
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electron Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、荷電ビーム直接描画により、半導体基板上に
高精度微細加工用の任意レジストパターンを形成する微
細パターン形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a fine pattern forming method for forming an arbitrary resist pattern for high precision fine processing on a semiconductor substrate by direct writing with a charged beam.
従来の技術
従来、IC及びLSI等の製造においては、紫外線を用
いたホトリソグラフィーによってパターン形成を行って
いる。近年、LSI素子のパターン寸法の微細化、また
ASICの製造に伜い、電子ビーム直接描画技術を用い
るようになってきている。パターン形成に使用される電
子ビームレジストは一般に、耐ドライエツチ性が悪いた
め、また、電子ビームの基板からの反射による近接効果
によりパターンの解像性が悪くなるため、電子ビームリ
ソグラフィーにおいては多層レジスト法が使用されてい
る。第5図は、電子ビームリソグラフィーにおける多層
レジストプロセスを説明する図である。近接効果をおさ
えるために下層膜51として高分子有機膜を2〜3μm
厚塗布し、中間層52として5i02等の無機膜、ある
いはSOGを0.2μm厚塗布し、上層に電子線レジス
ト53を0.5μm厚塗布する(第5図(a))。2. Description of the Related Art Conventionally, in the manufacture of ICs, LSIs, etc., patterns have been formed by photolithography using ultraviolet rays. In recent years, electron beam direct writing technology has come to be used to miniaturize the pattern dimensions of LSI devices and to manufacture ASICs. Electron beam resists used for pattern formation generally have poor dry etch resistance, and pattern resolution deteriorates due to the proximity effect caused by reflection of the electron beam from the substrate. Therefore, multilayer resist methods are used in electron beam lithography. is used. FIG. 5 is a diagram illustrating a multilayer resist process in electron beam lithography. In order to suppress the proximity effect, a polymeric organic film with a thickness of 2 to 3 μm is used as the lower layer film 51.
An inorganic film such as 5i02 or SOG is applied to a thickness of 0.2 μm as an intermediate layer 52, and an electron beam resist 53 is applied to a thickness of 0.5 μm as an upper layer (FIG. 5(a)).
パターン描画後、現像し、レジストパターンを形成する
(第5図(b))。次に、このレジストパターンをマス
クとして、中間層52のドライエツチングを行い(第5
図(e))、次に中間層をマスクとして下層膜51のド
ライエツチングを行う(第5図(d))。以上のような
多層レジストプロセスを用いることにより、微細なパタ
ーンを高アスペクト比で形成することができる。多層レ
ジスト法のうち、二層レジストは高分子有機膜上に、そ
れとミキシングをおこさない無機レジストまたはシリコ
ン含有レジストを塗布した構造をしており、また、三層
レジストは二層レジストの高分子有機膜とレジストとの
間に無機膜、主に5i02 、または有機ポリシロキサ
ンIIJI(SOG)を形成した構造をしており、どち
らも基板からの電子の反射による近接効果を抑える働き
をしている。しかし、これらの多層レジストでは有機膜
が非常に厚いため、新たな問題点が生じて(る。それは
絶縁膜による電子のチャージアップ効果である。電子が
絶縁膜であるレジスト、有機膜、5i02中に蓄積して
くると、パターンのずれ、バッティングエラー、フィー
ルドのずれ等、パターンを正確に描画することができな
(なってしまう。After drawing the pattern, it is developed to form a resist pattern (FIG. 5(b)). Next, using this resist pattern as a mask, dry etching of the intermediate layer 52 is performed (fifth
5(e)), then dry etching of the lower film 51 is performed using the intermediate layer as a mask (FIG. 5(d)). By using the multilayer resist process as described above, fine patterns can be formed with a high aspect ratio. Among the multilayer resist methods, the two-layer resist has a structure in which an inorganic resist or a silicon-containing resist that does not mix with the organic polymer film is coated on top of the organic polymer film, and the three-layer resist has a structure in which the organic resist is coated with an inorganic resist or a silicon-containing resist that does not mix with the organic polymer film. It has a structure in which an inorganic film, mainly 5i02 or organic polysiloxane IIJI (SOG), is formed between the film and the resist, both of which serve to suppress the proximity effect due to reflection of electrons from the substrate. However, since the organic film in these multilayer resists is extremely thick, a new problem has arisen (that is, the charge-up effect of electrons due to the insulating film. As this accumulates, patterns cannot be accurately drawn due to pattern deviations, batting errors, field deviations, etc.
発明が解決しようとする課題
上記の様に、電子線リソグラフィーにおいては、電子線
レジストの耐ドライエツチ性の低さ、電子による近接効
果等の問題点があり、多層レジストにより解決を図ろう
としている。しかし、多層レジスト法を用いると、レジ
スト等の絶縁膜が厚いため、電子チャージアップ効果が
顕著にあられれてきてパターンの正確な描画が困難にな
ってくる。この多層レジストにおける問題点を解決する
ため、中間層に金属、特に導電率の高い金属薄膜を用い
ている。例えば、SOG、5i02のかわりに、Si、
W、Ae等の金属薄膜を中間層として用いることにより
、チャージアップを防ぎ、正確なパターン描画を行うこ
とができる。しかし、レジストプロセスに金属を用いる
ため、コンタミネーションの問題がある。また、金属を
スパッタ蒸着しなければならないため、プロセスが複雑
、困難となり、パターン形成後の金属のエツチング、金
属の剥離等のプロセス上の問題点、描画においては、金
属薄膜があるため基板からの反射二次電子の減少により
位置合わせが困難になる等の問題点が生じる。Problems to be Solved by the Invention As mentioned above, in electron beam lithography, there are problems such as low dry etch resistance of electron beam resists and proximity effects due to electrons, and attempts are being made to solve them by using multilayer resists. However, when the multilayer resist method is used, since the insulating film such as the resist is thick, the electron charge-up effect becomes noticeable, making it difficult to accurately draw a pattern. In order to solve this problem with multilayer resists, metals, particularly metal thin films with high conductivity, are used for the intermediate layer. For example, instead of SOG, 5i02, Si,
By using a metal thin film such as W or Ae as an intermediate layer, charge-up can be prevented and accurate pattern drawing can be performed. However, since metal is used in the resist process, there is a problem of contamination. In addition, since the metal must be sputter-deposited, the process becomes complicated and difficult, and there are process problems such as etching the metal after pattern formation and peeling off the metal. Problems such as alignment becoming difficult arise due to a decrease in reflected secondary electrons.
また耐ドライエツチ性の高い単層レジストを用いて、電
子ビーム描画を行う場合でも、厚いレジスト中、または
、基板の絶縁膜中に電子が蓄禎されて、チャージアップ
がおこり、パターンのずれ、つなぎ合わせずれ、アライ
メントずれ等、パターンを正確に描画することができな
くなってしまう。そのため、レジスト膜上にAe等の金
属薄膜を形成して、チャージアップを防いでいる。第6
図は、電子ビームリソグラフィーにおける単層レジスト
プロセスを説明する図である。半導体基板1上に耐ドラ
イエツチ性の高い電子ビームレジストロ1を1.5μm
厚塗布し熱処理した後、チャージアップを防止するため
にアルミ薄膜62を100A蒸着する(第6図(a))
。描画後、アルカリ水溶液でアルミ層62を除去しく第
6図(b))、その後現像する(第6図(C))。以上
のようなプロセスを用いることにより、チャージアップ
によるパターンずれの生じない、正確なレジストパター
ンを形成することができる。しかし、金属をスパッタ蒸
着しなければならないため、プロセスが困難、複雑とな
り、また、金属によるコンタミネーション等の問題が生
じ、実用的でない。Furthermore, even when electron beam lithography is performed using a single-layer resist with high dry etch resistance, electrons are accumulated in the thick resist or in the insulating film of the substrate, causing charge-up, resulting in pattern shift and connection. Due to misalignment, misalignment, etc., it becomes impossible to accurately draw the pattern. Therefore, a metal thin film such as Ae is formed on the resist film to prevent charge-up. 6th
The figure is a diagram illustrating a single-layer resist process in electron beam lithography. A 1.5 μm thick electron beam resistor 1 with high dry etch resistance is deposited on the semiconductor substrate 1.
After thick coating and heat treatment, a thin aluminum film 62 of 100A is deposited to prevent charge-up (Fig. 6(a)).
. After drawing, the aluminum layer 62 is removed with an alkaline aqueous solution (FIG. 6(b)), and then developed (FIG. 6(C)). By using the process described above, it is possible to form an accurate resist pattern that does not cause pattern displacement due to charge-up. However, since the metal must be sputter-deposited, the process becomes difficult and complicated, and problems such as metal contamination arise, making it impractical.
本発明者らは、これらの課題を解決するために、金属薄
膜を用いずに、膜表面全面に電子ビーム照射を行い、描
画時のチャージアップを防止する微細パターン形成方法
を完成した。In order to solve these problems, the present inventors completed a fine pattern forming method in which the entire surface of the film is irradiated with an electron beam without using a metal thin film to prevent charge-up during drawing.
課題を解決するための手段
すなわち、本発明は、多層レジスト法を用いて電子ビー
ム直接描画を行う前に、下層である高分子有機膜に低加
速度電子ビーム照射を行う、または、中間層である無機
高分子膜に低加速度電子ビーム照射を行うことによって
、導電率を上げて電子ビーム露光を行い、電子によるチ
ャージアップをな(し、正確な微細パターンを形成する
ことができる方法である。Means for Solving the Problems In other words, the present invention involves applying low-acceleration electron beam irradiation to the underlying polymeric organic film before direct electron beam writing using a multilayer resist method, or by applying low-acceleration electron beam irradiation to the underlying polymeric organic film, or by applying low-acceleration electron beam irradiation to the intermediate layer. This is a method in which an inorganic polymer film is irradiated with a low-acceleration electron beam to increase its conductivity, perform electron beam exposure, and charge up with electrons, thereby forming an accurate fine pattern.
また、単層レジストを用いて、電子ビーム描画を行う前
に、レジスト膜全面に低加速度電子ビームを照射するこ
とによって、レジスト表面の導電率を上げることができ
、描画時のチャージアップを防止し、正確な微細パター
ンを形成することができる。In addition, by irradiating the entire surface of the resist film with a low-acceleration electron beam before performing electron beam writing using a single-layer resist, it is possible to increase the conductivity of the resist surface and prevent charge-up during writing. , accurate fine patterns can be formed.
高分子膜に低加速度で高ドーズ量の電子ビームを照射す
ることによって、高分子膜表面の導電率を上げることが
できる。加速電圧2KV、2000μc / cdの照
射を行うことによって、高分子膜表面のシート抵抗をI
X 108Ω/口以下にすることができる。この高分
子膜を用いることによって、電子ビーム描画時の入射電
子は、導電率の高い膜を伝わっていくので、電子のチャ
ージアップはなくなり、正確な微細パターンを形成する
ことができる。By irradiating a polymer film with a high-dose electron beam at low acceleration, the conductivity of the surface of the polymer film can be increased. By performing irradiation with an accelerating voltage of 2 KV and 2000 μc/cd, the sheet resistance of the polymer membrane surface was
X It can be made less than 108Ω/mouth. By using this polymer film, incident electrons during electron beam writing travel through the highly conductive film, eliminating charge-up of electrons and making it possible to form accurate fine patterns.
作用
本発明は前述したプロセスにより、膜表面の導電率を上
げ、容易にチャージアップのおこらない正確な微細パタ
ーンを形成することができる。特に、電子ビーム照射は
大気中で行うことができるので、インライン化を可能と
し、また、金属層を蒸着する必要がなく、コンタミネー
ションの問題もなく、工程を簡略化することができ、電
子によるチャージアップを防止して、正確な微細パター
ンを形成することができる。従って、本発明を用いるこ
とによって、電子ビーム直接描画を行う時、正確な高解
像度な微細パターン形成に有効に作用する。Operation The present invention can increase the conductivity of the film surface and form an accurate fine pattern that does not easily cause charge-up by using the above-described process. In particular, since electron beam irradiation can be performed in the atmosphere, it can be done in-line, and there is no need to evaporate a metal layer, there is no problem of contamination, and the process can be simplified. Charge-up can be prevented and accurate fine patterns can be formed. Therefore, by using the present invention, when performing electron beam direct writing, it is possible to effectively form accurate, high-resolution fine patterns.
実施例
本発明の一実施例を第1図に示す。半導体基板1(表面
に絶縁膜、導体膜等が形成されているこきが多い)上に
下層膜11として高分子有機膜を2μm厚塗布し、25
0℃、30分間オーブンベーキングを行う。この上から
加速電圧2KV、照射量1000μc / crdで電
子ビーム12を全面−括照射した(第1図(a))。次
に中間層13としてSGOを、さらに電子線レジスト1
4としてPMMA (ポリメチルメタクリレート)を、
それぞれ0.2μm厚、0.5μm厚スピンコードし、
加速電圧20 K V 、 ドーズ量100μc/c−
で電子線露光を行った(第1図(b))。電子ビーム照
射された高分子有機膜は表面から約0.4μm程度変質
し、導電率が高(なっている。従って、M I B K
(メチルイソブヂルケトン)とIPA(イソプロピル
アルコール)の混合液で2分間現像を行ったところ、正
確な微細パターンがあられれた(第1図(C))。この
レジストパターン14Pをマスクとして、中間層SOG
と、下層膜の高分子有機膜をエツチングして、垂直形状
の高アスペクト比の0.25μmラインアンドスペース
の超微細パターンを形成することができた(第1図ω)
)。なお、中間層13は下層膜11のエツチングマスク
となるものであれば、他の絶縁膜でもよいが、エツチン
グ選択比をとる意味でシリコンを含む有機膜が望ましい
。Embodiment An embodiment of the present invention is shown in FIG. A polymeric organic film is applied to a thickness of 2 μm as a lower layer film 11 on a semiconductor substrate 1 (often having an insulating film, a conductive film, etc. formed on the surface), and
Bake in the oven at 0°C for 30 minutes. From above, the entire surface was irradiated with an electron beam 12 at an accelerating voltage of 2 KV and a dose of 1000 μc/crd (FIG. 1(a)). Next, SGO is used as the intermediate layer 13, and then electron beam resist 1 is applied.
PMMA (polymethyl methacrylate) as 4,
0.2 μm thick and 0.5 μm thick spin code, respectively.
Accelerating voltage 20 KV, dose 100μc/c-
Electron beam exposure was performed (FIG. 1(b)). The polymeric organic film irradiated with an electron beam is altered by about 0.4 μm from the surface and has high conductivity. Therefore, M I B K
When development was carried out for 2 minutes with a mixture of (methyl isobutyl ketone) and IPA (isopropyl alcohol), an accurate fine pattern was formed (Fig. 1 (C)). Using this resist pattern 14P as a mask, the intermediate layer SOG
By etching the underlying polymeric organic film, we were able to form a vertical, high aspect ratio, 0.25 μm line-and-space ultra-fine pattern (Fig. 1 ω).
). Note that the intermediate layer 13 may be any other insulating film as long as it serves as an etching mask for the lower film 11, but is preferably an organic film containing silicon in order to obtain an etching selectivity.
以上のように、本実施例によれば、下層高分子有機膜に
低加速度電子ビーム照射した三層レジストを用いて電子
線直接描画を行うと、チャージアップを防止することが
でき、正確な微細パターンを形成することができる。As described above, according to this example, when electron beam direct writing is performed using a three-layer resist in which the lower layer organic polymer film is irradiated with a low-acceleration electron beam, charge-up can be prevented and accurate fine-grained writing can be achieved. A pattern can be formed.
次に本発明の第2の実施例を第2図に示す。半導体基板
1上に下層膜21として高分子有機膜を2μm厚塗布し
、250℃で30分間熱処理し、この上に中間層22と
してSOGを0.2μmμmビスピンコード220℃で
20分間熱処理する。この上から、加速電圧IKV照射
量1000μc / c−で電子ビーム23を全面−括
照射したく第2図(a))。次に、上層電子線レジスト
24としてPMMAレジストを0.5μmμmビスピン
コード200℃、20分間ベーキングした後、加速電圧
20KV、 ドーズ量100 tt c / cor
で電子線露光を行った(第2図(b))。電子ビーム照
射された中間層SGOは、表面から約0.15μm程度
変質し、導電率が高くなっている。従って、MIBKと
IPAの混合液で2分間現像を行ったところ、チャージ
アップによるパターンずれのおこっていない正確な微細
パターンがあられれた(第2図(C))。このレジスト
パターン24Pをマスクとして中間層SOGと、下層膜
の高分子有機膜をエツチングして、垂直形状の高アスペ
クト比の0.25μmラインアンドスペースの超微細パ
ターンを形成することができたく第2図(d))。なお
、中間層22は下層膜21のエツチングマスクとなるも
のであれば、他の絶縁膜でもよいが、エツチング選択比
をとる意味で、シリコンを含む有機膜が望ましい。Next, a second embodiment of the present invention is shown in FIG. A polymeric organic film is coated to a thickness of 2 μm as the lower layer 21 on the semiconductor substrate 1 and heat-treated at 250° C. for 30 minutes, and on top of this, SOG is heat-treated as the intermediate layer 22 at 220° C. with a thickness of 0.2 μm μm. From above, the entire surface is to be irradiated with an electron beam 23 at an acceleration voltage IKV irradiation dose of 1000 .mu.c/c- (FIG. 2(a)). Next, as the upper electron beam resist 24, a PMMA resist was baked with a 0.5 μm μm bispin code at 200° C. for 20 minutes, followed by an acceleration voltage of 20 KV and a dose of 100 ttc/cor.
Electron beam exposure was performed (FIG. 2(b)). The intermediate layer SGO irradiated with the electron beam is altered by about 0.15 μm from the surface, and its conductivity is increased. Therefore, when development was performed for 2 minutes with a mixed solution of MIBK and IPA, an accurate fine pattern was obtained without any pattern shift due to charge-up (FIG. 2(C)). Using this resist pattern 24P as a mask, the intermediate layer SOG and the lower layer organic polymer film are etched to form a vertical, high aspect ratio, 0.25 μm line-and-space ultra-fine pattern. Figure (d)). The intermediate layer 22 may be any other insulating film as long as it serves as an etching mask for the lower film 21, but an organic film containing silicon is preferable in terms of etching selectivity.
以上のように、本実施例によれば、中間層膜に低加速度
電子ビーム照射をした三層レジストを用いて電子線直接
描画を行うと、従来発生していたチャージアップを防止
することができ、正確な1a細パターンを形成すること
ができる。As described above, according to this example, when electron beam direct writing is performed using a three-layer resist in which the interlayer film is irradiated with a low-acceleration electron beam, the charge-up that conventionally occurs can be prevented. , an accurate 1a thin pattern can be formed.
次に本発明の第3の実施例を第3図に示す。半導体基板
1上に下層膜31として高分子有機膜を2μm厚塗布し
、250℃で30分間ベーキングを行う。この上から加
速電圧3 K V 、照射量1000μc / cdで
電子ビーム32を全面−括照射した(第3図(a))。Next, a third embodiment of the present invention is shown in FIG. A polymeric organic film is applied to a thickness of 2 μm as a lower layer film 31 on the semiconductor substrate 1, and baked at 250° C. for 30 minutes. From above, the entire surface was irradiated with an electron beam 32 at an acceleration voltage of 3 KV and a dose of 1000 μc/cd (FIG. 3(a)).
次に、上層電子線レジスト33としてシリコン含有レジ
ストを0.3μm厚塗布し、100℃で2分間ホットプ
レートベーキングした後、加速電圧20KV、 ドーズ
量10μc / corで電子線露光を行った(第3図
(b))。電子ビーム照射された高分子有機膜は、表面
から約0.5μm程度、変質し導電率が高くなっている
。従って専用現像液で60秒間現像を行ったところ、正
確な微細パターンがあられれたく第3図(C))。この
レジストパターン33Pをマス1りとして、下層高分子
有機膜をエツチングして、垂直形状の高アスペクト比の
0,25μmラインアンドスペースの超微細パターンを
形成することができた(第3図(d))。Next, a silicon-containing resist was applied to a thickness of 0.3 μm as the upper electron beam resist 33, and after baking on a hot plate at 100° C. for 2 minutes, electron beam exposure was performed at an acceleration voltage of 20 KV and a dose of 10 μc/cor. Figure (b)). The organic polymer film irradiated with the electron beam is altered in quality by about 0.5 μm from the surface, and its conductivity is increased. Therefore, when the film was developed for 60 seconds using a special developer, an accurate fine pattern was formed (Fig. 3 (C)). Using this resist pattern 33P as a mask, the underlying polymeric organic film was etched to form an ultra-fine vertical pattern with a high aspect ratio of 0.25 μm line and space (Fig. 3(d) )).
以上のように、本実施例によれば、二層レジストの下層
膜に電子ビーム照射を行うことによって、電子線直接描
画時のチャージアップを防止することができ、正確な微
細パターンを形成することができる。As described above, according to this example, by irradiating the lower layer of the two-layer resist with an electron beam, charge-up during electron beam direct writing can be prevented and accurate fine patterns can be formed. I can do it.
次に本発明の第4の実施例を第4図に示す。半導体基板
1上に電子線レジスト41としてAZ1400を1 ;
5 u m厚塗布し、100℃、2分間ホットプレー
トベーキングを行った。この上から加速電圧2 K V
、照射量1000μc/cI+1で電子ビーム42を
全面−括照射した(第4図(a))。Next, a fourth embodiment of the present invention is shown in FIG. AZ1400 is applied as an electron beam resist 41 on the semiconductor substrate 1;
It was coated to a thickness of 5 μm and hot plate baked at 100° C. for 2 minutes. Accelerating voltage 2 KV from above
The entire surface was irradiated with an electron beam 42 at a dose of 1000 μc/cI+1 (FIG. 4(a)).
次に、加速電圧20 K V 、 ドーズ量20 t
t c / caで電子線露光を行った(第4図(b)
)、電子ビーム照射されたレジストは、表面から約0.
2μm程度変質し、導電率が高くなっている。次に、レ
ジストの表面の変質層0.2μmをドライエツチングで
除去した後、有機アルカリ水溶液で現像を行ったところ
、チャージアップによるパターンずれのない、正確な微
細レジストパターンを形成することができた(第4図(
C))。Next, the acceleration voltage was 20 KV and the dose was 20 t.
Electron beam exposure was performed at tc/ca (Fig. 4(b)
), the electron beam irradiated resist is approximately 0.0 mm from the surface.
The quality has changed by about 2 μm, and the conductivity has increased. Next, after removing 0.2 μm of the degraded layer on the surface of the resist by dry etching, development was performed with an organic alkaline aqueous solution, and an accurate fine resist pattern without pattern shift due to charge-up could be formed. (Figure 4 (
C)).
以上のように、本実施例によれば、単層レジストで電子
線直接描画を行う時、レジストの表面に低加速度電子ビ
ーム照射を行うことによってレジスト表面の導電率を上
げ、描画時のチャージアップを防止することができ、正
確な微細レジストパターンを形成することができる。As described above, according to this embodiment, when direct electron beam writing is performed on a single-layer resist, the resist surface is irradiated with a low acceleration electron beam to increase the conductivity of the resist surface and charge up during writing. It is possible to prevent the formation of accurate fine resist patterns.
発明の詳細
な説明したように、本発明によれば、多層レジストの下
層膜として用いられる高分子有機膜、または、多層レジ
ストの中間層として用いられる無機高分子膜、またはレ
ジストに低加速度電子ビーム照射を行うことによって、
電子線直接描画時におこるチャージアップによる、パタ
ーンのずれ、つなぎ合わせずれ、アライメントずれ等を
防止することができ、正確な微細パターンを形成するこ
とができ、超高密度築債回路の製造に大きく寄与するこ
七ができる。As described in detail, according to the present invention, a low-acceleration electron beam is applied to an organic polymer film used as a lower layer film of a multilayer resist, an inorganic polymer film used as an intermediate layer of a multilayer resist, or a resist. By irradiating
It can prevent pattern misalignment, splicing misalignment, misalignment, etc. due to charge-up that occurs during direct electron beam writing, and can form accurate fine patterns, greatly contributing to the production of ultra-high-density bonded circuits. I can do Shikoshichi.
第1図は本発明における第1の実施例の工程断面図、第
2図は同第2の実施例の工程断面図、第3図は同第3の
実施例の工程断面図、第4図は同第4の実施例の工程断
面図、第5図は従来の多層レジスト法の工程断面図、第
6図は従来の単層レジスト法の工程断面図である。
1・・・・・・半導体基板、11.21・・・・・・下
層膜、13.22・・・・・・中間層、12.23・・
・・・・電子ビーム、14.24・・・・・・電子線レ
ジスト。
代理人の氏名 弁理士 粟野重孝 はか1名第1図
1−−一γ11:イ】ト、コシ;3;る〔、−vl暉
+2−t+ビーム
1J−仲間I
り+−一−f與気艷乙・ン゛スに
+4P−ルじスYハ′ダーツ
24P・−レジスにハ19−ソ
第
図
1’p34
3f−・−下4月莫
33−’ll)轢しジlト
阿−・tl−、!
33p−−レリストノでターン
!1
下層モ奏
53P−−−レジ又Yハ′タ−ノ
第
図
4flll−−−1,じスジ、へ″ターン63− 室)
鳥覧
tp
しじスLバ夕
ンFig. 1 is a process sectional view of the first embodiment of the present invention, Fig. 2 is a process sectional view of the second embodiment, Fig. 3 is a process sectional view of the third embodiment, and Fig. 4 5 is a cross-sectional view of the process of the fourth embodiment, FIG. 5 is a cross-sectional view of the conventional multilayer resist method, and FIG. 6 is a cross-sectional view of the conventional single-layer resist method. 1... Semiconductor substrate, 11.21... Lower layer film, 13.22... Intermediate layer, 12.23...
...Electron beam, 14.24...Electron beam resist. Name of agent Patent attorney Shigetaka Awano 1 person Figure 1 1--1 γ11: I] To, Koshi; 3; +4P-Rujis Y Ha' Darts 24P--Regis Ha19-S Fig. 1'p34 3f---Lower April 33-'ll) Run over the darts -・tl-,! 33p--Turn at Reliston! 1 Lower layer mode play 53P---Register/Y'terno figure 4flll---1, same line, next turn 63-chamber)
Bird view tp Shijisu L baton
Claims (4)
後、電子ビームを一括照射する工程と、上記高分子有機
膜上に無機絶縁膜を形成し熱処理する工程と、上記無機
絶縁膜上に荷電ビーム用レジスト膜を塗布し熱処理する
工程と、上記レジスト膜にパターンを描画し現像する工
程と、上記レジストパターンをマスクとして上記無機絶
縁膜をエッチングする工程と、上記無機絶縁膜パターン
をマスクとして上記高分子有機膜をエッチングする工程
とを備えて成ることを特徴とする微細パターン形成方法
。(1) A process of applying an organic polymer film on a semiconductor substrate and heat-treating it, and then irradiating it with an electron beam all at once; forming an inorganic insulating film on the organic polymer film and heat-treating it; A step of applying a resist film for a charged beam to the surface and heat-treating the resist film, a step of drawing a pattern on the resist film and developing it, a step of etching the inorganic insulating film using the resist pattern as a mask, and a step of etching the inorganic insulating film pattern as a mask. and etching the polymeric organic film.
工程と、上記高分子有機膜上に無機絶縁膜を塗布し熱処
理した後、電子ビームを一括照射する工程と、上記無機
絶縁膜上に荷電ビーム用レジスト膜を塗布し熱処理する
工程と、上記レジスト膜にパターンを描画し現像する工
程と、上記レジストパターンをマスクとして上記無機絶
縁膜をエッチングする工程と、上記無機絶縁膜パターン
をマスクとして上記高分子有機膜をエッチングする工程
とを備えて成ることを特徴とする微細パターン形成方法
。(2) A step of applying an organic polymer film on the semiconductor substrate and heat-treating it; a step of applying an inorganic insulating film on the organic polymer film and heat-treating it; and then irradiating the inorganic insulating film with an electron beam all at once; A step of applying a resist film for a charged beam to the surface and heat-treating the resist film, a step of drawing a pattern on the resist film and developing it, a step of etching the inorganic insulating film using the resist pattern as a mask, and a step of etching the inorganic insulating film pattern as a mask. and etching the polymeric organic film.
後、電子ビームを一括照射する工程と、上記高分子有機
膜上に無機レジスト膜を塗布し熱処理する工程と、上記
レジスト膜にパターンを描画し現像する工程と、上記レ
ジストパターンをマスクとして上記高分子有機膜をエッ
チングする工程とを備えて成ることを特徴とする微細パ
ターン形成方法。(3) After applying a polymeric organic film on a semiconductor substrate and heat-treating it, a step of irradiating it with an electron beam all at once; a step of applying an inorganic resist film on the polymeric organic film and heat-treating it; and a step of applying a pattern to the resist film. A method for forming a fine pattern, comprising the steps of drawing and developing the resist pattern, and etching the organic polymer film using the resist pattern as a mask.
熱処理する工程と、上記レジスト膜全面に低加速度電子
ビームを一括照射する工程と、上記レジスト膜にパター
ンを描画し現像する工程とを備えて成ることを特徴とす
る微細パターン形成方法。(4) A step of applying a charged beam resist film on a semiconductor substrate and heat-treating it, a step of irradiating the entire surface of the resist film with a low-acceleration electron beam, and a step of drawing a pattern on the resist film and developing it. A fine pattern forming method characterized by comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1075316A JPH02252231A (en) | 1989-03-27 | 1989-03-27 | Fine pattern forming method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1075316A JPH02252231A (en) | 1989-03-27 | 1989-03-27 | Fine pattern forming method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02252231A true JPH02252231A (en) | 1990-10-11 |
Family
ID=13572732
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1075316A Pending JPH02252231A (en) | 1989-03-27 | 1989-03-27 | Fine pattern forming method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02252231A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020018280A (en) * | 2000-09-01 | 2002-03-08 | 윤종용 | Method of electron beam lithography by double exposure and fabrication method of photomask using the same |
JP2007335450A (en) * | 2006-06-12 | 2007-12-27 | Renesas Technology Corp | Process for fabricating semiconductor device |
WO2017086196A1 (en) * | 2015-11-18 | 2017-05-26 | Hoya株式会社 | Mask blank having resist layer, method for manufacturing mask blank having resist layer, and method for manufacturing transfer mask |
-
1989
- 1989-03-27 JP JP1075316A patent/JPH02252231A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020018280A (en) * | 2000-09-01 | 2002-03-08 | 윤종용 | Method of electron beam lithography by double exposure and fabrication method of photomask using the same |
JP2007335450A (en) * | 2006-06-12 | 2007-12-27 | Renesas Technology Corp | Process for fabricating semiconductor device |
WO2017086196A1 (en) * | 2015-11-18 | 2017-05-26 | Hoya株式会社 | Mask blank having resist layer, method for manufacturing mask blank having resist layer, and method for manufacturing transfer mask |
JP2017097021A (en) * | 2015-11-18 | 2017-06-01 | Hoya株式会社 | Mask blank with resist layer, method for manufacturing mask blank with resist layer, and method for manufacturing transfer mask |
KR20180083893A (en) * | 2015-11-18 | 2018-07-23 | 호야 가부시키가이샤 | A mask blank having a resist layer, a method of manufacturing a mask blank having a resist layer, and a method of manufacturing a transfer mask |
US10712652B2 (en) | 2015-11-18 | 2020-07-14 | Hoya Corporation | Mask blank having a resist layer, method for manufacturing mask blank having resist layer, and method for manufacturing transfer mask |
TWI710849B (en) * | 2015-11-18 | 2020-11-21 | 日商Hoya股份有限公司 | Mask blank with a resist layer, method of manufacturing a mask blank with a resist layer, and method of manufacturing a transfer mask |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR930000293B1 (en) | Fine pattern forming method | |
JP3355239B2 (en) | Pattern formation method | |
JP2532589B2 (en) | Fine pattern formation method | |
US20070196772A1 (en) | Method for forming fine pattern of semiconductor device | |
JP3242568B2 (en) | Pattern formation method | |
JPH02252231A (en) | Fine pattern forming method | |
JPH02252233A (en) | Fine pattern forming method | |
JPH02251962A (en) | Fine pattern forming material and pattern forming method | |
JPS6239817B2 (en) | ||
JP3118887B2 (en) | Pattern formation method | |
JPH03138922A (en) | Minute-pattern forming method | |
KR100349375B1 (en) | Method for forming contact hole with sequential process of resist flow and scanning of electron beam | |
JP2506952B2 (en) | Fine pattern formation method | |
JPS63254729A (en) | Forming method for resist pattern | |
JPH01118127A (en) | Pattern forming method | |
JPH03283418A (en) | Resist pattern forming method | |
JP2610898B2 (en) | Fine pattern forming method | |
JPH01218021A (en) | Formation of fine pattern | |
JPH10312994A (en) | Manufacture of semiconductor device | |
JP2004200659A (en) | Method for forming fine pattern | |
JPH0272361A (en) | Electron ray resist having two-layered structure | |
JPS63254728A (en) | Forming method for resist pattern | |
JPH0429149A (en) | Pattern forming material and formation of pattern | |
JPH0429311A (en) | Formation of fine pattern | |
KR910007534B1 (en) | Micro-pattern forming method |