JPS61116677A - Testing of circuit - Google Patents

Abstract

PURPOSE:To facilitate the specification of a troubled location regardless of the complication of the circuitry, by dividing the circuit to be tested into a plurality of circuit systems to perform a trouble shooting confined to a circuit portion to which a trouble shooting signal is fed from a signal control section. CONSTITUTION:Signal control sections Y1-Y5 each having NAND gates N1 and N2, an inverter I and an AND gate A are provided at a specified part of a signal transmission path. Then, the level of a TEST1 signal to be inputted the inverter I and the AND gate N1 of the control system Y1 moves to the H level when the test pattern signal is fed to circuit systems D1 and D2 while i moves to the L level when the pattern signal is not. The same is done with the control sections Y3-Y5. The TEST2 and TEST3 signals move to the H level only when a test pattern signal is fed to the respective circuit systems D3, D4 and D5. Thus, the circuit to be tested is separated into several component parts and testing is done separately for each of the component parts.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for testing electrical circuits.

Various circuits are used in electronic devices, and printed circuit board circuits are widely used because they are convenient for assembling electronic devices, and easy to maintain and inspect. . These printed board circuits must be tested to determine whether they perform the intended function after assembly or when a failure occurs.

[Conventional technology]

As a testing method for electric circuits, for example, for printed circuit board circuits, the following methods have been conventionally used.

As shown in Figure 2, one circuit element is placed on the printed board P1.
~4 is mounted on ~ and a lead wire ~L6 is connected to ~ to these circuit elements.

T1. TSL, 'r5, T6 are signal input terminals,
T.B.

``T4'' and ``T7'' are signal output terminals, and G is a gate circuit. The terminals T and T-z are connected outside the printed board P1.

When testing this printed board circuit, signal input terminal T1
A signal is input from the output terminal T4, and it is determined whether the circuit operation is normal or not based on the signal appearing at the output terminal T4.

If the signal appearing at the output terminal T is the expected one, it is determined that the circuit is operating normally, but if the signal appearing at the output terminal T4 is different from the expected one, it is necessary to identify the defective location. There is. - For this reason, if the signal transmission path between input and output terminals is complex and circuit elements are arranged in multiple stages, this transmission path should be cut at an appropriate point (for example, connecting output terminal T3 and input terminal T2). Cut the lead wire (not shown).) Take out the signal input from the input terminal T-L from the output terminal T4, judge whether it is the expected signal or not, and if it is the expected signal, connect the input terminal T2 and the output terminal T. It is determined that the circuit operation between them is normal, and then the input terminal T1 and the cut point are tested in the same way.

[Problem that the invention seeks to solve]

In such conventional testing methods, when the circuit configuration is complex and there are a lot of connecting wires connecting each circuit element, it is not easy to cut the connecting wires and the effort is large, so it is difficult to efficiently test the circuit. is difficult to do.

SUMMARY OF THE INVENTION An object of the present invention is to provide an electric circuit testing method that allows easy identification of a failure location even if the circuit configuration is complex.

[Means for solving problems]

The present invention provides a simple electric circuit testing method that solves the above problems, and includes circuit elements electrically connected by a signal transmission path. In an electric circuit, a control signal is received at a predetermined portion of the signal transmission path, the signal propagating through the signal transmission path is cut off, and a failure diagnosis signal sent from a separately provided failure diagnosis signal transmission path is transmitted to the next stage circuit. This is accomplished by a circuit testing method characterized in that a signal control unit is provided to input signals to the elements, and the failure diagnosis is performed only in the circuit portion to which the failure diagnosis signal is supplied.

[For production]

The above electric circuit testing method receives a control signal at a predetermined part of the signal transmission path, blocks the signal propagating through this signal transmission path, and transmits the test mode signal to the next stage from the signal transmission path provided for test mode signal transmission. A test signal control unit is provided that allows input to the circuit elements in the next stage, and only the circuit portion including the next stage circuit element is tested using the test signal.

In other words, the circuit to be tested is divided into several component parts, and each component can be tested individually, making it easier to identify the faulty part of a circuit with a complex configuration.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a configuration diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 2 are given the same reference numerals.

Yl includes a Kayuto signal control circuit, A-VC, a NAND gate Nl, an N2 inverter I, and an AND gate A.

T input to inverter I and NAND gate N1
The level of the ESTI signal is determined by connecting the test pattern signal to circuit system D.
1. When supplying to DI, H (high) level signal 2
1-circuit system D1. When no test pattern signal is supplied to Dz, the signal is at L (low) level.

The other test signal control units Y3 to Y5 have similar configurations, and the TEST2 and TEST3 signals become H-level signals only when supplying test pattern signals to the circuit systems D3, D4, and D5, respectively. .

Next, the operation of this circuit will be explained.

Input terminal T1' and output terminal T4. The case of testing the circuit between '' will be explained.

A test pattern signal is inputted from the input terminal T1', and the signal appearing at the output terminal -' is inspected. This output terminal T4
If the signal appearing at the output terminal T4' is the expected one, it is determined that the circuit operation between the input terminal T and the output terminal T is normal; however, if the signal appearing at the output terminal T4' is different from the expected one, The circuit system D1 is tested by setting the TESTI signal to 1 level.

Since the output of inverter ■ is at L level, NAND gate N
-1 output is L level while the TESTI signal is H level (test period), and the output signal of circuit system D□' is AND
Input to gate A is inhibited.

On the other hand, one input terminal of AND gate A is connected during the test period.
Since an H level signal is input, a signal with the polarity of the test pattern signal input from the other input terminal inverted is output from the AND gate A.

Therefore, at the output terminal of the AND game 1-A, a signal ``Ryo shita cho shita'', which is the polarity of the test pattern signal reversed, appears. Since this signal TEST is input to the circuit system D1, the signal appearing at the output terminal T+' is observed, and if it is as expected, it is determined that the operation of the circuit system D1 is normal, and the cause of the failure is the circuit system D1. It turns out that there is □′.

Moreover, output terminal T4. If the signal appearing at T4' is not the expected one, it is determined that the cause of the failure is in the circuit system D1, and the circuit system D1 is repaired so that the expected signal appears at the output terminal T4'.

After that, the test pattern signal is inputted to the input terminal T1' again, and if the signal appearing at the output terminal T4' is the expected one, it is determined that the circuit system D1 is at fault and the circuit system D' is operating normally. If the signal appearing at the output terminal T4' is not the expected one, it is determined that the circuit system D1' is also at fault, and repair is performed.

Similarly for other circuit systems, their constituent circuit systems D2~
D5. Separate tests are performed on D2' to D5''' to identify the faulty circuit system.

〔Effect of the invention〕

As explained above, according to the present invention, a circuit can be divided into a plurality of circuit systems and signals for fault diagnosis can be supplied only to the divided circuit systems, making it easy to identify the faulty part of a complex circuit. become.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG. 2 is a diagram illustrating a conventional electric circuit testing method. K1-4=circuit element, Y4-Y5: test signal control section, N1. Nu: NAND gate, ■=inverter, A: AND gate, T□', 'r5'~T8': Signal input terminal, T4', Tq'~T12: : Signal output terminal, D~D5, D1'~ D5': Circuit system.

Claims (1)

[Claims] including circuit elements electrically connected by a signal transmission path,
In an electric circuit, a control signal is received at a predetermined portion of the signal transmission path, the signal propagating through the signal transmission path is cut off, and a failure diagnosis signal sent from a separately provided failure diagnosis signal transmission path is transmitted to the next stage circuit. 1. A circuit testing method, comprising: providing a signal control unit for inputting signals to elements; and performing failure diagnosis only on circuit portions to which the failure diagnosis signal is supplied.