JPS6111658Y2 - - Google Patents

Description

[Detailed explanation of the idea]

The present invention relates to an additional circuit for inspection of digital equipment, and more specifically, it provides redundancy to the digital equipment and detects abnormalities in the digital equipment based on whether an output pattern signal corresponding to a test pattern signal is obtained. This relates to an additional circuit for inspection. BACKGROUND ART In recent years, the degree of integration of integrated circuits (ICs) has improved, and functional requirements for systems have also increased, and circuits and their operations have become more complex. Additionally, along with this, the circuits and functions mounted on a single printed board have become increasingly complex. Conventionally, these printed circuit boards have been tested using dedicated hardware and measuring instruments such as oscilloscopes, and the normal operation of the boards is confirmed manually.If an abnormality is found, the operator uses measuring instruments to troubleshoot the problem. I've been making a diagnosis. However, as circuits have become more complex in recent years, it has become difficult to perform thorough and sophisticated tests using manual testing, and an abnormal amount of manpower has become necessary for fault diagnosis. Therefore, measures have been taken to automatically test and diagnose these printed boards using a general-purpose automatic printed board testing device (hereinafter abbreviated as ATE). Now, when trying to test printed circuit boards using ATE, the problem is the cost of developing the program. The program referred to here is the programming of a test pattern that is input from the ATE to the printed circuit board to be inspected (hereinafter abbreviated as DUT).
In other words, the more complex the DUT's circuits and functions, the longer test patterns are required for complete testing, and the more effort is required to program the test patterns. Furthermore, the actual test time becomes longer, resulting in a disadvantage that the efficiency of the test decreases. To deal with these problems, block the circuit and
It is sufficient to test each block using ATE. Figure 1 is a schematic configuration diagram to explain the test method using ATE.
Input the test pattern TPN to the DUT, and
The ATE reads the output pattern OPN, compares it with the expected normal output pattern, and considers the DUT to be normal if they match. Then, if it does not match, enter the test pattern TPN several times,
Back trace the IC nodes in the DUT from the abnormal output pin to search for the failure location. In this case, the test pattern TPN from ATE
must be programmed so that if there is a failure inside the DUT, the output will always be abnormal.
In other words, as the DUT circuit becomes more complex and the logic levels between inputs and outputs become deeper, such test patterns become extremely long and difficult to create, and fault diagnosis becomes time-consuming. I end up becoming like that. Therefore, for complex circuits with deep logic levels, we divide the circuit into several blocks and test them.
These issues have been addressed. FIG. 2 is a block diagram showing an example of testing a circuit by dividing it into two blocks. In the figure, block BLK ₁ and block BLK ₂ are test pins.
Although they are separated where TPIN is written, they do not necessarily need to be completely separated. First, block BLK ₁ and block BLK ₂ are divided as shown in FIG. 2a, and the test is performed as follows. That is, input the test pattern TPN from ATE to the input IN of the DUT. Input the output of block BLK ₁ from the test pin TPN to the ATE as the intermediate output pattern IOPN and compare it with the normal pattern. Here, of course, the DUT's output OUT
You may also input the output pattern OPN from (ATE) into a part and compare it. Next, set block BLK ₁ and block BLK ₂ to the second
It is divided as shown in Figure b and tested as follows. i.e. from ATE to test pin
Input intermediate input test pattern IITPN to block BLK ₂ via TPIN. Here, of course,
Some test patterns are blocked from the ATE via the input section of the DUT, that is, block BLK ₁ .
You can also input it to BLK ₂ . Input the output pattern OPN from the DUT's output OUT to the ATE and compare it with the normal pattern. Next, we will specifically explain how to block the circuits described above, that is, how to separate the circuits and how to bring out the intermediate test pins that serve as the interface to the ATE. Figure 3 is a block diagram showing one of the conventionally used general methods, in which the output of the TTL IC is high.
This takes advantage of the ability to shorten the output to low level when the output is high. In the figure, BLK ₁ is block 1, BLK ₂ is block 2, TP ₁ and TP ₂ are test terminals (test pins), and IC ₁ is a TTL IC. In such a configuration, first, in the mode shown in FIG. 2a, test terminal TP ₁ is set to high level,
Intermediate test pattern output from test terminal TP ₂
Input to ATE. Next, in the mode shown in Figure 2b, test terminal TP ₁ is set to low level, and IC ₁
Set the output to high level and input the intermediate input test pattern from test terminal TP ₂ . This operation is expressed in the table below.

[Table] However, in such a method,
The signal level is inverted between blocks _BLK1 and _BLK2 . IC ₁ may be damaged because it shorts the high level output of IC ₁ to low level.
Furthermore, if IC ₁ has a high drive capability, ATE may not be able to fully drive IC ₁ 's high level to low level, which may result in unstable operation. A means for eliminating these drawbacks is shown in FIG.
In Figure 4, the same numbers as in Figure 3 indicate corresponding parts, IC ₂ is the second TTL IC that inputs the output of the first TTL IC ₁ , and TP ₃ is the third test terminal (test pin ). In the signal separation circuit with such a configuration, the second
In the mode shown in figure a, the first and second test terminals TP ₁ and TP ₂ are set to "H", and the third test terminal is set to "H".
Input intermediate test pattern output from TP ₃ to ATE. In the mode shown in FIG. 2b, the first test terminal _TP1 is set to "L" and the intermediate input test pattern is inputted from the second test terminal _TP2 . In this case, nothing is input from the third test terminal _TP3 . Although the drawbacks of the circuit shown in FIG. 3 can be solved by such means, the following new drawbacks arise. That is, the number of gates increases from one to two. Also, the number of test pins increases from two to three. These drawbacks are contrary to highly integrated logic printed circuit boards. In view of the above-mentioned points, the present invention was devised in order to eliminate such drawbacks by solving such problems.The purpose of the present invention is to reduce the number of redundant integrated circuits for circuit separation through a simple circuit configuration. It is an object of the present invention to provide an additional circuit for inspection of a digital device, which can reduce the number of test pins and perform tests with stable reproducibility. In order to achieve this purpose, the present invention separates a digital device at an appropriate predetermined distance, divides it into a plurality of blocks, and connects the output end that appears by separating each block to this output end. A tri-state buffer circuit having an input terminal, an output terminal, and a control terminal is inserted between the input terminal after disconnection, and the input terminal of this tri-state buffer circuit is connected to the above-mentioned output terminal, and the output terminal is connected to the above-mentioned input terminal. At each end, a pre-up resistor is connected to the control terminal, a first test terminal is connected between the control terminal and the pull-up resistor, and a second test terminal is connected to the output terminal, and the first test terminal is connected to the output terminal. The test terminal is set to the first level, an output pattern signal is taken out from the second test terminal, the first test terminal is set to the second level, the output of the tri-state buffer circuit is placed in a floating state, and the output pattern signal is set to the second test terminal. A test pattern signal is inputted from the test terminal of the block so that the circuit of each separated block can be inspected. Hereinafter, embodiments of the present invention will be described in detail based on the drawings. First, before describing embodiments, the principle of the present invention will be explained in order to facilitate understanding of the present invention.
Figure 5 is a diagram for explaining the principle of the present invention. As shown in the figure, when a signal is being transmitted from point A to point B, the flow of the signal is turned on and off at point C by an external signal. However, when it is on, it can be confirmed from the outside that the signal at point A is correctly transmitted to point B, and when it is off, it is possible to apply a signal to point B from the outside. In addition, an element that can control the output to high impedance is used as an on/off switch at point C, and the control terminal is equipped with a test pin that can be connected to the outside, and signals can be input and output from the outside at point B. This test pin is used to separate signals in digital circuits. FIG. 6 is a block diagram showing an embodiment of an additional circuit for inspection of a digital device according to the present invention, and only the parts necessary for explanation are shown. In the figure, the IC is a tri-state buffer circuit that has an input terminal, an output terminal, and a control terminal; one example is the Quad
There are GaTes SN74426 etc. And this tri-state buffer circuit IC
A pre-up resistor is connected to the control terminal of the tri-state buffer circuit, and a first test terminal (test pin TP ₁ ) is connected between this control terminal and the pre-up resistor.
Connect the second test terminal (test pin) to the output terminal of the IC.
TP ₂ ) is connected. Here, the tristate (three states) refers to three states: HIGH level, LOW level, and floating state, that is, a state in which the output exhibits high impedance, in other words, a completely disconnected and open state. And this tri-state buffer circuit IC
is inserted between the output terminal that appeared when the block was separated and the input terminal that was connected to this output terminal after the separation, and that input terminal is connected to the block.
BLK ₁ is connected to the output terminal that appears by disconnecting the block, and the output terminal is connected to the output terminal of the block.
It is connected to BLK ₂ , that is, the input end after disconnection that was connected to the output end. Further, the control terminal and output terminal of this tri-state buffer circuit IC are respectively provided with first and second test terminals (test pins TP ₁ and TP ₂ ),
The first test terminal is set to the first level, the output pattern is taken out from the second test terminal, the first test terminal is set to the second level, and the output of the tri-state buffer circuit IC is placed in a floating state. The circuit is configured to input a test pattern signal from the second test terminal to inspect the circuits of each separated block. Next, the operation of the embodiment shown in FIG. 6 will be explained. First, this tri-state buffer circuit IC
is an IC in which the output of the circuit IC is controlled to high impedance by the control terminal test pin _TP1 . Then, in the mode shown in FIG. 2a, the test pin TP ₁ of the control terminal is set to "H", and the intermediate pattern output is inputted to the ATE from the test pin TP ₂ of the output terminal. In addition, in the mode shown in Figure 2b, the test pin _TP1 of the control terminal is set to "L", the output of the tri-state buffer circuit IC is set to high impedance,
Freely blocked via test pin TP ₂ from ATE
Input the intermediate input test pattern to BLK ₂ . In the present invention, each input side pin and each output side pin of the six ICs are commonly connected to each control terminal of these six ICs based on the circuit with the configuration shown in Fig. 6. A 16-pin tri-state buffer circuit IC with a pull-up resistor connected to this common pin, power supply pin, ground pin 15 pin B plus one spare pin.
6 circuits can be checked with one IC and one pre-up resistor. In this way, the number of redundant ICs for circuit separation can be reduced, the number of test pins can also be reduced, and tests with stable reproducibility can be performed. As is clear from the above explanation, the present invention is a simple method that allows checking in a stable state by utilizing the floating state of the tristate buffer without using complicated means. The circuit configuration reduces the number of redundant integrated circuits for circuit isolation, reduces the number of test pins, and enables stable and reproducible tests, making it practical for practical use. The effect is extremely large.

[Brief explanation of the drawing]

1, 2, 3, and 4 are block diagrams showing examples of conventional printed circuit board testing methods and circuit separation methods, and FIG. 5 shows an additional circuit for inspection of digital devices according to the present invention. FIG. 6 is a block diagram for explaining the principle. FIG. 6 is a block diagram showing an embodiment of the present invention. BLK ₁ , BLK ₂ ...Block, IC...Tri-state buffer circuit, TP ₁ , TP ₂ ...Test terminal (test pin).

Claims (1)

[Scope of utility model registration request] The digital device is separated at an appropriate predetermined point and divided into a plurality of blocks, a test pattern signal is input to each block, and an abnormality in the digital device is detected by whether an output pattern signal corresponding to the test pattern signal is obtained. In the additional circuit for inspection, a tri-type circuit has an input terminal, an output terminal, and a control terminal between the output terminal that appeared by disconnecting each block and the input terminal connected to this output terminal after disconnection. A state buffer circuit is inserted, an input terminal of the tristate buffer circuit is connected to the output terminal, an output terminal is connected to the input terminal, and a pre-up resistor is connected to the control terminal, and the control terminal and the pull-up resistor are connected to each other. connecting a first test terminal between them and connecting a second test terminal to the output terminal, setting the first test terminal to a first level and taking out an output pattern signal from the second test terminal; , set the first test terminal to the second level, put the output of the tri-state buffer circuit in a floating state, input the test pattern signal from the second test terminal, and inspect the circuits of the separated blocks. An additional circuit for inspection of a digital device, characterized in that it is capable of performing the following operations.