JPS6111489B2 - - Google Patents

Info

Publication number
JPS6111489B2
JPS6111489B2 JP15863378A JP15863378A JPS6111489B2 JP S6111489 B2 JPS6111489 B2 JP S6111489B2 JP 15863378 A JP15863378 A JP 15863378A JP 15863378 A JP15863378 A JP 15863378A JP S6111489 B2 JPS6111489 B2 JP S6111489B2
Authority
JP
Japan
Prior art keywords
inverter
output
transmission gate
mos transistors
complementary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15863378A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5586225A (en
Inventor
Hiroyuki Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP15863378A priority Critical patent/JPS5586225A/ja
Publication of JPS5586225A publication Critical patent/JPS5586225A/ja
Publication of JPS6111489B2 publication Critical patent/JPS6111489B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/52Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits using field-effect transistors

Landscapes

  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
JP15863378A 1978-12-25 1978-12-25 Binary counter Granted JPS5586225A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15863378A JPS5586225A (en) 1978-12-25 1978-12-25 Binary counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15863378A JPS5586225A (en) 1978-12-25 1978-12-25 Binary counter

Publications (2)

Publication Number Publication Date
JPS5586225A JPS5586225A (en) 1980-06-28
JPS6111489B2 true JPS6111489B2 (enrdf_load_stackoverflow) 1986-04-03

Family

ID=15675966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15863378A Granted JPS5586225A (en) 1978-12-25 1978-12-25 Binary counter

Country Status (1)

Country Link
JP (1) JPS5586225A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03121193U (enrdf_load_stackoverflow) * 1990-03-26 1991-12-11

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03121193U (enrdf_load_stackoverflow) * 1990-03-26 1991-12-11

Also Published As

Publication number Publication date
JPS5586225A (en) 1980-06-28

Similar Documents

Publication Publication Date Title
KR100366636B1 (ko) 전하 펌프 전압 변환기
JPH01265315A (ja) 半導体回路装置
US6633992B1 (en) Generalized pre-charge clock circuit for pulsed domino gates
JP2010161761A (ja) クロックd型フリップ・フロップ回路
JP3144395B2 (ja) ディレイ回路
JPH0151093B2 (enrdf_load_stackoverflow)
US6346841B2 (en) Pulse generator
JPS6111489B2 (enrdf_load_stackoverflow)
JPS589613B2 (ja) カウンタノ パタ−ンケイセイホウホウ
JPS6075121A (ja) フリツプ・フロツプ
JPS63204817A (ja) 論理回路
US20050134342A1 (en) Circuit and method for generating a signal pulse
JP2541244B2 (ja) クロック発生回路
JPS5930340B2 (ja) バイアス電圧発生装置
US20090085624A1 (en) Flip-flop circuit and duty ratio correction circuit using the same
JPH03102911A (ja) クロック信号発生回路
JP2855935B2 (ja) 半導体集積回路
US6266800B1 (en) System and method for eliminating effects of parasitic bipolar transistor action in dynamic logic using setup time determination
JPH0793568B2 (ja) フリップフロップ回路
JPH0320960Y2 (enrdf_load_stackoverflow)
JPS636897Y2 (enrdf_load_stackoverflow)
JPS5917719A (ja) Cmosフリツプフロツプ回路
JP2745697B2 (ja) 半導体集積回路
JP3278597B2 (ja) 遅延回路
KR100432121B1 (ko) 펄스 중심 감지 회로