JPS61108171A - Thin film field effect transistor - Google Patents
Thin film field effect transistorInfo
- Publication number
- JPS61108171A JPS61108171A JP22901584A JP22901584A JPS61108171A JP S61108171 A JPS61108171 A JP S61108171A JP 22901584 A JP22901584 A JP 22901584A JP 22901584 A JP22901584 A JP 22901584A JP S61108171 A JPS61108171 A JP S61108171A
- Authority
- JP
- Japan
- Prior art keywords
- source
- gate
- drain
- deposited
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 10
- 230000005669 field effect Effects 0.000 title claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910017872 a-SiO2 Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は液晶表示装置駆動用トランジスタ等の大面積基
板上で用いられる薄膜電界効果トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a thin film field effect transistor used on a large area substrate such as a transistor for driving a liquid crystal display device.
近年、トランジスタをマトリックスアレイに構成して駆
動装置とした薄型表示装置が注目されている。この表示
方法では、基板上に蓄積容量とスイッチングトランジス
タを接続した画素回路をマトリックス状に構成し、トラ
ンジスタをスイッチング素子として蓄積容量に画像情報
を蓄積しておき、この画像情報をマトリックス上に設け
られた液晶層ＥＬ層又はＥＬ層等のドツト状表示素子で
表示して画像を得ようとするものであゆ、ＣＲＴに比べ
はるかに薄型の表示装置が実現できる。In recent years, thin display devices in which transistors are arranged in a matrix array and used as a driving device have been attracting attention. In this display method, a pixel circuit in which a storage capacitor and a switching transistor are connected on a substrate is configured in a matrix, image information is stored in the storage capacitor using the transistor as a switching element, and this image information is provided on the matrix. This device attempts to obtain images by displaying images using dot-shaped display elements such as a liquid crystal layer (EL layer) or an EL layer, and it is possible to realize a display device that is much thinner than a CRT.
第４図に単位画素回路を示す。トランジスタＱｌ）のゲ
ートをアドレス電圧Ｖ（Ｘｉ）によりスイッチングし、
ソースに接続されたデータ電圧Ｖ（Ｙｊ）を蓄積容量Ｃ
ｓＨに書き込む。ゲートをオフすることにより画像情報
は蓄積容量に保持され、所定のフレーム時間保持される
。この画像電圧によ抄液晶セル峙が駆動され画像情報を
表示する。端子電圧Ｖｃは液ｄ％セルの対向電極の電圧
である。画素回路の動作において、ゲート・ドレイン間
の浮遊容量Ｃｇｄ Ｑ４の存在により、蓄積容量への書
き込み電圧Ｖｓの低下△Ｖｓが生ずる。ゲートのオン電
圧がＶＧ。FIG. 4 shows a unit pixel circuit. The gate of the transistor Ql) is switched by the address voltage V(Xi),
The data voltage V (Yj) connected to the source is stored in the storage capacitor C
Write to sH. By turning off the gate, the image information is held in the storage capacity for a predetermined frame time. This image voltage drives the liquid crystal cell to display image information. The terminal voltage Vc is the voltage at the counter electrode of the liquid d% cell. In the operation of the pixel circuit, the existence of the stray capacitance Cgd Q4 between the gate and drain causes a decrease ΔVs in the write voltage Vs to the storage capacitor. Gate on voltage is VG.
オフ電圧が００ときの△Ｖｓの値は
となり、 ＣｇｄＯ値により変化し１画素回路の駆動条
件が変化し、回路設計を困難にする。The value of ΔVs when the off-voltage is 00 is: It changes depending on the CgdO value, and the driving conditions of one pixel circuit change, making circuit design difficult.
第５図（ａ） 、 （ｂ）に画素回路の平面図を示す。FIGS. 5(a) and 5(b) show plan views of the pixel circuit.
画素回路は、ゲート電極（２］） 、ソース電極（２功
、ドレイン電極（ハ）、アモルファスシリコン−１画素
電極（ハ）により構成されている。第５図（ａ）にこれ
らのパターンが正しく形成している場合を示す。第５図
（ｂ）に、パターンずれが生じゲートとソース・ドレイ
ンのパターンが正しく整合されなかった場合を示す。The pixel circuit is composed of a gate electrode (2), a source electrode (2), a drain electrode (c), and an amorphous silicon pixel electrode (c). Figure 5 (a) shows these patterns correctly. FIG. 5(b) shows a case where a pattern shift occurs and the gate and source/drain patterns are not properly aligned.
第５図（ｂ）の場合には、ゲートとドレインの車なりが
大きいためゲート・ドレイン間の容−：Ｃｇｄが増大し
ている。又、ソース・ドレインがゲート領域よりはみ出
しているため、チャンネル長の減少が生じている。In the case of FIG. 5(b), since the distance between the gate and the drain is large, the capacitance between the gate and the drain: Cgd increases. Furthermore, since the source and drain protrude beyond the gate region, the channel length is reduced.
液晶ディスプレイは、従来のＩＣ，ＬＳＩと異なり大面
積で用いられるため、基板ガラスの熱膨張、マスクパタ
ーンの変換差等のパターン誤差が容易に生ずるだめパタ
ーン合わせがより困難であり第５図缶）のようなパター
ンずれが容易に発生する。Unlike conventional ICs and LSIs, liquid crystal displays are used over a large area, so pattern errors such as thermal expansion of the substrate glass and conversion differences in mask patterns easily occur, making pattern alignment more difficult (see Figure 5). Pattern deviations such as these easily occur.
このようなパターンずれにより、画素容疑への１き込み
電流（トランジスタのＯＮ電流）の減少、ゲート・ドレ
イン間の浮遊容量Ｃｇｄの増大が生じ、回路の駆動条件
を変化させ、正しい回路１作を困難にする。この問題は
１画素回路及びＭ］＾動回路の設計を困難にする。Such pattern misalignment causes a decrease in the current flowing into the pixel (transistor ON current) and an increase in the stray capacitance Cgd between the gate and drain, changing the circuit driving conditions and making it difficult to create the correct circuit. make it difficult This problem makes the design of single pixel circuits and M]^ motion circuits difficult.
本発明は上記の点に鑑み、パターンずれが生じてもトラ
ンジスタのＯＮ電流、ゲート９１７４７間の浮遊容量が
変化しない構造を有する薄膜電界効畷トランジスタを提
供するものである。In view of the above points, the present invention provides a thin film field effect transistor having a structure in which the ON current of the transistor and the stray capacitance between the gates 91747 do not change even if a pattern shift occurs.
ゲート及びソースのドレイン電極の間の位置関係を一定
の形とすることにより、パターンずれを生じてもチャン
ネル長及びソース・ドレイン間の重なりが変化しない構
造の薄膜電界効果トランジスタを得るものである。By making the positional relationship between the gate and source drain electrodes constant, a thin film field effect transistor having a structure in which the channel length and the overlap between the source and drain do not change even if a pattern shift occurs can be obtained.
本発明によれば、パターンずれを生じても、チャンネル
長及びソース・ドレイン間の重なりが変化しないだめ、
回路定数を一定にでき、画素回路及び駆動回路の設計が
容易な薄膜電界効果トランジスタを得るものである。According to the present invention, even if a pattern shift occurs, the channel length and the overlap between the source and drain do not change.
The present invention provides a thin film field effect transistor whose circuit constants can be kept constant and whose pixel circuits and drive circuits can be easily designed.
第１図に本発明の実施例を示す。Ｍｏ１０００Ａをスパ
ッターにより堆積（ゲート（２１）な形成する。FIG. 1 shows an embodiment of the present invention. Mo1000A is deposited by sputtering (gate (21) is formed).
ゲート絶縁膜として５ｉ０２をプラズマＣＶＤで２００
ＯＡ堆積Ｌ、次にアモルファスシリコン（ａ−８ｔ）
及びＰをドープしたｎ形アモルファスシリコン（ｎ＋ａ
−８ｔ ）を−すれぞれａｏｏｏＸ、５ｏｏＸ４ｉす
る。As a gate insulating film, 5i02 was deposited at 200 nm using plasma CVD.
OA deposition L, then amorphous silicon (a-8t)
and P-doped n-type amorphous silicon (n+a
-8t) are aoooX and 5ooX4i, respectively.
アモルファスシリコンｃ２４） ｉ ＣＤＥテエッチン
クシタ後にＭｏを５０ ＯＡ 、 Ａｌを１μｍをスパ
ッター及び蒸着により堆積し、ソース・ドレイン電極を
形成する。ソース・ドレイン電極（２２１、？３をマス
クとじてｎ十ａ−８ｔをエツチングする。第１図のよう
に、ソース及びドレインを同一幅で平行に形成し、ゲー
トを同一幅でソース及びドレインに垂直にパターン形成
することにより、ゲート及びソース−ドレイン′醒極の
たて方向、横方向の２０μｍのずれが生じても同一の’
ｒＰｒ特性が得られた。After amorphous silicon c24) i CDE etching, 50 OA of Mo and 1 μm of Al are deposited by sputtering and evaporation to form source and drain electrodes. Using the source/drain electrodes (221, ?3 as a mask, etching n10a-8t. As shown in Figure 1, the source and drain are formed in parallel with the same width, and the gate is formed with the same width between the source and drain. By forming the pattern vertically, even if the gate and source-drain polarities are shifted by 20 μm in the vertical and lateral directions, the same polarity can be achieved.
rPr characteristics were obtained.
尚、ゲート方向のみにパターンずれが生ずる場合には第
２図に示すようにゲート方向のみにパターン余裕をもた
せた構造とすれば良い。父、ソース方向のみにパターン
ずれが生ずる鳴合には絹３図に示すようにソース方向の
みにパターン余裕をもたせた構造とすれば良い。即ち、
ゲート方向及びソース方向のパターン余裕はそれぞれの
方向の合せ誤差程度の値とすれば良い。Incidentally, if pattern deviation occurs only in the gate direction, a structure may be adopted in which pattern margin is provided only in the gate direction, as shown in FIG. In the case where a pattern deviation occurs only in the source direction, a structure with a pattern margin only in the source direction as shown in Figure 3 may be used. That is,
The pattern margins in the gate direction and the source direction may be set to values approximately equal to alignment errors in each direction.
尚、薄膜トランジスタに用いられる半青体はアモルファ
スシリコンに限定されス、ポリシリコン。Note that the semi-blue bodies used in thin film transistors are limited to amorphous silicon and polysilicon.
ＣｄＳｅ、Ｔｅ等でも良い。又、ゲート絶縁膜はＳ ｉ
０２に限らず、Ｓｉ３Ｎ４．Ｔａ２０５．Ａｌ２Ｏ３で
も良いし、電極はＡｌ、Ｍｏに限らず低い抵抗率の材料
であれば何でも良い。CdSe, Te, etc. may also be used. Also, the gate insulating film is Si
Not limited to Si3N4.02. Ta205. Al2O3 may be used, and the electrode is not limited to Al or Mo, but any material with low resistivity may be used.
第１図は本願発明の第１の実施例を示す図、第２図及び
第３図は第２及び第３の実施例を示す図、第４図及び第
５図は従来例を示す図である。
２１・・・ゲート、２２・・・ソース、２３・・・ドレ
イン、２４・・・アモルファスシリコン。
第１図
第 ２ 図FIG. 1 shows the first embodiment of the present invention, FIGS. 2 and 3 show the second and third embodiments, and FIGS. 4 and 5 show the conventional example. be. 21...gate, 22...source, 23...drain, 24...amorphous silicon. Figure 1 Figure 2
Claims (3)
つ平行に配線されており、ゲート電極が前記ソース電極
及び前記ドレイン電極の長手方向に対して垂直となる方
向に配線されたことを特徴とする薄膜電界効果トランジ
スタ。(1) The source electrode and the drain electrode are wired in parallel and have the same width, and the gate electrode is wired in a direction perpendicular to the longitudinal direction of the source electrode and the drain electrode. Thin film field effect transistor.
きに延びる電極であることを特徴とする特許請求の範囲
第１項記載の薄膜電界効果トランジスタ。(2) The thin film field effect transistor according to claim 1, wherein the source electrode and the drain electrode are electrodes extending in opposite directions.
ト電極を有する半導体はアモルファスシリコンであるこ
とを特徴とする特許請求の範囲第１項記載の薄膜電界効
果トランジスタ。(3) The thin film field effect transistor according to claim 1, wherein the semiconductor having the source electrode, the drain electrode, and the gate electrode is amorphous silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22901584A JPS61108171A (en) | 1984-11-01 | 1984-11-01 | Thin film field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22901584A JPS61108171A (en) | 1984-11-01 | 1984-11-01 | Thin film field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61108171A true JPS61108171A (en) | 1986-05-26 |
Family
ID=16885418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22901584A Pending JPS61108171A (en) | 1984-11-01 | 1984-11-01 | Thin film field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61108171A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62287666A (en) * | 1986-06-03 | 1987-12-14 | ゼネラル・エレクトリツク・カンパニイ | Thin film field effect transistor allowing discrepancy of electrode position |
| JPS6468968A (en) * | 1987-09-09 | 1989-03-15 | Seiko Epson Corp | Thin film transistor |
| EP0333151A2 (en) * | 1988-03-18 | 1989-09-20 | Seiko Epson Corporation | Thin film transistor |
| JPH02275672A (en) * | 1989-03-30 | 1990-11-09 | Nippon Steel Corp | Thin film transistor |
| US6797982B2 (en) | 2000-08-28 | 2004-09-28 | Sharp Kabushiki Kaisha | Active matrix substrate and display device |
| JP2006245557A (en) * | 2005-02-03 | 2006-09-14 | Semiconductor Energy Lab Co Ltd | Semiconductor device, electronic device, and method of manufacturing semiconductor device |
| EP2086011A2 (en) * | 2008-02-04 | 2009-08-05 | Samsung Electronics Co., Ltd. | Thin film transistor and display device having the same |
-
1984
- 1984-11-01 JP JP22901584A patent/JPS61108171A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62287666A (en) * | 1986-06-03 | 1987-12-14 | ゼネラル・エレクトリツク・カンパニイ | Thin film field effect transistor allowing discrepancy of electrode position |
| JPS6468968A (en) * | 1987-09-09 | 1989-03-15 | Seiko Epson Corp | Thin film transistor |
| EP0333151A2 (en) * | 1988-03-18 | 1989-09-20 | Seiko Epson Corporation | Thin film transistor |
| JPH02275672A (en) * | 1989-03-30 | 1990-11-09 | Nippon Steel Corp | Thin film transistor |
| US7126157B2 (en) | 2000-08-28 | 2006-10-24 | Sharp Kabushiki Kaisha | Active matrix substrate, method of making the substrate, and display device |
| US6797982B2 (en) | 2000-08-28 | 2004-09-28 | Sharp Kabushiki Kaisha | Active matrix substrate and display device |
| US7459723B2 (en) | 2000-08-28 | 2008-12-02 | Sharp Kabushiki Kaisha | Active matrix substrate, method of making the substrate, and display device |
| US7696516B2 (en) | 2000-08-28 | 2010-04-13 | Sharp Kabushiki Kaisha | Active matrix substrate, method of making the substrate, and display device |
| US7829391B2 (en) | 2000-08-28 | 2010-11-09 | Sharp Kabushiki Kaisha | Active matrix substrate, method of making the substrate, and display device |
| US8304297B2 (en) | 2000-08-28 | 2012-11-06 | Sharp Kabushiki Kaisha | Active matrix substrate, method of making the substrate, and display device |
| JP2006245557A (en) * | 2005-02-03 | 2006-09-14 | Semiconductor Energy Lab Co Ltd | Semiconductor device, electronic device, and method of manufacturing semiconductor device |
| EP2086011A2 (en) * | 2008-02-04 | 2009-08-05 | Samsung Electronics Co., Ltd. | Thin film transistor and display device having the same |
| EP2086011A3 (en) * | 2008-02-04 | 2010-01-13 | Samsung Electronics Co., Ltd. | Thin film transistor and display device having the same |
| US8179491B2 (en) | 2008-02-04 | 2012-05-15 | Samsung Electronics Co., Ltd. | Thin film transistor having improved fabrication and performance characteristics and display device having the same |
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