JPS61102034A - Method of developing photo-resist - Google Patents

Method of developing photo-resist

Info

Publication number
JPS61102034A
JPS61102034A JP22460584A JP22460584A JPS61102034A JP S61102034 A JPS61102034 A JP S61102034A JP 22460584 A JP22460584 A JP 22460584A JP 22460584 A JP22460584 A JP 22460584A JP S61102034 A JPS61102034 A JP S61102034A
Authority
JP
Japan
Prior art keywords
developer
temperature
semiconductor substrate
nozzle
nozzles
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22460584A
Other languages
Japanese (ja)
Inventor
Hiroaki Tsutsui
宏彰 筒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22460584A priority Critical patent/JPS61102034A/en
Publication of JPS61102034A publication Critical patent/JPS61102034A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Abstract

PURPOSE:To equalize the size of a pattern in a wafer surface by arranging a plurality of nozzles in the radial direction, separately controlling the temperature and quantity of a developer fed from the nozzles and rotatably applying the developer. CONSTITUTION:Several developer dropping nozzles 3 are mounted in the radial direction of a semiconductor substrate 2, and the temperature and flow rate of a developer fed from each nozzle are controlled independently. Accordingly, the developer dropped from respective nozzle flows on the surface of the substrate 2, and is mixed with a novel developer dropped from the next nozzle with a proceeding to the periphery, thus compensating a temperature change, then reducing the width of temperature distribution to one over several of conventional devices, provided that a pattern in uniform size is acquired in a substrate surface.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造工程において、半導体基板
上に、塗布及び選択露光されたフォト・レジストのスプ
レー現像に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to spray development of a photoresist coated and selectively exposed on a semiconductor substrate in a semiconductor device manufacturing process.

〔従来の技術〕[Conventional technology]

従来、フォト・レジストのスピン現像はチャック上に吸
着され回転中の半導体基板表面に上部の滴下ノズルから
現像液が供給されることにより行われてきた。
Conventionally, spin development of photoresist has been carried out by supplying a developing solution from an upper dripping nozzle onto the surface of a rotating semiconductor substrate that is attracted onto a chuck.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながらキノンジアジド系のフォト・レジスト等の
現像のように、現像液温度によって現像速度が著しく変
化するような際には当初の現像液温度と半導体基板の温
度が異なっている場合、基板中央は当初の現像液温度で
現像されるが、中央部に滴下された現像液が周辺部に流
れていくに従−1半導体基板からの熱の伝尋により、現
像液温は、半導体基板の温度に近づいていき、半径方向
に現像速度の変化が生じ結果として基板面内でパターン
寸法のバラツキが生じるという欠点があった。
However, when developing quinonediazide-based photoresists, etc., where the development speed changes significantly depending on the developer temperature, if the initial developer temperature and the semiconductor substrate temperature are different, the center of the substrate will be Development is carried out at the temperature of the developer, but as the developer dropped in the center flows to the periphery, the temperature of the developer approaches the temperature of the semiconductor substrate due to the conduction of heat from the semiconductor substrate. However, there is a drawback that the development speed changes in the radial direction, resulting in variations in pattern dimensions within the substrate surface.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、上記次点を除くために、半導体基板上の半径
方向に滴下ノズルを複数個設け、それぞれが供給する現
像液の温度と量を個々に独立して制御することにより、
半導体基板面内で現像速度が一定になるようにしたもの
である。
In order to eliminate the above-mentioned runner-up problem, the present invention provides a plurality of dripping nozzles in the radial direction on the semiconductor substrate, and independently controls the temperature and amount of the developer supplied by each nozzle.
The development speed is made constant within the plane of the semiconductor substrate.

即ち、本発明による現像方法を用いることにより、半導
体基板面内で均一なパターン寸法が得られるという利点
がある。
That is, by using the developing method according to the present invention, there is an advantage that uniform pattern dimensions can be obtained within the plane of the semiconductor substrate.

〔実施例〕〔Example〕

次に、図面を用いて本発明について説明する、第3図は
従来のスピン現像の方式であり、チャ、り1上に吸着さ
れた半導体基板2の中央上方に現像液供給ノズル3が位
置している。滴下された現像液は半導体基板2のスピン
に従い矢印に沿って外周部へと流れる。このとき現像液
は当初の温度T1から、半導体基板の温度T2に両辺的
に近づいていく。この温度分布をグラフに示したものが
第4図である。これから半導体基板20表面内で現像液
温度は最大I T、−T、lの巾で分布していることに
なり、結果的に中央部と外周部で著しいパターン寸法の
相異が生じる。
Next, the present invention will be explained with reference to the drawings. FIG. 3 shows a conventional spin development method, in which a developer supply nozzle 3 is located above the center of a semiconductor substrate 2 adsorbed on a film 1. ing. The dropped developer flows toward the outer periphery along the arrows according to the spin of the semiconductor substrate 2. At this time, the developing solution approaches the temperature T2 of the semiconductor substrate from the initial temperature T1 on both sides. FIG. 4 is a graph showing this temperature distribution. From this, it can be seen that the developer temperature is distributed within the surface of the semiconductor substrate 20 with a maximum width of IT, -T, l, and as a result, a significant difference in pattern size occurs between the center and the outer periphery.

第1図は本発明の一実施例によるスピン現像の例であり
、従来と異なり現像液滴下ノズル3か半導体基板2の半
径方向に複数個設置されていて、各々のノズルから供給
される現像液については、温度と流量が独iK制御芒れ
ている。各ノズル3から篩下された現像液は矢印に従っ
て半桑体基ぢ2の表面上?流れ、周辺部にいくに従い次
のノズルから滴下された新しい現像液と混合され、温度
変化が桶正嘔れる。このときの温度分布をグラフに示し
たものが第2図であり、従来の方法に比べて分布中は数
分の一程度に押さえることができる。
FIG. 1 shows an example of spin development according to an embodiment of the present invention, in which, unlike the conventional case, a plurality of developer dripping nozzles 3 are installed in the radial direction of the semiconductor substrate 2, and the developer is supplied from each nozzle. As for the temperature and flow rate, the temperature and flow rate are controlled by iK. The developing solution sieved from each nozzle 3 is directed onto the surface of the semicircular substrate 2 according to the arrows. As it flows toward the periphery, it mixes with new developer dripped from the next nozzle, causing a change in temperature. FIG. 2 shows a graph of the temperature distribution at this time, and the temperature distribution can be suppressed to a fraction of that of the conventional method.

〔発明の効果〕〔Effect of the invention〕

このように、本発明によれは、半導体基板面内で均一な
寸法のパターンを得ることができる。
In this way, according to the present invention, a pattern with uniform dimensions can be obtained within the plane of the semiconductor substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例による工程を示す断面図、第
2図は本実施例による温度分布を示すグラフである。第
3囚に従来の例を示す断面図、第4図は従来例による温
度分布を示すグラフである。 1・・・・・・チャ、り、2・・・・・・半導体基板、
3・・・・・・現像液滴下ノズル、T1・・・・・・中
央のノズルの現像液温、T2・・・・・・半導体基板の
温度、r・・・・・・半導体基板の半径 JノZつし 第7図 7!7           r −学尊4札1本(中心・かりt距高1 第Z図 第3図 θ            r −半導林墓扱中1いがt3/)距真配 第4図
FIG. 1 is a sectional view showing a process according to an embodiment of the present invention, and FIG. 2 is a graph showing a temperature distribution according to this embodiment. The third figure is a sectional view showing the conventional example, and FIG. 4 is a graph showing the temperature distribution according to the conventional example. 1...Char, ri, 2...Semiconductor substrate,
3...Developer dripping nozzle, T1...Developer temperature of center nozzle, T2...Temperature of semiconductor substrate, r...Radius of semiconductor substrate J no Z Tsushi Figure 7 7! 7 r - Gakuson 4 note 1 (Center / Kari t distance height 1 Figure Z Figure 3 θ r - Semi-dorin grave handling medium 1 Iga t 3 /) Range Shin Diagram 4

Claims (1)

【特許請求の範囲】[Claims]  スピン現像法における現像液供給ノズルを複数にし、
半径方向に配置し、それぞれのノズルから供給される現
像液の温度と量を個々に制御することにより、半導体基
板上のパターン寸法をウェーハ面内で均一にすることを
特徴とするフォト・レジストの現像方法。
Multiple developer supply nozzles in spin development method,
A photoresist characterized by making the pattern dimensions on a semiconductor substrate uniform within the wafer surface by individually controlling the temperature and amount of developer supplied from each nozzle arranged in the radial direction. Development method.
JP22460584A 1984-10-25 1984-10-25 Method of developing photo-resist Pending JPS61102034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22460584A JPS61102034A (en) 1984-10-25 1984-10-25 Method of developing photo-resist

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22460584A JPS61102034A (en) 1984-10-25 1984-10-25 Method of developing photo-resist

Publications (1)

Publication Number Publication Date
JPS61102034A true JPS61102034A (en) 1986-05-20

Family

ID=16816341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22460584A Pending JPS61102034A (en) 1984-10-25 1984-10-25 Method of developing photo-resist

Country Status (1)

Country Link
JP (1) JPS61102034A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000133587A (en) * 1998-08-19 2000-05-12 Tokyo Electron Ltd Image pickup device
JP2000228349A (en) * 1999-02-08 2000-08-15 Tokyo Electron Ltd Substrate treatment apparatus
JP2002118057A (en) * 2000-10-12 2002-04-19 Oki Electric Ind Co Ltd Photoresist development nozzle, photoresist development apparatus and method therefor
US6566275B1 (en) * 1999-11-15 2003-05-20 Samsung Electronics Co., Ltd. Spinner apparatus with chemical supply nozzle and methods of forming patterns and performing etching using the same
JP2010182715A (en) * 2009-02-03 2010-08-19 Tokyo Electron Ltd Development processing method and development processor
JP2015092523A (en) * 2013-11-08 2015-05-14 株式会社Screenホールディングス Substrate processing apparatus

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000133587A (en) * 1998-08-19 2000-05-12 Tokyo Electron Ltd Image pickup device
JP2000228349A (en) * 1999-02-08 2000-08-15 Tokyo Electron Ltd Substrate treatment apparatus
US6566275B1 (en) * 1999-11-15 2003-05-20 Samsung Electronics Co., Ltd. Spinner apparatus with chemical supply nozzle and methods of forming patterns and performing etching using the same
JP2002118057A (en) * 2000-10-12 2002-04-19 Oki Electric Ind Co Ltd Photoresist development nozzle, photoresist development apparatus and method therefor
JP2010182715A (en) * 2009-02-03 2010-08-19 Tokyo Electron Ltd Development processing method and development processor
JP2015092523A (en) * 2013-11-08 2015-05-14 株式会社Screenホールディングス Substrate processing apparatus

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