JPS61100940A - 半導体装置 - Google Patents

半導体装置

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Publication number
JPS61100940A
JPS61100940A JP59223313A JP22331384A JPS61100940A JP S61100940 A JPS61100940 A JP S61100940A JP 59223313 A JP59223313 A JP 59223313A JP 22331384 A JP22331384 A JP 22331384A JP S61100940 A JPS61100940 A JP S61100940A
Authority
JP
Japan
Prior art keywords
semiconductor chip
package
semiconductor
semiconductor device
stuck
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59223313A
Other languages
English (en)
Inventor
Miyoshi Yoshida
吉田　美義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
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Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59223313A priority Critical patent/JPS61100940A/ja
Publication of JPS61100940A publication Critical patent/JPS61100940A/ja
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、パッケージ内に半導体チップを固着しワイ
ヤボンディングした半導体装置に関する。
〔従来の技術〕
従来、この種の装置として、第４図及び第５図に斜視図
及び断面図で示すものがあった。（１）は能動素子を有
する半導体チップで、シリコン材などからなり、表面に
電気的機能を取出すためのアルミ材などの金属パッド（
２）が形式されている。（５）はアルミナなどを主成分
にしたセラミック基板からなるパッケージで、内部配Ｍ
　（６）が設けられ、下部に多数の外部リード（７）が
出されている。
半導体チップ（１）は裏面全体で、エポキシ樹脂系など
の接着剤（３）によりパッケージ（５）内の底面に接着
されて固着されている。この後、金属細線（４）を用い
て半導体チップ（１）の周辺部上の金属パッド（２）と
パッケージ（５）の内部配線（６）とを、ワイヤポンデ
ィングする。
上記のように、半導体チップ（１）を裏面全体で固着す
るのは、ワイヤボンディング工程時に半導体チップ（１
）の周辺部に押下げ荷重が加わるが、これにより破損が
生じるのを防ぐためである。
つづいて、ふた（８）をパッケージ（５）に取付け、半
導体チップ（１）部を外部環境から保護する。
〔発明が解決しようとする問題点〕
上記のような従来の半導体装置では、半導体チップ（１
）の裏面全体を接着剤（３）　Ｋよシパッケージ（５）
に固着しているが、双方の熱膨張係数が異なっており、
温度変化により熱８力が生じ、機械的強度が小さい半導
体チップ（１）が破損するという問題点があった。
１個の半導体チップ（１）内に多くの電気的機能を持た
せたものにすると、パッケージ当りの電気的機能密度が
増大するが、そのため、半導体チップ（１）の寸法が大
きくなる。このように半導体チップが大きくなると、温
度変化によるパッケージ（５）との熱膨張差が増大し、
熱心力はいっそう大きくな〕、破損が起こりやすくな９
、ある寸法よシ大きい半導体チップはパッケージ（５）
に装着できなくなるという問題点があった。
この発明は、このような問題点を解決するためになされ
たもので、パッケージに接合剤により固着された半導体
チップの、温度変化による破損をなくシ、信頼性を向上
した半導体装置を得ることを目的としている。
〔問題点を解決するための手段〕
この発明にかかる半導体装置は、パッケージ内の底面側
に、半導体チップを下方側中央部で接合剤により固着す
るようにし、半導体チップの周辺部におけるワイヤポン
ディング時の押付けを下方から受止める補強手段を設け
たものである。
〔作用〕
この発明においては、半導体チップは下方側中央孔で接
合剤によシパッケージ内の底面側に接着されており、温
度変化があると半導体チップは周辺部が拘束されること
なく伸縮がされる。また、半導体チップは周辺部上面側
にワイヤボンド作業で押付は力が加えられるが、補強手
段により下方から受止められる。
〔実施例〕
第１図はこの発明による半導体装置の一実施例を示す断
面図であシ、（１）　、　（４）　、　＜７’）　、　
（８）は上記従来装置と同一のものである。α力はアル
ミナなどを主成分とするセラミックからなるパッケージ
で、底面には半導体チップ（１）の周部下面を受ける突
起部（２）が形成され、半導体チップ（１）の補強手段
をなしている。半導体チップ（１）は下面中央部でエポ
キシ樹脂などの接着剤（２）によシ、パッケージ（ロ）
内の底面に接着されている。
このように１パツケージαη内の底面に接着剤α］によ
り下面中央部で固着された半導体チップ（１）のパッド
（２）（第４図参照）と、パッケージαηの内部配線（
６）とを、金属細線（４）によりワイヤボンディングし
ている。このワイヤボンド工程で半導体チップ（１）の
周辺８分には上方から押付は荷重が加わるが、下面が突
起部（２）で受けられてお９、破損が防がれる。
半導体チップ（１）は下面中央部のみでパッケージ（ロ
）に固着されており、熱膨張が拘束されることなく、熱
心力による損傷がなくされる。これにより、半導体チッ
プ（１）の寸法が大きくなっても、下面中央部で固着さ
れるので、支障なく適用できる。
第２図はこの発明の半導体装置の他の実施例を示す断面
図である。α→は半導体チップ（１）と熱膨張係数が同
一又は近似の材料からなる補強板で、補強手段をなし、
接着剤Ｑｅにより半導体チップ（１）を下面全体に一体
に接着されて補強し、下面中央部で接着剤ａ３によりパ
ッケージ（５）の底面に固着されている。
パッケージ（５）の底面には第１図のような突起部（２
）を設けていないが、ワイヤボンド工程による半導体チ
ップ（１）の周辺品分の押付は荷重は、補強板ａ３によ
り受止められ、破損が防がれる。
゛　第３図はこの発明の他の異なる実施例を示す半導体
装置の断面図である。パッケージα力内の底部には複数
個の半導体チップα・が、それぞれ下面中央部で接着剤
０３により固着されている。ｏｓはノくツケージαηに
かぶせられたふたである。この半導体チップａ・は、ワ
イヤポンド工程での周辺部の押下げ力に対し受ける補強
手段として、厚くしだ材料にし強度を増大している。こ
のように１半導体チップα０を厚くして強度を増すこと
によね、補強手段とすることができる。
なお、半導体チップ（１）、αＱの材料はシリコンに限
らず、ガリウム・ひ素材などの場合にも適用できるもの
である。
また、パッケージ（５）、（ロ）、αηの材料はアルミ
ナ材に限らず、他の材料によりてもよい。
さらに、接合剤として上記実施例ではエポキシ系の接着
剤（至）、（至）を用いたが、他の材質の接着剤でもよ
く、あるいは、鉛−すず、金−すずなどの軟ろう材を用
いてもよい。
〔発明の効果〕
以上のように、との発明によれば、半導体チップを下方
側中央部で接合剤によりパッケージ内の底部側に固着し
たので、温度変化による半導体チップの伸縮が拘束され
ず、破損がなくなり、信頼性が向上され、さらに１半導
体チップの寸法が大きいものが装着できる効果がある。
【図面の簡単な説明】
ｖｇ１図はこの発明による半導体装置の一実施例を示す
断面図、第２図はこの発明の他の実施例を示す半導体装
置の断面図、第３図はこの発明の他の異なる実施例を示
す半導体装置の断面図、第４図及び第５図は従来の半導
体装置の斜視図及び断面図である。 １・・・半導体チップ、４・・・金属細線、５，１１・
・・パッケージ、１２・・・補強手段（突起邪）、１３
　、１５・・・接合剤（接着剤）、１４・・・補強手段
（補強板）、１６・・・半導体チップ（補強手段付）、
１７・・・パッケージ なお、図中同一符号は同一又は相当部分を示す。 第１図 第２図 第３図 １６；斗導４本チツア　　１７：パッケージ。 第４図 第５図

Claims (5)

    【特許請求の範囲】
  1. （１）半導体チップをパッケージ内の底面側に固着し、
    上記半導体チップと上記パッケージの内部配線とをワイ
    ヤボンディングした半導体装置において、上記半導体チ
    ップの周辺部のワイヤボンディング時の押付けを下方か
    ら受止める補強手段と、上記半導体チップの下方側の中
    央部に介在し上記パッケージ内の底面に固着した接合剤
    とを備えたことを特徴とする半導体装置。
  2. （２）補強手段はパッケージ内の底面に設けられ、半導
    体チップの周辺部下面を受ける突起部からなる特許請求
    の範囲第１項記載の半導体装置。
  3. （３）補強手段は半導体チップと熱膨張係数が同一又は
    近似の材料からなり、上記半導体チップの下面に一体に
    接合されており、下面中央部に介在する接合剤によりパ
    ッケージ内の底面に固着された補強板からなる特許請求
    の範囲第１項記載の半導体装置。
  4. （４）補強手段は半導体チップの厚さを増大してなるこ
    とを特徴とする特許請求の範囲第１項記載の半導体装置
    。
  5. （５）複数個の半導体チップを１個のパッケージ内に装
    置したことを特徴とする特許請求の範囲第１項ないし第
    ４項のいづれかに記載の半導体装置。
JP59223313A 1984-10-22 1984-10-22 半導体装置 Pending JPS61100940A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59223313A JPS61100940A (ja) 1984-10-22 1984-10-22 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59223313A JPS61100940A (ja) 1984-10-22 1984-10-22 半導体装置

Publications (1)

Publication Number Publication Date
JPS61100940A true JPS61100940A (ja) 1986-05-19

Family

ID=16796191

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59223313A Pending JPS61100940A (ja) 1984-10-22 1984-10-22 半導体装置

Country Status (1)

Country Link
JP (1) JPS61100940A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998033212A1 (en) * 1997-01-23 1998-07-30 Seiko Epson Corporation Film carrier tape, semiconductor assembly, semiconductor device, manufacturing method therefor, mounting board, and electronic equipment
US6482673B2 (en) 1996-10-17 2002-11-19 Seiko Epson Corporation Semiconductor device, method of making the same, circuit board, flexible substrate, and method of making substrate

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482673B2 (en) 1996-10-17 2002-11-19 Seiko Epson Corporation Semiconductor device, method of making the same, circuit board, flexible substrate, and method of making substrate
US6727595B2 (en) 1996-10-17 2004-04-27 Seiko Epson Corporation Semiconductor device, method of making the same, circuit board, and flexible substrate
WO1998033212A1 (en) * 1997-01-23 1998-07-30 Seiko Epson Corporation Film carrier tape, semiconductor assembly, semiconductor device, manufacturing method therefor, mounting board, and electronic equipment
US6175151B1 (en) 1997-01-23 2001-01-16 Seiko Epson Corporation Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument
US6414382B1 (en) 1997-01-23 2002-07-02 Seiko Epson Corporation Film carrier tape, semiconductor assembly, semiconductor device and method of manufacturing the same, mounted board, and electronic instrument
US6646338B2 (en) 1997-01-23 2003-11-11 Seiko Epson Corporation Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument

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