JPS609336U - delay circuit - Google Patents
delay circuitInfo
- Publication number
- JPS609336U JPS609336U JP1983101255U JP10125583U JPS609336U JP S609336 U JPS609336 U JP S609336U JP 1983101255 U JP1983101255 U JP 1983101255U JP 10125583 U JP10125583 U JP 10125583U JP S609336 U JPS609336 U JP S609336U
- Authority
- JP
- Japan
- Prior art keywords
- nth
- transfer gate
- stage
- transfer
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Pulse Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
） 第１図は従来の回路例、第２図は本考案の一実
′ 流側、第３図は、第２図をパターン化したもので
１ ある。
なお図において、ＩＮ・・・・・・入力、ＯＵＴ・・・
・・・出力、・ ＩＮｖ・・・・・・インバータ、Ｔ
Ｒ，、ＴＲ２，ＴＲ３・・・・・・ＮチャンネルＭｏＳ
トランジスタ、コンタクト１，２゜； ３・・・・
・・コンタクト、である。) FIG. 1 is an example of a conventional circuit, FIG. 2 is an actual version of the present invention, and FIG. 3 is a patterned version of FIG. 2. In the diagram, IN...Input, OUT...
...Output, INv...Inverter, T
R,, TR2, TR3...N channel MoS
Transistor, contact 1, 2°; 3...
...contact.
Claims (1)
ゲートの入力とを接続し、前記第２のトラン不ファゲー
トの出力と第３のトランスファケートの入力とを接続し
、同様にくり返してＮ段Ｃトランスファケートを接続し
て第Ｎのトランスファケートの出力を次段のインバータ
に接続し、軍記第１のトランスファゲートから前記第Ｎ
のトランスファゲートの制御入力を、前記第１のトラン
スファゲートから前記第Ｎのトランスファゲートがオン
になるような電圧にし、マスタースライヌにより第１段
から第Ｎ段まで自由な段数に直列に接続し、抵抗を変え
て第１段の入力から第Ｎ段の・ 出力までの伝搬遅延
時間を所望の値にすることを特徴とした遅延回路。Connect the output of the first transfer gate and the input of the second transfer gate, connect the output of the second transfer gate and the input of the third transfer gate, and repeat the same process to transfer the N-stage C transfer. The output of the Nth transfer gate is connected to the next stage inverter, and the output of the Nth transfer gate is connected from the first transfer gate to the Nth
The control inputs of the transfer gates are set to a voltage such that the first to Nth transfer gates are turned on, and the control inputs are connected in series to any number of stages from the first stage to the Nth stage by a master line. A delay circuit characterized in that the propagation delay time from the input of the first stage to the output of the Nth stage is set to a desired value by changing the resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983101255U JPS609336U (en) | 1983-06-29 | 1983-06-29 | delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983101255U JPS609336U (en) | 1983-06-29 | 1983-06-29 | delay circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS609336U true JPS609336U (en) | 1985-01-22 |
Family
ID=30239186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983101255U Pending JPS609336U (en) | 1983-06-29 | 1983-06-29 | delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS609336U (en) |
-
1983
- 1983-06-29 JP JP1983101255U patent/JPS609336U/en active Pending
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