JPS5893035U - oscillation circuit - Google Patents
oscillation circuitInfo
- Publication number
- JPS5893035U JPS5893035U JP13903582U JP13903582U JPS5893035U JP S5893035 U JPS5893035 U JP S5893035U JP 13903582 U JP13903582 U JP 13903582U JP 13903582 U JP13903582 U JP 13903582U JP S5893035 U JPS5893035 U JP S5893035U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- circuit
- mos
- inverter
- oscillation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の発振回路のブロック図、第２図は本考案
発振回路のブロック、第３図は動作説明に供するタイム
チャート、第４図は他の実施例のブロック図である。
符号、ｐ：ｐチャネルＭＯ３）ランジスタ、ｎ：ｎチャ
ネルＭＯ３トランジスタ、Ｉ□〜Ｉ ｎ：発振用インバ
ータ回路、１２，１３：波形整形用インバータ回路。FIG. 1 is a block diagram of a conventional oscillation circuit, FIG. 2 is a block diagram of the oscillation circuit of the present invention, FIG. 3 is a time chart for explaining the operation, and FIG. 4 is a block diagram of another embodiment. Symbol, p: p-channel MO3) transistor, n: n-channel MO3 transistor, I□ to I n: oscillation inverter circuit, 12, 13: waveform shaping inverter circuit.
Claims (1)
段縦続接続しでなるリング式の発振回路において、縦続
接続された発振用のインバータ回路に波形整形用のイン
バータ回路を縦続接続してリングを構成し、上記発振用
インバータ回路をなずＣ−ＭＯＳインバータの少なくと
も一方のトランジスタに、直列にＣ−ＭＯＳインバータ
の直列オン抵抗を可変するトランジスタ回路を接続し−
１該トランジスタ回路を、上記Ｃ−ＭＯ３）ランジスタ
の一方のトランジスタと同一チャネルのＭＯＳ）ランジ
スタと、該ＭＯＳトランジスタのゲートに、端子間電圧
の一方の電位がバイアス電位として与えられ且つ抵抗と
なるＣ−ＭＯＳ トランジスタとで構′成したことを特
徴とする発振回路。In a ring type oscillation circuit consisting of an odd number of cascaded inverter circuits made of C-MOS transistors, a ring is formed by cascade-connecting a waveform shaping inverter circuit to the cascade-connected oscillation inverter circuit, and the above-mentioned method is used. A transistor circuit for varying the series on-resistance of the C-MOS inverter is connected in series to at least one transistor of the C-MOS inverter without an oscillation inverter circuit.
1) The transistor circuit is connected to a MOS transistor having the same channel as one of the transistors of the above C-MO3) transistor, and one potential of the voltage between the terminals is applied as a bias potential to the gate of the MOS transistor, and the C serves as a resistor. - An oscillation circuit characterized in that it is configured with a MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13903582U JPS5843298Y2 (en) | 1982-09-14 | 1982-09-14 | oscillation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13903582U JPS5843298Y2 (en) | 1982-09-14 | 1982-09-14 | oscillation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5893035U true JPS5893035U (en) | 1983-06-23 |
| JPS5843298Y2 JPS5843298Y2 (en) | 1983-09-30 |
Family
ID=29932239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13903582U Expired JPS5843298Y2 (en) | 1982-09-14 | 1982-09-14 | oscillation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5843298Y2 (en) |
-
1982
- 1982-09-14 JP JP13903582U patent/JPS5843298Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5843298Y2 (en) | 1983-09-30 |
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