JPH04258017A - Delay circuit - Google Patents

Abstract

PURPOSE:To easily secure a required delay time with respect to the delay circuit used in a semiconductor integrated circuit. CONSTITUTION:A source of a P-channel MOS transistor TR 3 is connected to an output terminal Tout of an inverter 1, a drain of the TR 3 is connected to a power supply Vss via a capacitor C, to a drain of an N-channel MOS TR 4, a source of the TR 4 connects to the power supply Vss, and an input signal Vin2 transited similarly to the transition of an input signal Vin1 from an H level to an L level of the inverter 1 is inputted to gates of the TRs 3, 4 synchronously with the input signal Vin1. Or the circuit constitution employing N-channel MOS TRs 5, 6 is used in place of that employing the P-channel MOS TRs 3, 4.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit for appropriately setting the input timing of each control signal within a semiconductor integrated circuit. A large number of internal circuits constituting a semiconductor integrated circuit operate based on control signals at various timings. For example, in a semiconductor memory device, in order to set the input timing of a write signal and a data signal, it is necessary to set a setup time, a hold time, etc. using a control signal. To generate such a control signal, a delay circuit is used that outputs an output signal that is delayed with respect to the rising edge of the input signal or an output signal that is delayed with respect to the falling edge of the input signal.

0002

2. Description of the Related Art A conventional delay circuit is composed of an inverter circuit 1 as shown in FIG. For example, by reducing the gate width of the P-channel MOS transistor Tr1 of this inverter circuit 1, the input signal V
Forming a delay circuit that delays the rise of the output signal Vout with respect to the fall of the input signal Vin, or delays the fall of the output signal Vout with respect to the rise of the input signal Vin by reducing the gate width of the N-channel MOS transistor Tr2, A required delay time has been set by forming multiple stages of such inverter circuits 1 in series.

0003

However, in the above-described delay circuit, the delay time is set by adjusting the on-resistance of the transistor constituting the inverter circuit 1, so that the rise or fall of the input signal Vin is When setting a delay operation that delays only the falling direction, it has been difficult to secure a sufficiently long delay time.

An object of the present invention is to provide a delay circuit that can easily and reliably secure a required delay time.

[0005]

[Means for Solving the Problems] FIG. 1(a) is a diagram explaining the principle of the first invention. That is, the source of the P-channel MOS transistor Tr3 is connected to the output terminal Tout of the inverter circuit 1 to which the high-potential side power supply Vcc and the low-potential side power supply Vss are supplied, and the drain of the P-channel MOS transistor Tr3 has a capacitance C. The N-channel MOS transistor Tr4 is connected to the low-potential side power supply Vss via the
The source of the transistor Tr4 is connected to the low potential side power supply Vss, and the gates of both transistors Tr3 and Tr4 are connected to an input signal Vin1 which changes from the H level to the L level in synchronization with the input signal Vin1 which changes from the H level to the L level of the inverter circuit 1. Input signal Vin2 is input.

FIG. 1(b) is a diagram explaining the principle of the second invention. That is, the high potential side power supply Vcc and the low potential side power supply Vs
The output terminal Tout of the inverter circuit 1 is supplied with
The source of an N-channel MOS transistor Tr5 is connected to the N-channel MOS transistor Tr5, and the drain of the N-channel MOS transistor Tr5 is connected to the high potential side power supply Vcc via a capacitor C, and is also connected to the drain of a P-channel MOS transistor Tr6. Channel MOS transistor Tr
The source of 6 is connected to the high potential side power supply Vcc, and the gates of both transistors Tr5 and Tr6 have an input that changes from L level to H level in synchronization with input signal Vin1 that changes from L level to H level of inverter circuit 1. Signal Vi
n2 is input.

[0007]

[Operation] In the first invention, when the input signal Vin2 which changes from the H level to the L level in synchronization with the input signal Vin1 which changes from the H level to the L level is input, the input signal is sent from the output terminal Tout of the inverter circuit 1. Vin1
An output signal Vout is output that rises with a large delay from the fall of Vout.

In the second invention, when the input signal Vin2 which changes from L level to H level in synchronization with the input signal Vin1 which changes from L level to H level is input, the input signal is output from the output terminal Tout of the inverter circuit 1. Vi
An output signal Vout is output which falls with a large delay from the rise of n1.

[0009]

[Embodiment] A first embodiment embodying the present invention will be described below with reference to FIGS. 2 and 3. The inverter circuit 1 of the delay circuit shown in FIG. 2 is supplied with a high potential power supply Vcc and a low potential power supply Vss, and the source of a P-channel MOS transistor Tr3 is connected to the output terminal of the inverter circuit 1. The drain has a capacitance C
is connected to the power supply Vss via the N-channel M
It is connected to the drain of the OS transistor Tr4. Note that the capacitance C is realized by the junction capacitance and gate capacitance of the transistor, and its capacitance value is set to be sufficiently larger than the sum of the junction capacitance of the transistors constituting the inverter circuit 1 and the junction capacitance of the transistor Tr3. The size of Tr4 is larger than that of the transistors constituting the inverter circuit 1, and ensures a larger current driving capability than the inverter circuit 1. Transistor Tr3, Tr
The gate of 4 is connected to the input terminal of inverter circuit 1,
The source of the transistor Tr4 is connected to the power supply Vss.

In the delay circuit having such a configuration, when the input signal Vin rises from the L level to the H level, the transistor Tr3 is in the OFF state. Therefore, as shown in FIG. 3, the output signal Vout in response to the rise of the input signal Vin
The fall delay time Tpdr becomes smaller. At this time, the transistor Tr4 is turned on and the charge in the capacitor C is discharged to the power supply Vss via the transistor Tr4.

On the other hand, when the input signal Vin falls from H level to L level, inverter circuit 1 attempts to output an H level output signal, but at the same time transistor Tr3 is turned on, as shown in FIG. The output signal Vout of the inverter circuit 1 is continuously maintained at the L level, and the drain current of the transistor Tr3 causes the capacitance C
When charging is completed, the drain current of the transistor Tr3 is cut off and the output signal Vout becomes H level. As a result, the rise delay time tpdf of the output signal Vout with respect to the fall of the input signal Vin becomes sufficiently larger than the fall delay time tpdr.

Therefore, in this delay circuit, the input signal V
A sufficient rise delay time tpdf of the output signal Vout can be ensured based on the input of the inverter circuit 1, and the inverter circuit 1 includes two transistors Tr3 and Tr3.
This can be realized with a simple configuration by simply adding Tr4 and capacitor C. Furthermore, the rise delay time tpdf can also be adjusted by changing the capacitance value of the capacitor C.

Next, a second embodiment embodying the present invention will be described with reference to FIGS. 4 and 5. The inverter circuit 1 of the delay circuit shown in FIG. 4 is supplied with a high-potential power supply Vcc and a low-potential power supply Vss, and a train of N-channel MOS transistors Tr5 is connected to the output terminal of the inverter circuit 1. The source is connected to the power supply Vcc via the capacitor C, and is also connected to the source of the P-channel MOS transistor Tr6. Note that the capacitance C is realized by the junction capacitance and gate capacitance of the transistor as in the first embodiment, and its capacitance value is sufficiently larger than the sum of the junction capacitance of the transistor and the junction capacitance of the transistor Tr5 constituting the inverter circuit 1. It is set to be. The gates of the transistors Tr5 and Tr6 are connected to the input terminal of the inverter circuit 1, and the drain of the transistor Tr6 is connected to the power supply Vss.

In the delay circuit having such a configuration, when the input signal Vin rises from the L level to the H level, the inverter circuit 1 attempts to output an L level output signal, but at the same time, the transistor Tr5 is turned on, so that the 3, the output signal Vout of the inverter circuit 1
is continuously maintained at H level, and the transistor Tr5
When the charging of the capacitor C is completed by the drain current of the transistor Tr5, the drain current of the transistor Tr5 is cut off and the output signal Vo
ut becomes L level. As a result, the fall delay time tpdr of the output signal Vout with respect to the rise of the input signal Vin becomes sufficiently large.

On the other hand, when the input signal Vin falls from the H level to the L level, the transistor Tr5 is in the off state, so as shown in FIG. 5, the rise delay time tp of the output signal Vout with respect to the fall of the input signal Vin
df becomes smaller. At this time, the transistor Tr6 is turned on and the charge in the capacitor C is discharged to the power supply Vcc via the transistor Tr6.

Therefore, in this delay circuit, the input signal V
A sufficient fall delay time tpdr of the output signal Vout can be ensured based on the input of in, and it can be realized with a simple configuration similar to the first embodiment.

[0017]

As described in detail above, the present invention exhibits the excellent effect of providing a delay circuit that can easily and reliably secure the required delay time.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a waveform diagram showing the operation of the first embodiment.

FIG. 4 is a circuit diagram showing a second embodiment.

FIG. 5 is a waveform diagram showing the operation of the second embodiment.

FIG. 6 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1 Inverter circuit Vcc High potential side power supply Vss Low potential side power supply Tout Output terminal Vout Output signal Tr3, Tr6 P channel MOS transistor Tr4, Tr4 N channel MOS transistor C Capacitance

Claims (2)

[Claims] Claim 1: The source of a P-channel MOS transistor (Tr3) is connected to the output terminal (Tout) of an inverter circuit (1) to which a high potential side power source (Vcc) and a low potential side power source (Vss) are supplied. , the drain of the P-channel MOS transistor (Tr3) is connected to the low potential side power supply (Vss) via a capacitor (C) and also connected to the drain of the N-channel MOS transistor (Tr4). ) is connected to the low potential side power supply (Vss), and both transistors (Tr
3, Tr4) has an input signal (Vin1) that transitions from H level to L level in synchronization with the input signal (Vin1) that transitions from H level to L level of inverter circuit (1).
A delay circuit characterized in that an input signal (in2) is input. 2. The source of an N-channel MOS transistor (Tr5) is connected to the output terminal (Tout) of the inverter circuit (1) to which the high potential side power source (Vcc) and the low potential side power source (Vss) are supplied. , the drain of the N-channel MOS transistor (Tr5) is connected to the high potential side power supply (Vcc) via the capacitor (C), and is also connected to the drain of the P-channel MOS transistor (Tr6). ) is connected to the high potential side power supply (Vcc), and both transistors (Tr
5, Tr6) has an input signal (Vin1) that transitions from L level to H level in synchronization with the input signal (Vin1) that transitions from L level to H level of inverter circuit (1).
A delay circuit characterized in that an input signal (in2) is input.