JPS591241U - Dynamic frequency divider circuit - Google Patents
Dynamic frequency divider circuitInfo
- Publication number
- JPS591241U JPS591241U JP6747083U JP6747083U JPS591241U JP S591241 U JPS591241 U JP S591241U JP 6747083 U JP6747083 U JP 6747083U JP 6747083 U JP6747083 U JP 6747083U JP S591241 U JPS591241 U JP S591241U
- Authority
- JP
- Japan
- Prior art keywords
- frequency divider
- divider circuit
- dynamic frequency
- transistor
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のダイナミック分周回路、第２図はその動
作図、第３図は誤動作の起きる場合の動作図で、第４図
〜第９図は本考案による分周回路の例である。
、 １・・・・・・クロックパルス印加部、２〜４・
・・・・・分周回路のゲート部、５． ６． ７・・・
・・・トランジスタ、（２ｎ＋２）・・・・・・（２ｎ
＋１）段目のゲート部。Figure 1 is a conventional dynamic frequency divider circuit, Figure 2 is its operation diagram, Figure 3 is an operation diagram when a malfunction occurs, and Figures 4 to 9 are examples of the frequency divider circuit according to the present invention. . , 1... Clock pulse application section, 2-4.
...Gate section of frequency divider circuit, 5. 6. 7...
...Transistor, (2n+2)...(2n
+1) tier gate section.
Claims (1)
タを制御するクロックド・トランジスタよりなる１ ／
（２ｎ ＋ １ ）；（ｎは≧１の整数）のダイナミッ
ク分周回路に於いて、前記インバーターの偶数段のＭＯ
Ｓトランジスタのソース又はドレインと電源の間に付加
ＭＯＳトランジスタを加え、前記付加ＭＯＳトランジス
タのゲートに前記インバータの初段入力を加えたことを
特徴とするダイナミック分周回路。1/1 consisting of an odd number of stages of CMOS inverters and a clocked transistor for controlling the CMOS inverters.
(2n + 1); (n is an integer of 1 or more), in a dynamic frequency divider circuit, the MO of an even number of stages of the inverter
A dynamic frequency divider circuit characterized in that an additional MOS transistor is added between the source or drain of the S transistor and a power supply, and a first stage input of the inverter is added to the gate of the additional MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6747083U JPS6029244Y2 (en) | 1983-05-06 | 1983-05-06 | Dynamic frequency divider circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6747083U JPS6029244Y2 (en) | 1983-05-06 | 1983-05-06 | Dynamic frequency divider circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS591241U true JPS591241U (en) | 1984-01-06 |
| JPS6029244Y2 JPS6029244Y2 (en) | 1985-09-04 |
Family
ID=30197657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6747083U Expired JPS6029244Y2 (en) | 1983-05-06 | 1983-05-06 | Dynamic frequency divider circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6029244Y2 (en) |
-
1983
- 1983-05-06 JP JP6747083U patent/JPS6029244Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6029244Y2 (en) | 1985-09-04 |
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