JPS6029244Y2 - Dynamic frequency divider circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dynamic frequency divider circuit constituted by complementary connected insulated gate field transistors.

An object of the present invention is to detect the cause of malfunction during frequency division and compensate for it, thereby ensuring reliable operation of the frequency divider circuit.

Conventionally, electronic watches using high-frequency crystal resonators, such as AT-cut crystal resonators, have used dynamic frequency divider circuits for low power and high-speed operation.

Particularly for a crystal resonator having a fundamental frequency that is a multiple of 3, the 1/39 circuit is extremely important in practice.

A conventional 173 frequency divider circuit is shown in FIG.

Figure 1 shows a 1/3 dynamic frequency divider circuit in which clocked inverters having clocked transistors are connected in a closed loop in three stages between a C-MOS inverter and a power supply, where 1 is a clock pulse application section, 2, 3 4 is each gate portion of the frequency dividing circuit.

Also, Figure 2 shows 2.3 when the clock pulse is input to 4.
4 shows the potential changes at each part of 4.

When using the above frequency divider circuit, 2.3. In some cases, the potential of each part of the circuit 4 becomes an intermediate potential of the power supply voltage, which is prohibited in circuit operation.

If a clock pulse is applied in such case 1,
The frequency divider circuit does not operate normally as shown in Figure 2,
Each of the sections 2, 3, and 4 changes its potential in synchronization with the clock pulse as shown in FIG. 3, and does not function as a frequency dividing circuit.

This is because when the clock pulse is at a low level, P channel transistors 10, 11, and 12 are turned on, but 2, 3...
Since each part of transistor 4 is tilted toward the bi-level side, the P-channel transistors 13, 14, and 15 are not turned on deeply, but the N-channel transistors 23, 24, and 25 are turned on more deeply.

However, since the N-channel transistors 20, 21, and 22 are turned off by the clock pulse, the portions 2, 3, and 4 are not pulled up to the level of the power supply voltage.

Next, when the lock pulse is at a high level, the N-channel transistors 20, 21, and 22 are turned on, but 2°3.4
Since each part of the transistor is tilted toward the low level side, the N-channel transistors 23, 24, and 25 are not turned on deeply, but the P-channel transistors 13, 14, and 15 are turned on more deeply.

However, since P-channel transistors 10, 11.12 are not turned on, each portion of 2, 3.4 is not determined at the level of the power supply voltage.

In the end, the parts 2, 3.4 are synchronized with the clock pulse as shown in FIG. 3, and when the clock pulse is at a low level, the P-channel transistors 10, 11, and 12 are turned on, so 2. 3. In each part of 4, N-channel transistors 20, 21, and 22 are turned on when the clock pulse is at high level, so 2, 3.
Each part of 4 changes to the low level side, causing a problem in that the voltage does not reach the full power supply voltage, but changes only in an intermediate potential, and no frequency dividing operation is performed.

The present invention eliminates the above-mentioned drawbacks, and has the following features:
．． When each part of 4 is at an intermediate potential of the power supply voltage, this is detected and the frequency dividing function is ensured by forcibly preventing each part of 2, 3, and 4 from reaching an intermediate potential. This is what I did.

Embodiments of the present invention will be described with reference to the drawings.

FIG. 4 shows a specific example of the present invention, and 5 is an additional transistor added according to the present invention.

With these five additional transistors, 2. 3. When each portion of 4 is at an intermediate potential, the additional transistor 5 is conductive, so that the potentials of portions 2.3 and 4 are separated.

This will be explained in more detail. As mentioned above, in the conventional example without the additional transistor 5, there was a problem in that the transistor could not be removed from the intermediate potential of the power supply voltage in synchronization with the clock pulse.

In the present invention, an additional transistor 5 is newly provided in parallel with the P-channel transistor 11 in order to escape from this unfavorable synchronization with the clock pulse.

With this configuration, when the clock pulse is at a high level and the P-channel transistors 13, 14.15 are turned on more deeply than the N-channel transistors 23, 24.25, the P-channel transistors 10, 11.12
Even if the additional transistor 5 is off, the additional transistor 5 is inputted in parallel with the P-channel transistor 11 with a level that is too high on the low level side and is turned on deeply.
Since the P-channel transistor 14 is turned on deeply, the potential of the portion 4 is forcibly pulled to the high level side.

As a result, the potentials of each part of 2°3 become low level and high level, respectively, and it is possible to escape from the state of being synchronized with the clock pulse at an intermediate potential.

Further, since the additional transistor No. 5 is given a potential of 2, and the additional transistor No. 14 is given a potential of 3, they will not become conductive during normal operation, and normal operation will not be disturbed.

As described above, the frequency dividing circuit according to the present invention helps prevent malfunction of the frequency dividing circuit and significantly improves the division function.

Furthermore, in the above example, separation of potentials between portions 2 and 3 and portions 4 was considered, but of course separation between portions 2 and 3, 4, 2, 4 and 3 may be possible.

An example in which an additional transistor 6 is added is shown in FIG.

Furthermore, considering the complementarity of the transistors from a functional point of view, it is possible to add a force-loading transistor as shown in FIG. 6 instead of the one shown in FIG. 4, and other cases can be considered in the same way.

The present invention can be applied not only to 1739 frequency circuits, but also to general frequency dividing circuits of 1/(2n+1), where n is an integer, by adding transistor 8 as shown in Fig. It can be applied to the frequency dividing circuit of the crystal oscillator.

It is also believed that the present invention can be applied to general high frequency frequency divider circuits.

This configuration prevents the potential of the drain of the C-MOS inverter of the 1/(2n+1) dynamic frequency divider circuit from becoming an intermediate potential of the power supply voltage, which would disable the circuit operation.
Moreover, since the input signal of the clocked inverter at the previous stage is input to the gate portion of the additional transistor, there is no adverse effect during normal operation.

[Brief explanation of the drawing]

Figure 1 is a conventional dynamic frequency divider circuit, Figure 2 is its operation diagram, Figure 3 is an operation diagram when a malfunction occurs, and Figure 4 is a diagram of its operation.
7 to 7 are examples of frequency dividing circuits according to the present invention. 1...Clock pulse application section, 2-4...
・Gate part of frequency divider circuit, 5.6.7.8...
Gate section of additional transistor (2n+2)-(2n+1)th stage.

Claims (1)

[Scope of utility model registration request] 1/(2n+1) in which clocked inverters each having a clocked transistor provided between the C-MOS inverter and the power supply are connected in an odd number of stages in a closed loop; (n is a natural number) In a dynamic frequency divider circuit, clocked inverters at any stage are connected in a closed loop. An additional MO3) transistor is provided in parallel with one of the clocked transistors, and an input signal of a clocked inverter located at the preceding stage of the clocked inverter at the arbitrary stage is connected to the gate electrode of the additional MOS transistor. Dynamic frequency divider circuit.