JPS6090408A - Automatic level control circuit - Google Patents

Abstract

PURPOSE:To reduce signal distortion and perform high-precision control by varying the gain of a variable gain amplifier stepwise at specific intervals, and controlling this gain linearly according to the value of a counter which counts a clock according to an output level. CONSTITUTION:An output voltage e0 is detected by a level detector 20 and the counting-up or -down operation of the 1st counter 42 is specified according to whether the output E0 is larger than a reference voltage Er, thereby counting the clock CP. A shift-up output KD or shift-down output KU is sent to the 2nd counter 43 with the carry C or borrow B of the counter 42 to turn on one of FETs 161-169 according to the counted value of the 2nd counter 43. Resistances 151-159 are so set as to vary the gain of the amplifier 10 linearly, so the gain is controlled linearly according to the output voltage and signal distortion is reduced to perform high-precision level control.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in an automatic level control circuit (ALC circuit) used for stabilizing the detection level of a data transmission device, for example.

[Technical background of the invention]

Conventionally, as a circuit of this type, for example, as shown in FIG. 1, an output signal e of a variable gain amplifier 1 is used.

is rectified by the level detector 2 to detect the level and output the detection output E. is compared with the reference level Br by the comparator 3, and the error voltage ΔV obtained via the integrator 4 is supplied to the FETIa of the variable gain amplifier 1 to control the gain by varying its resistance value. The output signal e. A method is known in which the level of is made constant. In such a circuit, for example, when the input signal ei decreases, the detection level Bo of the output signal e0 decreases, so the error voltage ΔV obtained by comparing it with the reference level Er also decreases,
This reduces the resistance value of FET 1a of variable gain amplifier 1. Then, the gain G increases because it can be expressed as when the resistance value of the negative feedback resistor 1b is RF and the resistance value of the FET 1a is Rs, and as a result, the input signal ei is amplified to a greater extent and becomes the 8'' output signal e. The amplitude of is held constant. Note that when the input signal ei increases, an operation opposite to the above operation is performed, and the output signal e. The level of is fixed.

[Melting point of background technology]

However, such conventional circuits are limited to variable gain amplifier l.
The gain is controlled by varying the resistance value of FE'l'la. Therefore, the change in gain is FE,
The output signal e is dominated by the resistance change characteristics of Tza, and generally the inter-channel resistance of i' ET is linear only within the drain-source voltage range of about 100 mV to 200 mV. However, this method has the disadvantage of causing signal distortion due to nonlinearity.

- [Object of the Invention] An object of the present invention is to provide an automatic level control circuit that can reduce signal distortion and perform highly accurate level control.

[Summary of the invention]

In order to achieve the above object, the present invention provides a variable gain amplifier with a configuration in which the gain can be varied in multiple stages at predetermined intervals, compares the detection level of an output signal with a reference level, and determines the magnitude relationship between the two. The clock is counted up or down depending on the result, and the gain of the variable gain amplifier is varied depending on the count value.

[Embodiments of the invention]

FIG. 2 shows the configuration of an automatic level control circuit according to an embodiment of the present invention, in which 10 represents a variable gain amplifier, 20 represents a level detector, 3o represents a comparator, and 40 represents a control section.

The variable gain amplifier 10 includes an amplifier 11 and its output signal e.
. Nine resistors 151 to 159, together with the feedback resistor 12, determine the gain of the amplifier z1.
It is composed of. These resistors are connected in series with the switching FETs 161-169, and only one of the FETs is in a conductive state, so the voltage gain GN is given by the following equation.

However, RF: resistance 12 Gs: G, G,..., G.

R2H: R8I (Resistance 151) T RSt (
The gain error level detector 20 of 1 step is composed of a peak-to-peak detection circuit, and is constructed as shown in Figure 3. That is,
The circuit includes a buffer amplifier 21a, a diode 22a1
Capacitor 23a.

A negative peak value detection circuit 26B is constructed from the discharge circuit 24a of the capacitor 23a and the buffer amplifier 25B, and the buffer amplifier 21b% diode 22b
1 capacitor 23b.

The discharge circuit 24b and the buffer amplifier 25b constitute a positive peak value detection circuit 26b. Then, the detection outputs of these peak value detection circuits 26a and 26b are led to the inverting input terminal and non-inverting input terminal (G) of the differential amplifier 28 via resistors 278 and 27b, respectively,
The difference output is sent out as a peak-to-peak detection output Eo. In addition, this circuit applies a carry output Kl) from the control unit 40 (to be described later) to the switching transistors 29a and 29bl of the discharge circuits 24a and 24b, thereby forcibly discharging the capacitors 923a and 23b. I have to.

Comparator 30 includes comparator 311 . and a reference power supply 32, which detects the peak output from the level detector 2°.
Peak detection output E. compared with the reference level Er.

B,,)Er When , a comparison output of "H" level is generated and Eo＜Er When , a comparison output of IL level is generated.

The control unit 40 includes a clock generator 41, a first up/down counter 42, and a digit output from this counter 42. -J-KU and a second up/down counter 43 that counts the carry output KD, and a second 7-counter that counts the gain holding signal (■ (''level) PS) from a control signal generation circuit (not shown). and two AND gates 44a and 44b that block the supply of the down and carry outputs KU and KD to the pull-down counter 43.

It is composed of a return circuit 47 that supplies the carry down and carry outputs KU and KD to the first up/down counter 42 via an OR gate 45 and a delay circuit 46, and returns the count value of this counter 42 to its initial value. has been done.

The first up/down counter 42 counts up or down the clock pulse CP generated from the clock generator 41 according to the comparison output level of the comparator 30.

On the other hand, the second up-down counter 43 up-counts and down-counts the carry output KU and carry output KD of the first up-down counter 42, respectively, and outputs 'H' from the output terminals S1 to S9 corresponding to the count value.
Furthermore, as shown in FIG. Frequency divider 411
, 412 to divide the frequency, and the divided output is sent to the selection circuit 4.
] 13, it is selectively selected and output as a clock pulse CP. The selection circuit 413 is operated by a frequency selection signal FS generated from a control signal generation circuit (not shown).

Furthermore, when the initialization signal RON is generated from a control signal generation circuit (not shown), the control unit 40 sets the count values of the first and second up/down counters 42, 43 to the median value within the count range. I am trying to initialize it.

Next, the operation of the circuit configured as described above will be explained with reference to the timing diagrams of FIGS. 5 to 7.

First, we will explain the rising state in which the signal - is input and the output signal level becomes stable.

When the input signal eli arrives and the initialization signal RON is generated from a control signal generation circuit (not shown).

The count values of the first and second up/down counters 42 and 43 are the median values within the count range, respectively.
3” and “5”.

Therefore, the second up/down counter 43 outputs a 'H' level control signal from the output terminal 8B and F
ET 165 becomes conductive, and as a result, variable gain amplifier 10 amplifies input signal ei with a gain Gfi determined by resistor 155 and feedback resistor 12.

However, the output signal e obtained from the variable gain amplifier 10 at this time. Detection level E. Since Eo<Er with respect to the reference level Br, the comparison output C8 of the comparator 30 is at the "L" level. Therefore, the up/down counter 42 of ff1-1 enters the down count mode and counts down the clock pulse CP. As a result, the count value CT1 of the up/down counter 42 of @l changes from "3" to r
2J, rlJ. Then, count value CTJ
When becomes "0", the up/down counter 42 of @l generates a carry down output K[J, and this output KU is sent to the second up/down counter 4 via the AND gate 44a.
It is applied to the up terminal U of No. 3. As a result, the second up/down counter 43 increments the count value CTJ to "6" and outputs an "H" level signal from the output terminal S6. For this reason, the variable gain amplifier 10.

FET 166 becomes conductive, reducing the gain to this resistor 15.
6 and the feedback resistor 12. The gain is thus increased by l steps ΔG, thereby increasing the output signal e. The level increases by a constant value as shown in FIG. On the other hand, the carry down output KU is applied to the first up/down counter 42 via a return circuit 47 as a return signal LS. Therefore, the count value CTz of the first up/down counter 42 returns to the initial value "3". When the count value CT1 returns to "3", the output signal e is output as shown in FIG. Detection level E0 is higher than reference level Hr.
o(Er), the first up/down counter 42 repeats the above counting operation and generates a down-down output KU every time the count value CTZ becomes "0". The up/down counter 43 of
59 selected positions are stepped up in order to obtain a gain G,
, G, are increased by a constant value ΔG.

This gain increase causes the output signal e. detection level 13o
becomes E o > E r with respect to the reference level Mr, and as a result, the comparison output C8 of the comparator 30 becomes “H”.
When the clock pulse CP reaches the level, the first up/down counter 42 enters the up-count mode and starts up-counting the clock pulse CP. Also, at this time, the above E0:>E
When the relationship r is achieved, the control signal generation circuit (not shown) determines that the rising state of the input signal ei has ended, and the control signal F S goes to the "L" level.

Therefore, the selection circuit 413 of the clock generator 41 selects the output of the divider 411 instead of the divider 412,
As a result, the first amplifier down counter 42 is supplied with the low-speed clock CPo/N instead of the high-speed clock CPo/M that had been supplied so far. Therefore, the counting operation of the first up/down counter 42 is performed thereafter.

In other words, the variable gain control operation of the variable gain amplifier 10 is slower than during the rising period.

Next, the stable state will be explained. When the count value CT1 becomes "6" due to the count up operation of the first up/down counter 42, a carry output KD is generated from the counter 42, and this carry output KD As a result, the count value CTz of the second up/down counter 43 is counted down to "7". As a result, the selected positions of the resistors 152 to 159 of the variable gain amplifier IO are also stepped down to 157.

As a result, the gain becomes G and decreases by a constant value.

Then, due to this gain reduction, the output signal e. Detection level E. When Eo<Er again, the first up/down counter 42 counts down the clock pulse CP.

Decrement output K when count value CTI reaches 10.
Convert U to 'J (=') and enter the second up/down counter 43
The count value CT2 is set to "8".

As a result, the gain of the variable gain amplifier 10 is again increased by the resistor 15B.
Step up to the higher value G8 corresponding to . Thereafter, the count value CT2 of the second up/down counter 43 repeats "7" and "8" at a speed corresponding to the clock pulse CP in accordance with the comparison output CS level of the comparator 30.
The output signal e0 also changes correspondingly. therefore,
Output signal e. The output amplitude is stabilized within one step error of the gain. Also, compared to resistor J5J-159, F
Since the conduction resistance of ET is extremely small and can be ignored, signal distortion due to nonlinearity of FIT, which was a problem in conventional circuits, does not occur, and even if it occurs, it will be extremely small.Furthermore, in the circuit with the above configuration, , the lower the frequency of the clock pulse CP, the more accurately the peak-to-peak value can be detected by the level detector 2o.
On the other hand, the response speed is slow. - If the frequency of the clock pulse CP is increased in order to increase the force response speed, the first up/down counter 42 will perform a counting operation in the wrong direction before the true peak value of the output signal eo has arrived. probability increases, which may lead to deterioration of level stabilization performance. However, in the circuit of this embodiment, two types of clock pulses CPo/M and CPo/N are prepared as described above.

A high-speed clock pulse CPo/M is used during the rising state of the input signal, and a low-speed clock pulse CPo/N is used during the -gender-fixed state. Therefore, both high-speed responsiveness and accurate level control are ensured.

In addition, in this embodiment, the level detector 20 is used as a peak detector because it is necessary to prevent distortion of the output waveform as much as possible.
A peak detector is employed, and this peak-to-peak detector uses capacitors 23a and 23b for holding peak values, as shown in FIG. For this reason, it is possible to relatively quickly follow an increase in the output signal QO due to an increase in gain, but conversely, when the output signal QO increases when the gain decreases,
(It is not possible to follow the decrease in , at high speed.

However, in the circuit of this embodiment, each capacitor 2:41,
Radiation circuits 24a and 24 are connected in parallel to 23b, respectively.
b.

When the carry output KD is generated from the first up/down counter 42, the discharge circuits z4a and stb are made conductive and the "C"j differential f23a is activated.

23b is forced to rapidly discharge. Therefore, if gain reduction control is performed.

Capacitor 23a of the peak-to-peak detection circuit.

23b is immediately and forcibly discharged as shown in FIG. 6, for example. Therefore, the detection output E of the peak-to-peak detection circuit.

output signal e at high speed. Follow the level of Therefore, high-speed response is possible while suppressing signal distortion. In FIG. 6, the output signal eo is 0M5K (Qaussian Minimum 5ift Ke
ying ) is shown.

Furthermore, if a peak-to-peak detection circuit is used as the level detector 20 as in the circuit of this embodiment.

If 87N of the input signal ei deteriorates, the peak-to-peak detection circuit may respond to noise peaks and perform incorrect gain control.

However, in this embodiment, the deterioration of 87N is detected by the 87N monitoring circuit (not shown), and in response to this, the gain holding signal Pa (''L''
level) is generated, the carry output KU and carry output KD issued from the first up/down counter 42 thereafter are blocked by AND gates 44a, 44b and supplied to the second up/down counter 43. Not done. FIG. 7 shows this situation, and the broken line in FIG. 1 is the blocked signal. Therefore, even if the first up/down counter 42 malfunctions due to noise or the like, the effect will not affect the variable gain amplifier 10, and the gain will remain at the value at which the S/N is high. . Therefore, the level control stability is extremely high.

In this way, the automatic level control circuit of this embodiment can linearly control the gain of the variable gain amplifier 10 over the entire gain change range, and can reduce output signal distortion.
Moreover, it is possible to maintain the gain even when the drop is 87N, and it is possible to maintain both high-speed response and accurate level control.Furthermore, it achieves high-speed response even though it uses a peak-to-peak detection circuit. can do.

Note that the present invention is not limited to the above embodiments.

For example, the number of variable steps of a variable gain amplifier may be set to more than 10 steps, and in this way, the interval between each step can be further narrowed, and as a result, the level change error in the steady state can be reduced. I can do it. In addition, the frequency of the clock pulse CP is set to three or more types.

By selectively using these frequencies, various modifications can be made without departing from the spirit of the invention.

〔Effect of the invention〕

As detailed above, the present invention provides a variable gain amplifier having a configuration in which the gain can be varied in multiple stages at predetermined intervals, and comparing the detection level of the output signal with a reference level to determine the magnitude relationship.
According to this result, the clock is counted up or down, and the gain of the variable gain amplifier is varied according to the counted value.

Therefore, according to the present invention, it is possible to provide an automatic level control circuit that can reduce signal distortion and perform highly accurate level control.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional automatic level control circuit, FIGS. 2 to 7 are diagrams for explaining an automatic level control circuit according to an embodiment of the present invention, and FIG. 2 is a circuit configuration of the same circuit. 3 is a circuit configuration diagram of the level detector, FIG. 4 is a circuit configuration diagram of the clock generator, and FIGS. 5 to 7 are timing diagrams used to explain the operation. DESCRIPTION OF SYMBOLS 10... Variable gain amplifier, 151-159... Resistor, 20... Level detector, 26a... Negative peak value detection circuit, 26b... Positive peak value detection circuit. 24a, 24b...Discharge circuit, SO...Comparator. 40... Control unit, 41... Clock generator, 42.
...First up/down counter % 43...Second up/down counter, 47...Return circuit. Applicant's representative Patent attorney Takeshi Suzue Syllable 1

Claims (5)

[Claims] (1) A variable gain amplifier whose gain can be thermally varied in multiple steps over a predetermined period of time, a level detector that detects the output signal level of this variable gain amplifier, and a level detector that compares the detection output of this level detector with a reference level. A comparator that generates a comparison output depending on the magnitude relationship, and a control unit that performs up-counting or down-counting of clock pulses depending on the comparison output and varying the gain of the variable gain amplifier according to the count value. An automatic level control circuit characterized by: (2) The control section is equipped with a gain holding means for keeping the gain of the variable gain amplifier fixed according to the state of the input signal to the variable gain amplifier. Lebel control Wj path. (3) The control unit initially sets the gain of the variable gain amplifier to the center value of its variable range by setting the count value to a predetermined value before the input signal is supplied to the -il variable gain amplifier. An automatic level control circuit according to claim 1. (4) The level detector consists of a peak detector equipped with a means for forcibly discharging the capacitor holding the detected output value to initialize the detected output value in a short period of time when the gain of the variable gain amplifier changes. An automatic level control circuit according to claim 1. (5) The control section selects and counts high-speed clock pulses during the rising period of the variable gain amplifier, and selects and counts low-speed clock pulses during the stable period. Automatic level control circuit as described.