JPH0568127B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to an improvement in an automatic level control circuit (ALC circuit) used, for example, for stabilizing the detection level of a data transmission device. [Technical Background of the Invention] Conventionally, this type of circuit detects the level by rectifying the output signal _e0 of a variable gain amplifier 1 with a level detector 2, as shown in FIG. Comparator 3 compares E ₀ with reference level Er, and the error voltage ΔV obtained through integrator 4 is supplied to FET 1a of variable gain amplifier 1 to control the gain by varying its resistance value. , a device is known in which the level of the output signal e ₀ is made constant by this. With such a circuit, for example, when the input signal ei decreases, the output signal e ₀
Since the detection level E ₀ of is lowered, the error voltage ΔV obtained in comparison with the reference level Er is also lowered, and the resistance value of the FET 1a of the variable gain amplifier 1 is thereby reduced. Then, the gain G is the negative feedback resistor 1b
When the resistance value of FET1a is R _F and the resistance value of FET1a is R _S , it can be expressed as G = 20 log (1 + R _F /R _S ) [dB]. As a result, the input signal ei
is amplified to a greater extent, and the amplitude of the output signal e ₀ is held at a constant value. Note that when the input signal ei increases, an operation opposite to the above operation is performed, and the level of the output signal e ₀ is made constant. [Problems with Background Art] However, in such a conventional circuit, the gain of the variable gain amplifier 1 is controlled by varying the resistance value of the FET 1a. Therefore, the change in gain is dominated by the resistance change characteristics of FET1a, and generally the channel resistance of FET is 100mV or more when the drain-source voltage is 100mV or more.
Since it is a straight line only within a range of about 200mV,
There was a drawback that signal distortion occurred in the output signal e ₀ due to nonlinearity. [Object of the Invention] An object of the present invention is to reduce signal distortion and perform high-precision level control, and to respond at high speed to not only increases but also decreases in the output signal. An object of the present invention is to provide an automatic level control circuit that can improve performance. Another object of the present invention is to enable high-speed response to the rising edge of an input signal and to accurately detect the level when the input signal is stable, thereby achieving high-speed response and level control. The object of the present invention is to provide an automatic level control circuit that has both high stability and high stability. [Summary of the Invention] In order to achieve the above object, the present invention provides a variable gain amplifier whose gain can be varied in multiple stages at predetermined intervals, a capacitor that holds a detected output value, and a variable gain amplifier that can change the gain of the variable gain amplifier. Sometimes, a level detector is provided which has means for forcibly discharging this capacitor and initializing the detected output value in a short period of time. Then, the level detector detects the output signal level of the variable gain amplifier, compares the detected value with the reference level to determine the magnitude relationship, and depending on the result, counts up or down the clock pulse. , the gain of the variable gain amplifier is varied according to the count value. In order to achieve the other objects mentioned above, another aspect of the present invention provides a clock pulse that generates a high-speed first clock pulse having a predetermined frequency and a second clock pulse that is slower than the first clock pulse. Equipped with a generator. and,
During the rising period of the variable gain amplifier, the first clock pulse is selected and the first clock pulse is counted up or down depending on the comparison output of the comparator, while during the stable period of the variable gain amplifier, the first clock pulse is counted up or down depending on the comparison output of the comparator. The second clock pulse is counted up or down depending on the comparison output of the comparator. The gain of the variable gain amplifier is then varied according to these count values. [Embodiment of the Invention] FIG. 2 shows the configuration of an automatic level control circuit in an embodiment of the present invention, in which 10 is a variable gain amplifier, 20 is a level detector, 30 is a comparator, and 4
0 indicates a control unit. The variable gain amplifier 10 is composed of an amplifier 11, a feedback resistor 12 that feeds back its output signal e ₀ , and nine resistors 151 to 159 that together with the feedback resistor 12 determine the gain of the amplifier 11. These resistors are connected in series with the switching FETs 161 to 169, and only one of the FETs becomes conductive, so the voltage gain G _N is given by the following equation. G _N = 20 log (1 + R _F /R _S ) [dB] However, R _F : Resistance 12 G _N : G ₁ , G ₂ ,..., G ₉ R _SN : R _S1 (Resistance 151), R _S2 (Resistance 152) ，
...R _S9 (Resistor 159) 1-step gain error ΔG = G _N - G _N-1 = 20 log (1 + R _F /R _SN ) -20 log (1 + R _F /R _{S (N-1)} ) [dB] Level The detector 20 is composed of a peak-to-peak detection circuit and is constructed as shown in FIG. That is, the circuit has a buffer amplifier 21
a, a diode 22a, a capacitor 23a, a discharge circuit 24a of this capacitor 23a, and a negative peak value detection circuit 26a from the buffer amplifier 25a.
A positive peak value detection circuit 26b is constructed from the buffer amplifier 21b, the diode 22b, the capacitor 23b, its discharge circuit 24b, and the buffer amplifier 25b. and,
The detection outputs of these peak value detection circuits 26a and 26b are led to the inverting input terminal (-) and non-inverting input terminal (+) of the differential amplifier 28 via resistors 27a and 27b, respectively, and the difference output is detected as a peak value.・
It is sent as peak detection output E ₀ . Also,
In this circuit, a carry output KD from a control section 40, which will be described later, is applied to switching transistors 29a and 29b of discharge circuits 24a and 24b, thereby forcibly discharging capacitors 23a and 23b. The comparator 30 includes a comparator 31 and a reference power source 3.
2, the peak-to-peak detection output E ₀ from the level detector 20 is compared with the reference level Er, and when E ₀ > Er, a comparison output of "H" level is generated, and when E ₀ < Er At this time, a comparison output of "L" level is generated. The control section 40 includes a clock generator 41, a first up/down counter 42, and a clock generator 41, a first up/down counter 42, and a
a second up-down counter 43 that counts the carry down output KU and carry output KD from;
Two units that prevent the supply of the down and carry outputs KU and KD to the second up-down counter 43 when a gain holding signal (“H” level) PS is generated from a control signal generation circuit (not shown). The AND gates 44a and 44b and the carry and carry outputs KU and KD are supplied to the first up-down counter 42 via the OR gate 45 and the delay circuit 46, and the count value of this counter 42 is set to the initial value. It is composed of a return circuit 47 for returning to the state. The first up-down counter 42 counts up or down the clock pulse CP generated from the clock generator 41 according to the comparison output level of the comparator 30. On the other hand, the second up-down counter 43
The carry-down output KU and carry-out output KD of the up-down counter 42 are up-counted and down-counted, respectively, and "H" level signals are generated from the output terminals _S1 to _S9 corresponding to the count values. Further, as shown in FIG. 4, for example, the clock generator 41 divides the reference clock _CP0 generated by the reference clock generator 410 into two clocks with different frequency numbers.
The frequency is divided by leading to two frequency dividers 411 and 412, and the divided output is selectively selected by a selection circuit 413 and outputted as a clock pulse CP. Note that the selection circuit 413 generates a frequency selection signal generated from a control signal generation circuit (not shown).
Operates by FS. Furthermore, when the initialization signal RON is generated from a control signal generation circuit (not shown), the control unit 40
each of the first and second up-down counters 42,
The count value of 43 is initialized to the center of the count range. Next, the operation of the circuit configured as described above will be explained with reference to the timing diagrams of FIGS. 5 to 7. First, a rising state after a signal is input until the output signal level becomes stable will be described. When the input signal ei arrives and the initialization signal ROM is generated from a control signal generation circuit (not shown), the first
and second up-down counters 42, 43
The count values of are set to "3" and "5", respectively, which are the median values within the count range. Therefore, the second up-down counter 43 outputs an "H" level control signal from the output terminal S ₅ and the FET 165 becomes conductive. Amplify the input signal ei with a gain _G5 determined by However, at this time, the detection level E ₀ of the output signal e ₀ obtained from the variable gain amplifier 10 is equal to the reference level Er
Since E ₀ <Er, the comparison output CS of the comparator 30 is “L”
It has become a level. Therefore, the first up-down counter 42 enters the down-count mode and counts down the clock pulse CP. As a result, the count value CT1 of the first up-down counter 42 changes from "3" to "2" to "1".
Then, when the count value CT1 becomes "0",
Decrement output from the first up-down counter 42
KU is generated and this output KU is the AND gate 4
4a to the up terminal U of the second up down counter 43. As a result, the second up-down counter 43 sets the count value CT2 to "6".
It counts up and outputs an "H" level signal from the output terminal _S6 . Therefore, the variable gain amplifier 10
When the FET 166 becomes conductive, the gain becomes a value determined by this resistor 156 and the feedback resistor 12.
Let's say _G6 . Therefore, the gain increases by one step ΔG, and thereby the level of the output signal _e0 increases by a constant value as shown in FIG. On the other hand, the above digit down output
KU is applied to the first up-down counter 42 as a return signal LS via a return circuit 47. Therefore, the count value CT1 of the first up-down counter 42 returns to the initial value "3". When the count value CT1 returns to "3", the detection level _E0 of the output signal _e0 becomes the reference level as shown in Figure 3.
As long as E ₀ <Er for Er, the first up-down counter 42 repeats the above counting operation to obtain the count value CT1.
Generates down-digit output KU every time becomes "0".
Then, the second up-down counter 43 is incremented by this down-down output KU, and the selected positions of the resistors 151 to 159 of the variable gain amplifier 10 are stepped up in order to increase the gain by a fixed amount ΔG to G ₇ and G ₈ . let This gain increase reduces the detection level of the output signal e ₀
When E ₀ becomes E ₀ >Er with respect to the reference level Er, and as a result, the comparison output CS of the comparator 30 becomes “H” level, the first up/down counter 42 enters the up count mode and increases the clock pulse CP. Start counting. Also, at this time, if the above relationship E ₀ > Er is achieved,
A control signal generation circuit (not shown) determines that the rising state of the input signal ei has ended and outputs the control signal.
FS becomes “L” level. Therefore, the selection circuit 413 of the clock generator 41 selects the output of the frequency divider 411 instead of the frequency divider 412, and as a result, the first up-down counter 42 receives the high-speed clock CPO/ A slow clock CPO/N is supplied in place of M. Therefore, from then on, the counting operation of the first up-down counter 42, that is, the variable gain control operation of the variable gain amplifier 10, becomes slower than during the rising period. Next, the stable state will be explained. Due to the count-up operation of the first up-down counter 42, the count value CT1 becomes "6".
Then, the counter 42 outputs a carry KD.
is generated, and the count value CT2 of the second up-down counter 43 is counted down to "7" by this carry output KD. As a result, the selected positions of the resistors 151 to 159 of the variable gain amplifier 10 are also stepped down to 157, thereby increasing the gain.
G becomes ₇ and decreases by a certain value. When the detection level E ₀ of the output signal e ₀ becomes E ₀ <Er again due to this decrease in gain, the first up-down counter 42 counts down the clock pulse CP, and the count value CT1 becomes "0". The second up-down counter 4 generates a down-down output KU at the point in time.
The count value CT2 of 3 is set to "8". As a result,
The gain of variable gain amplifier 10 again steps up to a higher value G ₈ corresponding to resistor 158. From then on,
Depending on the comparison output CS level of the comparator 30, the count value CT2 of the second up-down counter 43 is
"7" and "8" are repeated at a speed according to the clock pulse CP, and the output signal e ₀
also changes. Therefore, the output amplitude of the output signal e ₀ is stabilized within an error of one step of the gain.
Further, since the conduction resistance of the FET is extremely small compared to the resistors 151 to 159 and can be ignored, signal distortion due to nonlinearity of the FET, which has been a problem in conventional circuits, does not occur, and even if it occurs, it is extremely small. Furthermore, in the circuit configured above, the clock pulse
The lower the frequency of CP, the more accurately the level detector 20 can detect peak-to-peak values, but on the other hand, the response speed becomes slower. On the other hand, if the frequency of the clock pulse CP is increased in order to increase the response speed, the first peak value will be reached before the true peak value of the output signal e ₀ arrives.
The probability that the up-down counter 42 will perform a counting operation in the wrong direction increases, which may lead to deterioration of level stabilization performance. However, in the circuit of this embodiment, two types of clock pulses CPO/M,
CPO/N and use a fast clock pulse CPO/M during the rising state of the input signal, while a slow clock pulse during steady state.
I am using CPO/N. Therefore, both high-speed responsiveness and accurate level control are ensured. In addition, in this embodiment, the level detector 20 is
A peak-to-peak detector is used as a
This peak-to-peak detector has capacitors 23a and 23 for holding the peak value as shown in FIG.
b is used. Therefore, it is possible to relatively quickly follow an increase in the output signal e ₀ due to an increase in gain, but it is also possible to follow a decrease in the output signal e ₀ at a high speed when the gain is decreased. I can't.
However, in the circuit of this embodiment, each capacitor 23
Discharge circuits 24 are connected in parallel to a and 23b, respectively.
a and 24b are provided, and when a carry output KD is generated from the first up-down counter 42, the discharge circuits 24a and 24b are made conductive to forcibly rapidly discharge the capacitors 23a and 23b. . Therefore, when gain reduction control is performed, capacitor 2 of the peak-to-peak detection circuit
3a and 23b are immediately and forcibly discharged as shown in FIG. 6, for example. Therefore, the detection output E ₀ of the peak-to-peak detection circuit follows the level of the output signal e ₀ at high speed. Therefore, high-speed response is possible while suppressing signal distortion. Note that in Figure 6, the output signal e ₀ is GMSK (Gaussian Minimum
(Sift Keying) detection waveform. Furthermore, as in the circuit of this embodiment, the level detector 2
If a peak-to-peak detection circuit is used with the input signal ei set to 0, if the S/N of the input signal ei deteriorates, the peak-to-peak detection circuit may perform incorrect gain control in response to the noise peak. However, in this embodiment, an S/N monitoring circuit (not shown) detects S/N deterioration, and in response, a control signal generating circuit (not shown) sends a gain holding signal PS.
(“L” level) is generated, the first
The carry output KU and carry output KD issued from the up-down counter 42 are blocked by AND gates 44a and 44b and are not supplied to the second up-down counter 43. FIG. 7 shows this situation, and the broken lines ◯ and ◯ in the figure indicate the blocked signals. Therefore, even if the first up-down counter 42 malfunctions due to noise or the like, the effect will not affect the variable gain amplifier 10, and the gain will be
The value when N is high is maintained. Therefore, level control stability is extremely high. In this way, with the automatic level control circuit of this embodiment, the variable gain amplifier 10
It is possible to control the gain linearly, reduce output signal distortion, maintain the gain even when the S/N decreases, and ensure both high-speed response and accurate level control. Despite using the upper peak-to-peak detection circuit, high-speed response can be achieved. Note that the present invention is not limited to the above embodiments. For example, the number of variable steps of a variable gain amplifier may be set to 10 or more. In this way, the interval between each step can be further narrowed, and as a result, the level change error during steady state can be reduced. I can do it. Also clock pulse
There may be three or more types of CP frequencies, and these frequencies may be used selectively. others,
Circuit configuration of variable gain amplifier, level detector, comparator, and control section (with microprocessor)
Various modifications may be made without departing from the spirit of the present invention. [Effects of the Invention] As detailed above, the present invention provides a variable gain amplifier whose gain can be varied in multiple steps at predetermined intervals, a capacitor that holds a detection output value, and a capacitor that holds a detection output value, and a A level detector is provided that has means for forcibly discharging this capacitor and initializing the detected output value in a short period of time.
Then, the level detector detects the output signal level of the variable gain amplifier, compares the detected value with the reference level to determine the magnitude relationship, and depending on the result, counts up or down the clock pulse. , the gain of the variable gain amplifier is varied according to the count value. Therefore, according to the present invention, even when the output signal level of the variable gain amplifier increases or decreases, it is possible to detect the level by following these level changes at high speed. Therefore, highly accurate level control can be performed with reduced signal distortion, and level control with excellent responsiveness can be performed. On the other hand, in another aspect of the present invention, the control section includes a clock pulse generator that generates a high-speed first clock pulse having a predetermined frequency and a second clock pulse that is slower than the first clock pulse. Then, during the rising period of the variable gain amplifier, the first clock pulse is selected and the first clock pulse is counted up or down according to the comparison output of the comparator, while during the stable period of the variable gain amplifier. , the second clock pulse is selected, the second clock pulse is counted up or down according to the comparison output of the comparator, and the gain of the variable gain amplifier is varied according to these count values. are doing. Therefore, according to the present invention, it is possible to follow changes in the input signal at high speed by using a high-speed clock pulse when the input signal rises, and when the input signal level is stable, the signal level can be adjusted by using a low-speed clock pulse. can be detected accurately. Therefore, it is possible to provide an automatic level control circuit that has both high-speed responsiveness and high level control stability.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional automatic level control circuit, FIGS. 2 to 7 are diagrams for explaining an automatic level control circuit according to an embodiment of the present invention, and FIG. 2 is a circuit configuration of the same circuit. 3 is a circuit diagram of the level detector, FIG. 4 is a circuit diagram of the clock generator, and FIGS. 5 to 7 are timing diagrams used to explain the operation. DESCRIPTION OF SYMBOLS 10... Variable gain amplifier, 151-159... Resistor, 20... Level detector, 26a... Negative peak value detection circuit, 26b... Positive peak value detection circuit, 24
a, 24b...discharge circuit, 30...comparator, 40...control unit, 41...clock generator, 42...first up-down counter, 43...second up-down counter, 47...demodulation circuit.

Claims (1)

[Claims] 1. A variable gain amplifier whose gain can be varied in multiple steps at predetermined intervals; an output signal level of the variable gain amplifier is detected and the detected value is held in a capacitor;
a level detector having a means for forcibly discharging the capacitor to initialize the detected output value in a short period of time when the gain of the variable gain amplifier changes; The present invention further comprises: a comparator that generates a comparison output according to the relationship; and a control section that up-counts or down-counts clock pulses according to the comparison output and varies the gain of the variable gain amplifier according to the count value. Features an automatic level control circuit. 2. The automatic level control circuit according to claim 1, wherein the control section includes gain holding means for holding the gain of the variable gain amplifier fixed in accordance with the state of the input signal to the variable gain amplifier. 3. A variable gain amplifier whose gain can be varied in multiple steps at predetermined intervals, a level detector that detects the output signal level of this variable gain amplifier, and a detected output value of this level detector that is compared with a reference level to determine the magnitude relationship. a comparator that generates a comparison output according to the frequency of the variable gain amplifier; a clock pulse generator that generates a high-speed first clock pulse having a predetermined frequency and a second clock pulse that is slower than the first clock pulse; During the rising period, the first clock pulse is selected and counted up or down depending on the comparison output of the comparator, while during the stabilization period of the variable gain amplifier, the second clock pulse is selected. and a control section that selects the second clock pulse and counts up or down the second clock pulse according to the comparison output of the comparator, and varies the gain of the variable gain amplifier according to these count values. Features an automatic level control circuit.