JPS6313409A - Automatic gain control circuit - Google Patents

Abstract

PURPOSE:To obtain an AGC circuit improved in distortion factor without deterioration in S/N by applying automatic gain control in a form changing negative feedback quantity and applying feedback quantity control by means of a circuit whose resistor is added or removed by means of a switch. CONSTITUTION:A high frequency amplifier (RFA) consists of an operational (differential) amplifier. A received output of an antenna ANT is supplied to the RFA through a band pass filter BPF passing through a broadcast wave frequency band only and amplified, and subject to frequency conversion, intermediate frequency amplification and detection or the like in a processing circuit SP, and led to a speaker through a low frequency amplifier. The AGC circuit consists of a level detection circuit P2a, a low pass filter P2b, a comparator P2c, a controller CTL1 and a feedback quantity control circuit FC1 of RFA. Since automatic gain control is applied by changing the negative feedback quantity of the negative feedback amplifier depending on the signal level in such a way, the distortion factor is improved and the deterioration in S/N is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic gain control circuit used in a receiver.

[Conventional technology]

Automatic gain control (AGC) circuits are widely used in radio receivers to prevent variations in audio output due to variations in electric field strength. The AGC circuit in the case of an AM tuner is
Shown in Figure. Transistor Q1, resistor R7, and capacitor C2 represent a high-frequency amplification stage, where the antenna input is amplified and then enters a processing circuit SP for frequency conversion, intermediate frequency amplification, detection, etc., and the detected output is sent to a low-frequency amplification stage (not shown). The detected output is also input to the speaker via the resistor R.
1 to R: input to the transistor Q2 through a low-pass filter LPF consisting of a +, -t-capacitor C1.

The transistor Q2 constitutes a comparison and drive circuit together with the resistors R4 and R5, and when the output of the LPF section exceeds the base-emitter voltage VBE of the transistor Q2, it begins to conduct, forming a shunt to the resistor R4, and forming a shunt to the resistor R4. , R5 lowers the divided voltage output of the power supply Vcc. This divided voltage output enters the base of transistor Q1 via resistor R6, changing the base bias of the transistor and thus changing the gain of the transistor. In many cases, reverse AGC is used, and by lowering the bias current, the gain of the high frequency amplification stage is lowered.

[Problem that the invention seeks to solve]

In this case, the gain decreases and the distortion in the next stage decreases, but
Distortion in the high frequency amplification stage Q1 is not improved.

Therefore, it may be improved by adding a damping circuit to the input. In either case, the S/N decreases.

Furthermore, the present invention aims to provide an amplifier and an AGC circuit with a good distortion factor.

Increasing the amount of negative feedback in a negative feedback amplifier improves the distortion rate,
There is no decrease in S/H. In this case, a distortion-free variable resistance element is required, but this can be constructed from a resistor and a switch, and a resistance switching type variable resistance can be integrated into an IC, making it easy to miniaturize the circuit. The present invention was made focusing on this point.

[Means for solving problems]

FIG. 1 shows the configuration of the present invention. RFA is Q+ in Figure 2
A high frequency amplifier is schematically shown as , and in this circuit it consists of an operational (differential) amplifier. The received output of the antenna ANT enters the high frequency amplifier RFA through a band pass filter BPF that passes only the broadcast wave frequency band, and is amplified by the post-processing circuit SP.
The signal undergoes frequency conversion, intermediate frequency amplification, detection, etc., and is guided to a speaker through a low frequency amplifier (not shown). The detection output is also used for AGC, but in the present invention, this AGc time is used as a level detection circuit P 2 a s low-pass filter P2b, comparator P2c, controller CTL+, RFA
It consists of a feedback amount control circuit FC+. Feedback amount control circuit P
The CI consists of a plurality of resistors and switches that connect/open them to each other and connect/open them to ground, and the controller CTL+ produces a multi-bit output for controlling the switches.

[Effect]

Since this AGC circuit performs automatic gain control by changing the amount of negative feedback of the negative feedback amplifier according to the signal level, the distortion factor is improved and there is no drop in S/H.

Control is performed by detecting the level of the detection output and determining whether Vil through the LPF is greater than or equal to the reference value Vr1, and when this is the case, the controller CTL+ gives a multi-bit signal that increases the feedback amount to the feedback amount control circuit FC1. , the following is done by reversing this. The low-pass filter P2b smoothes the detected output level and produces an output Vi1 having an average signal level over a period of several tens of m5. Specific examples of these circuits and details of their operations will be described below.

〔Example〕

FIG. 3 shows a specific example of FIG. 1. As shown in Figure 5, the output of the antenna ANT is passed through the BPF, amplified by the RFA, converted to a digital signal by the analog/digital converter ADC, and then tuned, detected, noise removed, and processed by the digital signal processor DSP. Adjust the high and low frequencies and return it to an analog signal using a digital/analog converter DAC.
This is applied to a type of radio receiver that amplifies with a power amplifier PA and sounds through a speaker SP, and a concrete example of the main part, which was proposed separately, is shown in Fig. 4.

First, to explain Fig. 4, BPF is a broadcast frequency band as shown in the figure, 530KHz to 1620KH for AM broadcasting.
Pass through the z range and block everything else. The high frequency amplifier RFA, which is an analog amplifier, is provided with feedback amount control circuits PCI and FC2 in its feedback path. Feedback amount control circuit (F
BC) PCl, Fe2 are resistors R1, as shown in FIG.
R2, . . . are connected to switches Sl, S2.・・・・・・
It is of the type that can be inserted/removed and connected/opened to the ground at . . . Switches Sl, S2°, . . . are opened and closed by the output of the controller CTL. In this example, controller CTL outputs 12 bits and switches 31 . S2.
There are 12111...

The controller outputs S1 to S12 constitute a 12-bit binary code (BCD), which is oooooooo.

oooo~111111111111, the resistance value R+ is set such that the transmission amount changes linearly as shown in FIG. 6(b).

Select R21... Feedback amount control circuit F
If the transmission amount (negative feedback amount) of C1 and Fe2 is β, the gain CV of the high frequency amplifier RFA is l/β, which is determined by the resistance value and has little distortion.

The feedback amount control circuit PCI is for AGC (same as the PCI in FIG. 1), and determines the amount of transmission according to the long-term (several tens of m5) average of the input level. The feedback amount control circuit FC2 is for data (DSP), and is controlled according to the input level at each moment, and the code value of Fe2, which is the switching point between H and L of the output of the comparator CO, is set to A. /Output as a D conversion value.

That is, the comparator GOMP compares the output Vi of the high frequency field device RFA with the reference voltage Vr, generates H and L outputs Vo according to the H (high) and L (low), and inputs them to the controller CTL2. The output Vo of the controller CTL2 is Vi>V
When Vo is at H level indicating r, the 12-bit output is successively changed in the direction of increasing the amount of feedback, and when Vo is at L level indicating Vi<Vr, the 12-bit output is successively changed in the direction of decreasing the amount of feedback. In the end, Vi=Vr. Vi
=Vr, the feedback amount corresponds to the input voltage of the amplifier RFA, and the 12-bit output of CTj2 at this time is nothing but the A/D converted value of the input voltage. The 12-bit output of controller CTL2 is sent to the DSP.

The digital signal processor DSP performs channel selection processing, AM detection, etc. based on the 12-pin A/D conversion value input from the controller 12b, and the detection output is converted to an analog signal by the digital/analog converter DAC, and the power amplifier After being amplified by the PA, it is added to the speaker SP. Further, the AGC processing section generates a bit indicating the input signal level H or L, and adds that one bit to the AGC controller CTL+. As mentioned above, this 1 bit indicates the H and L of the average level of 10m5 input signals.
The controller CTL+ generates a 12-bit output that controls the feedback amount control circuit in such a way that if the bit is H, the amount of feedback is increased, and if the bit is L, the amount of feedback is decreased. With this control, the output Vi of the amplifier RFA remains constant over a long time span.

As shown in FIG. 3, the AGC processing section P2 in the DSP includes a section P2a connected to the channel selection processing section P1 to detect the input signal level, and a low-pass filter P connected to the level detection section.
2 b % Set the output Vil of the filter to the reference value Vr1
A comparator P2C is provided which outputs the 1 bit indicating the HIL by comparing it with .

Further, the AGC feedback amount control circuit CTL+ includes an up/down counter UDC, which counts down the clock CLK when the 1-bit output from the comparator P2c is at H level indicating Vil > Vrl, and the 1-bit output counts down the clock CLK. Clock CLK when at L level indicating Vil<Vrl
is counted up, and the count value of the counter becomes a 12-bit output to the PCI. The clock CLK determines the up/down speed and, in turn, the response speed of the AGC.

In this analog/digital conversion circuit ADC, AGC
In the system, for a long time (several tens of meters) width, the constant Vi is A
/D conversion, and because the A/D conversion value is obtained in the form of the Fe2 switch on/off signal to obtain the amount of RFA feedback necessary to make the Vi constant at each moment, the level fluctuation It is possible to A/D convert a large input signal without distortion.

〔Effect of the invention〕

As explained above, the present invention performs automatic gain control by changing the amount of negative feedback, and also controls the feedback amount using a resistor insertion/removal type circuit using a switch, so that the distortion factor is improved and the S/H Thus, an AGC circuit without a drop in performance can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of the present invention, Fig. 2 is a conventional AGC circuit diagram, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 4 is the main part structure of a radio receiver using DSP. FIG. 5 is a block diagram showing the overall configuration of the radio receiver, and FIG. 6 is an explanatory diagram of the feedback amount control circuit. In the drawing, RFA is a differential amplifier, PCI is a feedback amount control circuit,
P2c is a comparator, CTL+ is a controller, and sp is a processing circuit. Applicant Fujitsu Ten Ltd. Representative Patent Attorney Minoru Aoyagi s1 Figure 4 NT Figure 5 Figure 6

Claims (1)

[Claims] An automatic gain control circuit that controls the average level of a signal to a predetermined value, comprising: an amplifier (RFA) that amplifies the signal; a plurality of resistors inserted in the negative feedback circuit of the amplifier; A feedback amount control circuit (FC1) consisting of switches that are connected/opened to each other and connected/opened to the ground, and a comparator (FC1) that generates an H or L level output depending on whether the average level of the signal is higher or lower than a reference value. P2c); and a controller (CTL_1) that outputs a multi-bit signal instructing switching on and off of the feedback amount control circuit according to the output of the comparator.