JPS6086671A - Vector processing device - Google Patents

Abstract

PURPOSE:To prevent degradation of the division capacity by performing division in a high speed in the pipeline system when vector data is divided in the reciprocal approximation system where multiplication is repeated to obtain a quotient. CONSTITUTION:A divided N and an approximate reciprocal R0 are supplied successively at one-machine cycle pitch through data busses 13 and 19 and data busses 14 and 20 respectively, and they are set to data registers 48 and 49 through data registers 40 and 41 or the like respectively. These numbers are subjected to multiplication processing in the pipeline system with multiple generating circuits 61 and 62, CSA trees 64 and 65, and a parallel adder 67, and a result N1 is obtained in a data register 77. A result R1 calculated by a pipeline multiplier is sent through a data bus 16 and is set to a data register 100. The result N1 calculated by a pipeline division adding circuit is set to a data register 101, and a pipeline multiplier 3 sends out the multiplication result as a quotient Q. Thus, division is performed in a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a vector processing device that processes division of vector data at high speed in a pipeline.

[Background of the invention]

In a vector data processing device that performs a series of operations on a set of numbers (operation 'x'), vector data supplied one after another is processed in a pipeline, and the operation results ffi! Pipeline performance: jlL
They often have a container. Kasho.

A pipeline arithmetic unit that performs subtraction and one multiplication is already known, but there is no example of one that performs division by two pipes. Therefore, when considering a program that is executed by a combination of several arithmetic operations, operations that do not include division are processed at high speed in the pipeline, but division J! In calculations involving X, the performance may be extremely degraded, so it is necessary to process the division X at high speed in a pipeline.

The reciprocal approximation method is widely used as an arithmetic method for processing division at high speed. In this method, when the dividend is N and the divisor is 91 songs as Q, then DxRoxR1×・
R1, R2 that brings ... closer to 1
・・・・・・・・・・・ Q〜NXRIOXRI
X...... is used.

For the first value, calculate the reciprocal of D by calculating the divisor and using the approximate reciprocal table. The accuracy of ⇠◎, which is an approximate reciprocal of the divisor, depends on the size of the approximate reciprocal table, but let us assume that the accuracy is as shown in the following equation.

DXRo=1±ε 0×ε< 1 (1) Therefore, if R1=2 DXRo (2), then R1=2−(1±ε)=1+ε (3), and DXRo X&= (1±ε) (1〒g)−1−
ε20kuε"<1 (4) Next, if 几2 = 2 DXRo
6) D X Ro X RI X R2= (1-ε2
)(1+62)=1−ε40×ε′<1+71. By repeating the same operation, υ, RoXRt
It can be set as x-...xn, →1(8).

Now, if the precision of 64 is less than the number of effective digits of data representation of the target vector processing device, then Q=N x Ro x Rt x R2uol can be used as the quotient.

In this way, the source material using the reciprocal approximation method is to prepare in advance an approximate reciprocal of the divisor, which has a lower precision than the number of effective digits for data expression, and then repeat the rice cracker process to improve the accuracy of the reciprocal and create a song. That's what you're trying to get.

In a processing device with a high-speed multiplier, the reciprocal approximation method is an effective '0Klt method that processes division JJL at high speed, but on the other hand, the pipeline method processes division JI4. When performing the desired Ff! Since it is necessary to connect multiple multipliers in series to match the number of multiplications required to obtain the result, the scale of the circuit required to perform division x' in a pipeline becomes enormous.

For this reason, in conventional vector processing devices, the desired 1
In rare cases, the division is realized by repeatedly using a single pipeline terminator a number of times equal to the number of squares required to obtain the thigh.

That is, when the temporary divisor is N1, the quotient Q is obtained in the following four steps.

Step 1: 1 bowl of approximate reciprocal 0 to 1/D μυ Step 2: Improving accuracy of approximate reciprocal Rt = (2DXRo) u7) Step 3: Approximating numerator Ns = NXRo (13 Step 4: Improving accuracy of Q = =N+XRx (141 FIG. 1 shows the floating point data representation format used at this time.

Floating point data is processed using 1 bit to represent the sign, 15 bits to represent the exponent, and 48 bits to represent the mantissa, for a total of 64 bits. In this conventional technology, the effective representation of the data of the mantissa is achieved by removing the nose using the reciprocal approximation method.
It is sufficient to secure a 48-bit memory, and for this purpose, the four-step operation from step 1 to step 4 is performed to divide 'J4. has been realized.

In step 1, an approximate reciprocal number RO of the divisor is calculated with a precision of 30 bits. Next, in step 2, improve the accuracy to 47 bits and set it to Rs', and in steps 3 and 4, NXRO
I play with XR and serve a bowl of IiQ. Figure 2 shows how the accuracy is improved in this division process.

In the prior art, the vector data division process consisting of the four steps described above is realized by the following instructions and hardware configuration.

The process of creating an approximate inverted ridge O with an accuracy of 30 pits in step 1 is a Floating process prepared just for this process.
point reciprocal al)l)ro
This is done using the xim3ti□n instruction.

The process in step 2 is performed using the l(, eciproc211terations command, which is prepared only for this process.

The processing in steps 3 and 4 is a normal floating/"
・Processed using several-point vector multiplication instructions.

Conventionally, a floating-point multiplication unit and a floating-point reciprocal approximation unit are used for the above processing.The floating-point multiplication unit is an arithmetic unit used to process the vector multiplication Jl instruction, which is executed one machine cycle at a time. It is a multiplier with a bigline structure that processes the data sent in a pipeline and outputs the multiplication result at a rate of one operation per machine cycle. The floating point reciprocal approximation unit is plotjrlg pojnt l(,e
ciproc41AT;)proximB t i□n
The unit that processes instructions outputs an approximate reciprocal number with a precision of 30 bits from the data that has been sent for a long time at a rate of 1 machine cycle, and outputs the approximate reciprocal number at a rate of 1 operation result per 1 machine cycle. It is an arithmetic unit with a pipeline structure.

As can be seen from the above, in the conventional division of vector data, the floating point reciprocal approximation unit t is used once and the floating point reciprocal unit is used three times, both of which are processed in a pipeline at plotting point B.
Execute the eciprocal Approxjlnation instruction once, 1 (eciprocaI JteratlO
Execute n8 instruction once, floating point multiplication instruction twice, and 14 instructions to divide vector data J! Process it in a pipeline. In such a processing method, it is necessary to execute four instructions to process vector data, which takes processing time, and while the floating-point multiplication unit is used for division processing, normal inbound processing cannot be performed. There are problems like this. Also, before obtaining the interval Q, step 2. Step 3: 1. There is a problem in that it is necessary to hold N1 as an intermediate result until the quotient Q is received, and the extra 1 white requires a chain register or a vector register.

[Purpose of the invention]

An object of the present invention is to provide a circuit that processes division of vector data at high speed in a pipeline in a vector processing device that employs a division method in which multiplication is repeated.

[Overview of the invention]

The present invention is similar in that, in order to achieve a cylinder speed of 21 i$, a vector processing device equipped with a candidate number of pipeline arithmetic units employs a division method that repeats multiplication processing to achieve the desired result. When performing division Jl of vector data, we do not prepare a multiplication circuit dedicated to processing safe multiplication until the end of the song, but instead use it to process the instruction that multiplies vector data J1. Two pipeline multipliers provided as M are carefully combined and operated in conjunction to obtain the 9. The main purpose of this method is to perform standard processing and process division at cylinder speed in a pipeline. That is, by pairing two pipeline multipliers and providing a data bus that inputs the output result of one multiplier into the other multiplier, the 92 pipeline multipliers can be combined. By providing an additional circuit with a pipeline structure dedicated to division that shares a pipeline multiplier and a data supply port, and operating these in conjunction, division of vector data is processed in two pipes. Pipelining is an instruction that adds a divisor as an input operand and its approximate reciprocal as an output operand, and specifies the dividend, divisor, and approximate reciprocal of the divisor as input operands, and outputs the output. This is done by executing the 8r2 instruction with the instruction as the operand.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using Examples.

The division method in the present invention is based on a reciprocal approximation method. In this embodiment, a vector processing device having a floating point data format shown in FIG. 7A3 will be considered. The nature of the data derivation format of the vector processing device is not essential to the present invention.

The data representation format handled in this example is as shown in the third example.
The sign part is represented by 1 bit, the exponent part by e bits, and the mantissa part by m bits. Furthermore, the decimal point of the mantissa is located at the beginning of the mantissa.

What is relevant in division using the reciprocal approximation method is the number of digits present in the mantissa.In the data representation format shown in Figure 3, the number of significant digits in the mantissa is m bits, so division using the reciprocal approximation method is In this case, it is sufficient to consider the precision of m bits (precision 2-'') for the repetition of multiplication.

In this embodiment, the first approximate reciprocal of the divisor to be stored in the approximate reciprocal table is Kt bits, and the distance between the n degrees of the first approximate reciprocal and the number of floating point significant digits is as follows. There is a relationship.

6t≦m(7t μm In other words, to obtain a value that satisfies the number of floating point significant digits (m bits) for the first approximate reciprocal of the divisor obtained by subtracting the approximate reciprocal table, repeat multiplication using the reciprocal approximation method. Especially υ
, it is necessary to increase the accuracy by a factor of 6. FIG. 3 shows the relationship between the precision t of the first approximate reciprocal and the number m of significant digits in the mantissa part of floating point data.

In this example, the dividend is divided by N1, e is D, and after drawing the approximate reciprocal table to obtain r, which is the first approximate reciprocal of the divisor, the precision is increased by 6 times to obtain the quotient. The principle is as follows.

The process to obtain Q consists of the following 6 steps. Step 1: Subtract the approximate reciprocal value from the upper t number of mantissa parts of the divisor to obtain the first approximate reciprocal r of the divisor. As mentioned above, the precision of the first approximate reciprocal r is t bits, so the number of bits of the divisor necessary to obtain the first approximate reciprocal r may be the upper t bits of the m bits of the mantissa. .

Step 2: rt = 1 + (1-1) x r) + (1-DXr) 2
岨其 of μθ.

Step 3: 几0=rxrI　H calculation.

Step 4: Rt = 2-D X Roul calculation.

Step 5: N1=NXfi, O4 calculation.

Step 6: Q = N I X R1mp calculation.

Next, it will be shown that a quotient Q with an accuracy of m bits is obtained by the processing from step 1 to step 6 above.

When the divisor is multiplied by the first approximation reciprocal r, the value is close to 1. If the error is ε (0≦x1), the following equation can be obtained.

DXr=1±ε @ The error ε is caused by the fact that the first approximate reciprocal r does not have an accuracy of t bits, which is smaller than the number of significant digits of the floating point mantissa, m bits.

The formulas η, (to), 4, (to), υ and 24 lead to a series of 9-order equations.

-1-1) (1+ε2) =1±63 (2) ・几l=2DXR◎ −2−(1±63) =1+ε3v0 − l) X ROX R1= (1±63) (1+
g3 ) = 1-66 @ Equation (to), by calculating Dx o In this case, the precision of the floating-point data mantissa is less than or equal to the number of effective representation digits.

Therefore, if the quotient Q is Q-N X Ro

Step 5 above. Step 6 is for calculating ) in Eq.

In this embodiment, the processes from step 1 to step 6 described above, which are necessary to obtain the quotient, are implemented as follows. That is, the processing 'k from step 1 to step 3
'V E R instruction (vectorglementwi
VER performed with se 1 (eciprocBl instruction)
The output result of the command is approximately 0 given in the formula, RO
is an approximate reciprocal of the error ε3 of the divisor. Therefore, the VER instruction is an instruction that outputs an intermediate result to obtain Q, and is also an instruction that calculates an approximate reciprocal. The processing from step 4 to step 6 is V
BD instruction (VectorElementwise
yjde command].

In this way, the division processing from step 1 to step 6 described above is performed by successively executing two instructions, the VER instruction and the VED instruction.

The processing of the VER instruction and the VED instruction is a normal multiplication instruction-VEM instruction (■ector glernentwi3
eMH1tiply instruction) is processed in a pipeline by operating a pipeline multiplier and a division circuit with a pipeline structure provided for division processing in conjunction with each other. . The details of the processing will be described below.

First, an example of the structure of a pipeline multiplier will be shown.

FIG. 4 shows the implementation of a pipeline multiplier. In Figure 4, 1.21't is a data bus to which the multiplicand and multiplier are sent, respectively, 3 is a data bus that outputs Rongqi Shaogu, 10 to 17 are data registers, and 20 to 23 are multiple generation. Circuits, 30 to 33 are C8A tree (Carry
5ave Adder), 34 is a parallel adder, 40 is a first partial product carry output register, 41
is the sum output register of the first partial product, 42 to 47 are the carry output register and sum output register of the second partial product, third partial product, and fourth partial product, and 48 is the multiplication: Jl:I#i
This is the result register. The multiplication method of the pipeline multiplier shown in Fig. 4 is already a well-known technology, in which the multiplier is decoded in 2-bit units to generate a multiple of the multiplicand (*The mantissa part of the number is m as shown in Fig. 8g3. bits, so multiples of 7 are generated), and save these multiples using CBrrySave
Adder and parallel adder are added to obtain the rice nose result. In the example shown in FIG. 4, the m bits and the multiplicand held in the data register o are
o to generate multiples and convert these multiples into C8A)
! It is input to J-30 and added, and a carry output is obtained to the data register 4o, and a sum output is obtained to the data register 41 (calculation of the first partial product). Next, the second lower bit of the multiplier and the multiplicand are input to the multiple generation circuit 21 to generate a multiple, and these multiples, the carry output of the first partial product, and the sum output are calculated by C8A) -31 and the carry output and sum output of the second partial product are respectively sent to the data register 42.
Obtained at 43. Thereafter, similar processing is performed to obtain the carry output of the first and fourth partial outputs in the data register 46 and the sum output in the data register 47, and these are added by the parallel adder 34 to obtain the final product in the data register 48.

In the example shown in FIG. 4, the structure is such that it can be carried out using the above-mentioned terminal processing line. In other words, the input data, the multiplicand and the multiplier, are connected to data buses 1 and 2, respectively.
The data is sent one after another with one data allocation per machine cycle, which is the basic processing unit time of the processing device. The first multiplicand and multiplier sent are each in data register 1.
When set to 0.14, s is immediately used to calculate the first s division.
b. After one machine cycle, the carry output and sum output are stored in data registers 40 and 41. At the same time, the multiplicand sent first is set in data register 15, and the multiplicand and multiplier sent in the second column are set in data registers 1o and 14. Similarly below,
When the second part of the data sent first is stored in the data registers 42 and 43, the first part of the data sent to the second column is stored in the data registers 40 and 41. The third sent multiplicand and multiplier are respectively set in .14. Then, when the final product of the data sent first to the data register 48 is completed, the fourth partial product of the data sent to the 21st F is sent to the data register 46.47 in the third scan. The third part of the data is stored in data register 44.45.
Then, the second part of the data sent to the third checker is placed in the data register 42.43, the first part of the data sent to the fourth checker is placed in the data register 40°41, and the fifth part is placed in the data register 40.41.
The multiplicand and multiplier sent to the test are set in data register 10.14.

In this way, multiplication is processed in the pipeline, and once the multiplication result of the data sent first is sent out via the data bus 3, the multiplication results are sent out one after another at the machine cycle pitch.

Next, we will discuss an embodiment in which the division processing from Step 1 to Step 6 described above is processed by organically combining the two pipeline multipliers shown in FIG. 4 and an additional circuit with a pipeline structure dedicated to division. This will be explained in detail using FIG.

In FIG. 5, 1 and 3 are pipeline/multipliers whose structure is exactly the same as the pipeline multiplier shown in FIG. Pipeline/multipliers 1 and 3 can operate independently and are VEMs that perform vector data multiplication.
Each command can be processed independently. That is, when pipeline multiplier 1 processes a VEM instruction, data bus 1
Multiplicand data and multiplier data are supplied one after another from 0.degree. 11, and the multiplication results are sent out one after another over the data bus 12.

When the pipeline/multiplier 3 processes a VEM instruction, multiplicand data and multiplier data are successively supplied from the data buses 13 and 14, and multiplication results are sent from the data bus 15 one after another. Separate VE in pipeline multipliers 1 and 3
It is possible to process M instructions simultaneously.

Next, the operation of the division process in the embodiment shown in FIG. 5 will be explained. When performing division processing in the embodiment shown in FIG. 5, the following points are characteristic of the circuit configuration.

(1) In FIG. 5, 4 is a pipeline division addition circuit, which is a circuit specially provided to perform steps 2 and 5 of the division processing steps 1 to 6. It has a pipeline structure. For details of the internal configuration of the pipeline division addition circuit, the input data supply port is common to the input data supply port of the pipeline/multiplier 30. When supplying data to the pipeline division addition circuit 4, , from data bus 13.14, which supplies data to pipeline multiplier 3, via data bus 19.20ft.

(3) In FIG. 5, the output data of the pipeline division addition circuit 4 is sent to the pipeline multiplier 3 via the data bus 17, 18'.

(4) From (2) and (3), the pipeline division additional circuit 4 does not have a dedicated input data supply port and output data output port, and has the characteristics of an additional circuit attached to the pipeline multiplier 3. For convenience, in FIG. 5, when viewed from a vector processing device including the circuit in FIG. 5, the pipeline division addition circuit 4 is not an independent arithmetic unit, but a circuit combined with the pipeline multiplier 3. It is treated as one arithmetic unit. In FIG. 5, a circuit 2 in which a pipeline/multiplier and a pipeline division addition circuit are combined is called a pipeline multiplier with division addition mechanism. That is, the pipeline division addition circuit 4 provided exclusively for division processing in this embodiment is as follows:
When viewed from the perspective of the vector processing device as a whole, this embodiment is advantageous in that there is no need to provide a new data bus for handling a large amount of vector data, which is one of the features of this embodiment.

(5) In FIG. 5, there is a data bus 16 for sending the output data of the pipeline/multiplier 1 to the pipeline multiplier 3, and a bit inverting circuit 21 is inserted therebetween.

(6) In FIG. 5, 30.31 is a data bus select circuit, and the p1 data bus select circuit 30 sends the output data of the pipeline division addition circuit 4 to the path 13 that supplies multiplicand data to the pipeline multiplier 3. pass 17,
It is possible to select one of the paths 16 for sending data obtained by bit-inverting the output data of the pipeline multiplier 1,
Further, the data selection circuit 31 includes a pipeline multiplier 3
It is possible to select either the path 14 for supplying multiplier data to or the path 18 for transmitting output data of the pipeline division/addition circuit 4.

Next, the internal configuration of the pipeline division addition circuit 4 will be explained. In FIG. 5, 40 to 51 and 78.79 are data registers, and 60 to 62 are +f! 63 to 65 are the same circuits as C8A) IJ- explained in Fig. 4, 66 and 67 are the same circuits as the parallel adder explained in Fig. 4, and 70 to 75 are each C8A) Carry output registers of trees 63 to 65,
Sum output registers 76 and 77 are output registers of parallel adders 66 and 67, respectively, and 32 and 33 are data bus select circuits. Further, in FIG. 5, reference numeral 80 denotes a memory circuit, the purpose of which is to register an approximate reciprocal table. The pipeline division addition circuit 4 having the above configuration is functionally comprised of the following three components.

(1) Multiplier width-bit pipeline multiplier Data register 40, multiple generation circuit 60, C8A tree 63, parallel adder 66, data registers 70, 71 in FIG.
The circuit constituted by 76 is a pipeline multiplier that uses the data stored in the data register 40 as a multiplicand and the data read from the storage circuit 80 as a multiplier.

The number of bits of the multiplier is determined by the multiple generation circuit 60 and the C8A tree 6.
Since 3 is the same as those explained in FIG. 4, it is one bit.

(2) Multiplication i middle-bit pipeline *calculator data registers 48 to 51, multiple generation circuits 61, 62, C8A)
A circuit consisting of a key 64, 65, a parallel adder 67, and data registers 72 to 75 and 77 uses the data stored in the data register 48 as a multiplicand and the data stored in the data register 49 as a multiplier. It is a pipeline multiplier. The number of bits of the multiplier is the same as the multiple generator circuit explained in Figure @4.

(3) Approximate reciprocal table The storage circuit 80 shown in FIG. 5 reads data by using the data stored and viewed in the data register 40 as an address, and is an approximate reciprocal table that holds the first approximate reciprocal in division processing. used as.

In this way, although the pipeline division addition circuit is specially prepared for division processing, the circuit configuration is similar to a normal pipeline multiplier, which is advantageous in terms of circuit implementation. .

In the embodiment of FIG. 5 having the characteristic 7J: configuration as described above, the manner in which the division processing from step 1 to step 6 is executed in a pipeline will be described below. As mentioned above, the division process in this embodiment uses the VE command VE
This is performed using two instructions: D and Ht.

(1) Processing of the VER instruction The VER instruction takes the divisor as input data, performs the step-to-step 3 processing described above, and outputs the approximate reciprocal of the divisor given by 2 bets, 0, as output data. The processing is performed using the pipeline multiplier 2 with division/addition structure shown in Figure 5. Details of the processing for each step are shown below.

Step 1: The input data divisor is connected to data buses 13 and 1 in FIG.
are supplied one after another at one machine cycle pitch through 9,
It is set in the data register 40. data register 4
The approximate reciprocal registered in the storage circuit 80 is subtracted using the upper t bits of the m bits of the mantissa of the divisor iD set to 0 as an address to obtain the first approximate reciprocal r of the divisor.

The bit width of r is t bits.

Step 2: Calculate the divisor and the first approximate reciprocal r.

rt=1+(1-DXr)+('1-Dxr)" (1
7) First, 1-Dxr (31) is calculated by the multiplier width-pit pipeline multiplier in the bigline division addition circuit 4.

The first approximate reciprocal number r has a width of t bits, and the relationship shown in the equation (t!9) holds between t and the number m of floating point mantissa bits.

Therefore, in the calculation of formula (31), Dxr is D as the multiplicand,
It can be calculated using an Eveline multiplier with r as a multiplier and a -bit in the multiplier.

Actually, it is calculated in the form of equation (33) by transforming into equation (31)'.

1 +Dx (-r) (33) In the calculation of equation (33): - The process of changing the multiplier from r to -r is performed by the bit inverting circuit 81 in FIG. 6, which performs 1's complement conversion.

- Addition of value 1 is performed by adding value 1 generation circuit 8 when adding multiples generated by multiple generation circuit 75 in C8A tree 70.
Processing is performed by adding the two outputs together.

Through the above processing, the value of equation (33) is stored in the data register 44. These processes are performed in a pipeline. That is, when the divisors are supplied one after another at one machine cycle pitch via the data buses 13 and 19, and the calculation result of the -th bud data is set in the data register 76, the 24th digit
The partial product of the i-th data is stored in the data register 70.71,
The data of the third bud is set in the data register 40.

Next, the equation αη is calculated using the calculation result of equation (33). The calculation of equation [7J is performed using a pipeline multiplier with a multiplier width of bits in the bigline division/addition circuit 4. To calculate Buddhahood, transform Buddhahood η as shown in equation (34).

1+(1-DXr) ・(1+(1-])Xr))(3
4) That is, the data select circuits 32 and 33 are controlled to select the value of the data register 76, and 1i[ of (1-DXr) obtained in the data register 76 is set in the data register 49 as a multiplier. The value (1
+(1-DX) is set in the data register 48 as the multiplicand.

When the multiplicand and multiplier are set in the data registers 48 and 49, the multiple generation circuit 61, 62, C8A) Lee-64
, 65, and a multiplication process is started in the pipeline using a parallel adder 67.

Furthermore, the addition of the value 1 in equation (34) is performed using the same method as used in the calculation of equation (33), and the multiple generated by the multiple generation circuit 61 is added to C8A! When adding in J-64, the output of the value 1 generation circuit 84 is added and added, thereby performing multiple processing.

By the above processing, the value r of the formula αη! is the data register 79
Nimaru.

Further, the first approximate reciprocal number r read from the storage circuit 80 advances through the data registers 42 to 47 in synchronization with the progress of the multiplication process until the corresponding 2αη is obtained. That is, the formula u'D corresponding to the data of the I-th previous month (l is a natural number)
When the calculation result r1(ri) is set in the data register, the first approximate reciprocal r (i) corresponding to the i-th data is set in the data register 47.

In addition, in the calculation of equation (34), the multiplier 1-DXr l
Since J[ is given by the formula Q and t pit is good, the formula (
According to the relationship 32), the multiplier width is sufficient and is 2.

Step 3: The multiplication process in Equation 4 is performed using the pipeline multiplier 3.

That is, by controlling the data bus select circuit 30 to select the data bus 17 and controlling the data select circuit 31 to select the data bus 18, the value r obtained in the data register 47 and the data register 77 are controlled. The values r1 obtained in
Incorporate into 1. When data is input into the data registers 00 and 101, the pipeline multiplier 3 operates as described in the explanation of FIG. Register 02
is obtained and sent out via the data bus 15 as the operation result of the VER instruction.

In the processing of the VER instruction shown above, after the input data, the divisor, is set in the data register 4o, the
A series of processing until the M result R, is stored in the data register 102 is performed in a pipeline, and when vector data is supplied one after another at one machine cycle pitch via the data bus 13.19, the data of the first bud is When the KM result is sent out via the data bus 15, the calculation results are sent out one after another at a pitch of 17 syncycles.

(2) Processing of the VED instruction The VED instruction takes the dividend N1 and the divisor and the calculation result of the VEIL instruction, 几0, as input data, performs the processing of steps 4 to 6 in θσ, and outputs the quotient Q. Output. The processing is performed by operating the pipeline multiplier 1 and the pipeline multiplier 2 shown in FIG. 5 in conjunction with each other. Details of the processing of each step mother are shown below.

Step 4: The second calculation is performed by the pipeline multiplier 1.

R1=2DXRoul In FIG. 6, the approximate reciprocal number 0 is supplied one after another at one machine cycle pitch via the data bus 10 and the divisor D1 data bus 1lt-. Divisor and approximate reciprocal 0
are set in the data registers 200 and 201, respectively, the pipeline multiplier 1 operates as described in the explanation of FIG. 4, the multiplication process of D X Ro is processed in the pipeline, and ff1J! The result is available in data register 202.

The process of subtracting the DXRoO value from 2 to obtain R11 is DX
This corresponds to obtaining the two's complement value of the value of Ro, and this is realized by the bit inversion circuit 21°+1 circuit 22.

The value R1 obtained above is sent to the pipeline multiplier 2 with a division addition mechanism via the data bus 16.

Step 5: The multiplication process in equation (a) is performed through pipeline division and addition.

N t = N and set to 41.

In the processing of this step, the data bus select circuit 3
2 selects the data register 78, and the data bus select circuit 33 is controlled to select the value of the data register 79. The dividend N set in the data register 40 is
It is set in the data register 48 via the data register 78 and the data bus select circuit 32. Similarly, the approximate reciprocal value 0 set in the data register 41 is set in the data register 49 via the data register 79 and the data bus select circuit 33.

Using Nf: multiplicand set in the data register 48 and Re set in the data register 49 as a multiplier, the multiplication process of 2071 is performed using the multiple generation circuits 61, 62, C8A) Lee 64.65, and parallel adder 67t''. This is done in a pipeline, and the result N1 is obtained in the data register 77.

In the multiplication process of the expression (to), the multiplier ⇠◎ is in the expression)
It has the accuracy shown in . That is, it has three times the accuracy of the ellipse of the cross-order approximate reciprocal r. Since the first approximation reciprocal r is expressed in t bits, there is no problem in terms of accuracy if the value 0 is expressed in 3Xt bits. Since there is a relationship of 2Uω between t and the number of significant digits m of the floating point mantissa, there is no problem.

Here, the processes of step 4 and step 5 are performed synchronously. That is, when input data is supplied one after another at one machine cycle pitch, the i-th column divisor D1, the i-th dividend N, and the approximate reciprocal Ro of the i-th column are stored in the data registers 200, 100° 101, and 201. They are set at the same time. Furthermore, the first divisor D1 approximate reciprocal 1111o is 200.20 of the data register.
After being set to 1, D
The time taken until the X B oO value is set in the data register 202, and after the first dividend N and approximate reciprocal Ro are set in the data registers 40 and 41, respectively.
The pipeline multiplication device 1 and the pipeline removal addition circuit 4 are omitted so that the time it takes for the calculation result Nl of step 5 to be set in the data register 77 is 5 machine cycles. Therefore, in the process of step 6 to be described next, R1 of the first scan, Nl of the I-th stitch
are set in data registers ioo and ioi, respectively, at the same time.

Step 6: The multiplication process of the expression nυ is processed by the pipeline multiplier 3. When the VED instruction is executed, the data bus select circuit 30 in FIG. 6 selects the data bus 16, and the data bus select circuit 31 is controlled by 1ttlJ to select the data bus 18.

The result 1 of step 4 calculated in the pipeline by the pipeline multiplier 1 is sent one after another at a pitch of 1 machine cycle via the data bus 16 and set in the data register 100. Further, the result of step 5 calculated in the pipeline by the pipeline division/addition circuit is sent slowly through the N1kif-tabus 18 at l machine cycle pitch and set in the data register 101. At this time, as mentioned above, the first R1 of interest is the data register io.
o.

N1 of the i-th scan is set in the data register 101 at the same time.

R, and Nl are data registers 100.10, respectively.
When set to 1, the pipeline multiplier 3 operates as described in the explanation of FIG. The data obtained in the data register 102 is VE
The multiplication result of the D instruction is sent out one after another as music Q via the data bus 15 at one machine cycle pitch.

In the processing of the VED instruction shown above, after the input data division IILD, dividend N1, and approximate luck number Ro are set in the data registers 200, 100, 201° 101, respectively, the song Q that can be performed using the output data is stored in the data register 102.
The series of processing up to the end of the first scan is performed in a pipeline, and when input data is supplied one after another at a pitch of 17 syncycles, when the calculation result of the first scan data is sent out via the data bus 15, Thereafter, the calculation results are sent out one after another at one machine cycle pitch.

In the embodiment of the present invention described above with reference to FIG.
The division of data is performed using the circuit shown in FIG.
This is accomplished by consecutively executing two commands: the R command and the VEI command. Furthermore, both the VER instruction and the VED instruction are processed in a pipeline, and one execution result is obtained in one machine cycle. Therefore, in the embodiment shown in FIG. 5, Q can be obtained isometrically by allocating one operation result to two machine cycles.

FIG. 6 shows an embodiment of a vector processing device that combines the circuit configuration for vector division processing shown in FIG. In FIG. 6, pipeline multiplier 1, pipeline multiplier with division addition mechanism 2, and data buses 10 to 16 correspond to those in FIG. The main memory 100 holds vector data and vector instruction sequences, and 2oo is a group of vector registers, which are located between the main memory and the pipeline arithmetic unit and are used to temporarily store vector data. It is. In the embodiment of FIG. 6, there are N vector registers, each o, 1°2, . . . , N-1.
It is gaining strength. Furthermore, the valley vector register is capable of holding vector data consisting of a maximum of a large number of elements. Data buses 101-105 are for data transfer between the main memory and vector registers.

Reference numeral 206 denotes a vector register read/input control circuit, which controls the data bus connection between the vector register and the pipeline arithmetic unit. lJ It's something to groan about.

Data buses 201-205 are data buses between the vector registers and the vector register read/pledge control circuit.

300 is a vector instruction register (VectorInst
A register (abbreviated as VIR) is a register that temporarily holds a vector instruction read from the CPU storage device via the data bus 304.

301 is a circuit for decoding the vector instruction held in the vector instruction register 300; a signal line 302 is for notifying the vector register decoding/expense control circuit of the decoding result of the vector instruction; and a signal line 303 teeth,
Pipeline elevator 2 with repair/additional structure shown in Fig. 5
This is for controlling the data select circuits 30, 31, 32, and 33 within.

In the embodiment shown in FIG. 6, only two pipeline arithmetic units related to the division process are shown as pipeline arithmetic units, but it is not possible to use β other pipeline arithmetic units. .

FIG. 7 shows an example of a vector instruction sequence for executing division in the vector processing device shown in FIG. 6. In FIG. 7, instruction ■■ is vector data dividend number N on the main memory.

Vector LoaD instruction (abbreviation Vl, D) that loads each vector register Oao+ into the bud.
It is. Instruction ■ is the VER instruction shown above, which reads the divisor loaded into the first register of the vector register by instruction ■, calculates the approximate reciprocal Re, and stores the result in the second vector register. It is something. Instruction ■ is the VED instruction shown above, and instructions ■, ■, and ■ calculate the dividend N, divisor, and approximate reciprocal Ro stored in the Oth, first, and second fields of the vector register, respectively. It reads out, calculates Q'l1f, and stores the result in the third vector register. Note that the instruction ■ does not specify the second register of the vector register where ◎ is stored, but this is because the operand specification method of the ■ED instruction is different from the previous one of the vector register where the divisor is stored. This is because the number of specified operands is reduced by assuming that the approximate reciprocal number 0 of the divisor is stored in the vector register of the previous issue, which is 1 more.

Next, the manner in which the vector order sequence shown in FIG. 7 is received by the vector processing device shown in FIG. 6 will be explained.

Here, the instructions ① and ② in the m7 diagram have no particular relation to the present invention, so their explanation will be omitted.

(i) Processing of vEg instructions When the instructions ■ and VE]R shown in FIG. It will be done. Vector Hall Order Deciphering Episode lN1301
When the contents of the instruction are decoded in the signal line 302, the data bus 202 and the data bus 13, and the data bus 203 and the data bus 15 are all coupled to the vector register read/write control circuit, and the first vector register Instructs to read data from the destination and store data in vector register 24i. In addition, via the No. 1i Iwao 303, the VER
Directs the processing of instructions. Thereafter, the divisor values are sequentially extracted from the first check of the vector register, and sent to the pipeline multiplier with a division addition mechanism via the data buses 202 and 13. They are successively written to the second bud of the vector register via buses 15 and 203.

(2) Processing of the VED instruction In exactly the same way as for the VER instruction described above, the main memory 100
The instruction ① and the VED instruction in FIG. When the contents of the instruction are decoded by the vector instruction decoding circuit 301, the data bus 201 and the data bus 13, the data bus 202 and the data bus 10, and the data bus 203 and data buses 11 and 14e, respectively, and check the 0th vector register.

11th! , instructs the continuation of the second examination and its inclusion in the 31st examination. Further, via the signal line 303, all processing instructions for the VED instruction are given to the pipeline booster with division/additional protection. Shikarutoshi, from the 0th check, 1st eclipse, and nest 2 check of the vector register, the plate divisor N, divisor ri, and approximation 212, respectively! Number R.

The data buses 201, 13, and 2 are taken out one after another, respectively.
02 and 10, 203, 11 and 14 to the pipeline multiplier 1 and the pipeline multiplier 2 with division addition mechanism, the quotient Q is calculated in the pipeline, and the quotient Q is supplied to the vector register via data buses 15 and 204. Write one after another in the third examination.

As described above, according to this embodiment, the pipeline multiplier used for normal multiplication processing is used, and the vector data is divided by 'x' using two instructions, the VER instruction and the VED instruction.
, is processed in the pipeline, and the vector register holding Re is 1 as part of the process until obtaining the quotient Q.
It has the characteristic of being next to each other with books.

〔Effect of the invention〕

As mentioned above, in a vector processing device, the end:j!
When dividing vector data using the reciprocal approximation method, which calculates the quotient by repeating ptA, conventionally, a normal multiplier is used to calculate the quotient. In contrast, in the present invention, for the 211i1 pipeline multiplier used in normal pipeline multiplication processing, the output result of one multiplier is directly input to the other multiplier. In addition, an additional circuit with a pipeline structure dedicated to division processing, which has a structure similar to a normal pipeline multiplier, is installed in such a way that the population data supply port is shared with the pipeline multiplier. Vector data division J1. without providing a large-scale circuit dedicated to division processing within the processing device can be processed quickly using a pipeline.

[Brief explanation of drawings]

Figure 1 is a diagram showing a conventional floating-point numerical data representation format, Figure 2 is a diagram showing the concept of multiplication improvement in conventional division processing, and Figure 3 is a diagram showing a floating-point data representation used in an embodiment of the present invention. Figure 4 is a block diagram of a pipeline multiplier used in an embodiment of the present invention, Figures 5 and 6 are block diagrams of an embodiment of the present invention, and Figure 7 is a block diagram of a pipeline multiplier handled in an embodiment of the present invention. FIG. 3 is a diagram showing a vector instruction sequence handled by one embodiment. DESCRIPTION OF SYMBOLS 1... Pipeline multiplier, 2... Dictionary addition Shinkushun pipeline multiplier, 3... Pipeline multiplier, 4
Figure 1 fJ2 Figure ■ 4 Figure

Claims (1)

[Claims] It is equipped with at least two pipeline-structured multipliers prepared for the purpose of processing vector data multiplication instructions for the purpose of speeding up processing, and employs a method that performs division by repeated multiplication. In a vector processing device,
The two multipliers are grouped as a unit, and a data bus for directly inputting the output result of one multiplier to the other multiplier, and an addition dedicated to division processing that shares a data input port with the latter multiplier. A vector processing device characterized by processing division of vector data in a pipeline by providing a circuit and operating the two multipliers and an additional circuit dedicated to the division in conjunction.