JPS61220028A - Multiplying device - Google Patents

Abstract

PURPOSE:To omit an adder adding the code bit of a partial product and to reduce a circuit size by executing the digit matching when the tree circuit of the 2nd stages Wallace adds the output of the tree circuit of the 1st-staged Wallace. CONSTITUTION:It is assumed that the input numbers k1, k2...km of tree circuits 4, 5 and 6 of the 1st-staged Wallace are (k). A dividen X and a multiplier Y set to registers 1 and 2,respectively, are inputted to a partial produce generator 3 to produce N-number of partial products. They are inputted to the 1st-staged circuits 4, 5 and 6 by k-number of them so as to be added. After m-number of sums S1-Sm of the circuits 4, 5 and 6 and m-number of carriers C1-Cm are digit-matched, they are narrowed to the sum S and the carry C by the tree circuit 7 of the 2nd-staged Wallace having (2Xm) inputs. Then the adder 8 adds the sum S to the carry C, and sets the product Z to a register 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multiplication device suitable for use in a digital signal processing circuit such as a digital filter.

[Background of the invention]

As a method of calculating the product of a multiplier and a multiplicand, for example, as shown in Japanese Patent Application Laid-Open No. 199044, Bo
Generate partial products using oth's algorithm, add the generated partial products using Wallace's method, narrow down to a carry (carry) and a sum (sum), and finally add the carry and sum using an adder. The desired format is known. There are two ways to add partial products: one is to generate partial products sequentially and add them cumulatively, and the other is to generate partial products at the same time and add the partial products at the same time.The former method is a small input addition method. The latter requires less time to calculate the product and the multiplication speed is slow, while the latter requires less calculation time and the multiplication speed is fast, but the partial product Each has advantages and disadvantages, such as when the number of and bat length increases, multi-input and multi-bit adders are required, and the circuit scale increases.

Recently, there has been an increase in the use of LSI multipliers in digital signal processing circuits such as digital filters, and due to processing speed constraints, the latter multiplication method is used. A method to reduce the scale is desired.

[Purpose of the invention]

The purpose of the present invention is to meet such demands, and by using a method that simultaneously generates partial products and simultaneously adds them to obtain the product, it is possible to reduce the circuit size without reducing the calculation speed. To provide a multiplication device.

[Summary of the invention]

In order to achieve this objective, the present invention divides n partial products into m groups of 'a (α-1, 2, 5-..., m), and divides the n partial products into Wallac on the tier
4. By the tree circuit of e. Add the inputs to generate m intermediate sums, and after aligning the digits of these intermediate sums, add them using the Wallace tree circuit of the second stage (2Xm) input. There is a percentage mark.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

Figure 1 is a block diagram showing an embodiment of a multiplication device according to the present invention, and 1 and 2 are multiplicands X.

5 is a partial product generator; 4, 5.6 is a first-stage Wallace tree circuit for inputting cards; 7 is a second-stage Wallace tree circuit for inputting m; 8 is an adder, and 9 is a register for storing the product Z.

In the figure, in order to simplify the explanation, it is assumed here that the input numbers 'Iv 'l ''* 'm of the Wallace tree circuit 4°5.6 in the first stage are equal to each other and A. do.

Multiplicand X1 multiplier Y set in register 1.2 is input to partial product generator 3 to generate n partial products. These partial products are input four by four to the first stage Wallace tree circuit 4.5.6 and added. 1st stage Wallace tree circuit 4, 5.6 m sums S
, ~sm and m numbers of cards IJ + C, ~伽, after performing digit alignment, the second stage Walli of (2 × m) input
The ce tree circuit 7 narrows down the result to the sum S and carry C, and the adder 8 adds these sum S and carry C to set the product z in the register 9.

The above operation will be explained in more detail as a 10-bit/XIO-bit multiplication device.

Diagram 2 shows 2 where the multiplicand X and multiplier Y are both 10 bits.
This shows the multiplication process in the complement representation of .

In the figure, the multiplier Y is decoded 2 bits at a time using the second-order Booth algorithm, and partial products A, B, and C are decoded.
, D, B and a two's complement correction term TC. Since the product is the sum of all of these A, B, C, D, E, and TC, normally the sign bits of each partial product A, B, C, and D are set so that the digits are aligned with the partial product E. , A', B, C',
Add D', and add 0 for π°, and make 6-manpower W.
Addition is performed using a tree circuit of allace. In this case, since the number of bits in the product 2 is 19 bits, 19 Wallace tree circuits powered by six people are required. For this reason, the circuit scale becomes large. In addition, age 3
The figure shows one unit (i
100°101, 10
2 and 103 are full adders.

In contrast, the addition method of the present invention will be explained using FIGS.

First, in Diagram 4, A, B, C, D, and E are partial products shown in Diagram 2, and TC is a two's complement correction term also shown in Diagram 2. Also, 4°5 is 1 in the 1 figure.
The tree circuit of Wallace in the row is shown, 4-0 to 4
@2. And 5-4 to 5-18 are 3-man Wallac
In the tree circuit of e, 6 is generated by one full adder each. The partial molecule jFA is generated by Wallace's tree circuit 4 in the first stage.

B, and the two's complement correction term TC are added for each bit, and 1
A 3-bit sum (So to S4) and a 13-bit *Y'I (Ct to Cts) are obtained. simultaneous trap 1 molecule fr
CD and E are added bit by bit using the Wallace tree circuit 5 in the first stage to form a 15-bit sum (S; ~
S, -) and 15 bit carry (C; ~C8°.)
get. These two types of sum and carry are then added by a four-man Wallace tree circuit in the second stage.

Next, a method for adding the sum and carry from the tree circuit of the Wallace in the first stage of the first stage using the tree circuit of the Wallace in the second stage will be explained with reference to Figures 5 and 6. In Figure 5, 7-4 to 7-18 are units of a four-man Wallace tree circuit, and corresponding parts in Figure 1 and Figure 4 are given the same reference numerals. In addition, Figure O6 shows a concrete example of the 1st position (i-th digit) of this four-person Wallace tree circuit, and 10.11
is a full adder.

In Figure 5, Wallace's tree circuit 4.5 at the first stage to Wallace's tree circuit 7 at the second stage.
When inputting to 81., the output sty of the Wallace tree circuit 4 in the first stage and 81. Use the 1st stage wall
The digits are aligned with the output of the ace tree circuit 5 and input to the Wallace tree circuit 7 in the second stage of the spear.

In this way, the digits are adjusted for the output of the Wallace tree circuit in the first stage, and the output of the Wallace tree circuit in the second stage is adjusted.
By adding with the tree circuit of CE, 6-man power Wa
Compared to the case of using a llace tree circuit and performing digit alignment using the input partial products, the W
Allace's tree circuit 12-21 and 4-person Wa
The tree circuit 22-5-25 of llace can be omitted.

Therefore, when performing operations with the same number of bits, the circuit scale of this embodiment is reduced compared to the prior art. In this embodiment, the case where both the multiplier and the multiplicand are 110 bits has been shown, but furthermore, the number of bits of the multiplier and the multiplicand becomes large (as the number of full adders that can be omitted increases).

Also, when the number of bits of the multiplier and multiplicand increases, and the number of partial products increases, it is not only necessary to use a two-stage WallaCe tree circuit (, three-stage, four-stage...multi-stage Wallace tree circuit). The circuit can perform addition of partial products.

The OFF diagram is a block diagram showing a part of another embodiment of the multiplication device according to the present invention, in which 26 is an OR circuit, 27 is an AND gate, and 28 is the output of the OR circuit 26.

29 is the output of the AND gate 27, and corresponding parts are given the same reference numerals.

In Figure 5, the digits were aligned using the three-man Wallace tree circuit 4-12 sum 5Illkya') eta; The digits are aligned using gate 27. For all possible states of sum 5ll-carry C, , output 2 of OR circuit 26
8 and the output 29 of the AND gate 27 have the truth shown in the following table, and have the same value as the input to the Wallace adder at the next stage.

〔table〕

For this reason, the output SI of the Wallace tree circuit in the first stage! Rather than directly performing digit alignment using IC1m, digit alignment can be performed using a value decoded using a gate.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of partial products are divided into groups and added using the Wallace tree circuit with decimal input.
The output of the tree circuit of e is further connected to the second stage Wall.
Compared to the above-mentioned conventional technology in which addition is performed using a single stage of multi-input Wallace tree circuit, the adder that adds the sign bit of the partial results can be omitted, since digit alignment is required when adding by the ace tree circuit. Therefore, it is possible to reduce the circuit scale and provide a multiplication device suitable for LSI implementation.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of a multiplication device according to the invention. Fig. 2 is an explanatory diagram showing a conventional multiplication procedure.
Block diagram showing one unit of the tree circuit of lace
The figure is an explanatory diagram of the arithmetic processing operation of the Wallace tree circuit at the first stage in Figure 1. An explanatory diagram showing how to input to the Wallace tree circuit, Figure 6 is the second wall of Figure 5.
A block diagram showing one unit of an ace tree circuit, and an off diagram showing a part of another embodiment of the multiplication device according to the present invention. 1...Register for storing the multiplicand, 2...Register for storing the multiplier, 3...Partial product generator, 4,5゜6・
...Wallace's tree circuit in the first stage, 7...
2nd stage Wallace tree circuit, 8... adder, 9... register for storing product.

Claims (1)

[Claims] A partial product generator that divides a multiplier into n (natural number) groups of multiple bits each and multiplies each group with a multiplicand to generate n partial products; and a partial product generator that generates n partial products from the n partial products. and means for generating a product of the n partial products kα (where α
= 1, 2, 3, . . . , m).
The output of the tree circuit of the Wallace in the second stage is inputted with digit alignment (2×m).
1. A multiplication device comprising an ace tree circuit and an adder that adds the outputs of the second-stage Wallace tree circuit.