JPS6084868A - Charge transfer device - Google Patents

Charge transfer device

Info

Publication number
JPS6084868A
JPS6084868A JP58191668A JP19166883A JPS6084868A JP S6084868 A JPS6084868 A JP S6084868A JP 58191668 A JP58191668 A JP 58191668A JP 19166883 A JP19166883 A JP 19166883A JP S6084868 A JPS6084868 A JP S6084868A
Authority
JP
Japan
Prior art keywords
gate
accumulation
transfer
charges
under
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58191668A
Other languages
Japanese (ja)
Other versions
JPH0669089B2 (en
Inventor
Tadashi Aoki
正 青木
Hirokuni Nakatani
中谷 博邦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP58191668A priority Critical patent/JPH0669089B2/en
Publication of JPS6084868A publication Critical patent/JPS6084868A/en
Publication of JPH0669089B2 publication Critical patent/JPH0669089B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/148Charge coupled imagers
    • H01L27/14831Area CCD imagers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To enable the great improvement of the charge transfer efficiency during an accumulation period by a method wherein a buried channel is provided under a double step gate adjacent to the photo charge accumulation part. CONSTITUTION:The photo charge accumulation part 1 and an accumulation gate 10 are connected inside, which are further connected to a substrate 2. A shift gate 5 serves to transfer charges accumulated under the gate 10 to the CCD part 6 and determines the time of accumulation. In the case of photo irradiation to the part 1, the charges photoelectrically converted in this region move down to the gate 10 as the result of making a difference in potential by the difference in the concentration between the region 11 under a barrier gate 9 and the region 12 under the gate 10. This transfer of charges are performed during the period of accumulation, and the rate of leaving charges becomes 0.5% or less. The transfer from the gate 10 to the CCD part 6 is by the buried channel CCD mode, and the rate of remaining charges due to this transfer becomes 0.02% or less.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、電荷転送装置に関するものである。[Detailed description of the invention] (Industrial application field) The present invention relates to a charge transfer device.

(従来例の構成とその問題点) 昨今、電荷転送機能を有するCCD (電荷結合素子)
の開発が進み、その応用としてCODイメージセンサの
開発が活発に進められている。
(Conventional structure and its problems) Recently, CCD (charge coupled device) with charge transfer function
The development of COD image sensors is progressing, and COD image sensors are being actively developed as an application thereof.

第1図は、従来のCCD固体撮像装置の光電変換部近辺
の断面を示したものである。1は、基板2とは反対の導
電型を有し、光電変換及び蓄積作用をなす光電荷蓄積部
である。3は基板2と同じ導電型で、基板2よシも濃度
の高いチャンネルストッパであり、4は光電荷蓄積部1
の電位を決めるホトゲートであシ、5は光電荷蓄積部1
の電荷をCC0部6に転送する役目をなし、かつ蓄積時
間を決定するシフトゲートであり、7はゲート酸化膜で
ある。
FIG. 1 shows a cross section of a conventional CCD solid-state imaging device near a photoelectric conversion section. Reference numeral 1 denotes a photoelectric charge accumulating portion which has a conductivity type opposite to that of the substrate 2 and performs photoelectric conversion and accumulation functions. 3 is a channel stopper which has the same conductivity type as the substrate 2 and has a higher concentration than the substrate 2, and 4 is a photocharge storage section 1.
5 is a photo-charge storage section 1 which determines the potential of
This is a shift gate that serves to transfer the charge of 1 to the CC0 section 6 and also determines the accumulation time, and 7 is a gate oxide film.

第2図は、第1図の構造のポテンシャルを示す。FIG. 2 shows the potential of the structure of FIG.

今、光電荷蓄積部1及びホトゲート4の下の電荷8をC
C0部6へ転送するには、シフトゲート5にパルス電圧
を印加して、第2図(a)の状態から(b)の状態に移
す。この時の転送はBBD転送であシ、シフトゲート5
に印加するパル大幅を充分に長く取っても、光電荷蓄積
部1及びホトゲート4の下に蓄積された電荷の2%以上
を取り残してしまう。結果として次の蓄積期間の信号と
混合し、イメージセンサの場合は残像となる。
Now, the charge 8 under the photocharge storage section 1 and the photogate 4 is
To transfer to the C0 section 6, a pulse voltage is applied to the shift gate 5 to shift from the state shown in FIG. 2(a) to the state shown in FIG. 2(b). Transfer at this time is BBD transfer, shift gate 5
Even if the width of the pulse applied to is made sufficiently long, more than 2% of the charges accumulated under the photocharge storage section 1 and the photogate 4 will remain. As a result, it mixes with the signal of the next accumulation period, resulting in an afterimage in the case of an image sensor.

第3図は、以上の点を改良した従来例である。FIG. 3 shows a conventional example improved in the above points.

第1図のホトゲート4を分割して、バリャゲート9と蓄
積ゲート10にしている。バリヤゲート9は光電荷蓄積
部1の電位を決めるゲートである。
The photogate 4 shown in FIG. 1 is divided into a barrier gate 9 and an accumulation gate 10. Barrier gate 9 is a gate that determines the potential of photocharge storage section 1 .

蓄積ゲー) 10は光電荷蓄積部1で光電変換した電荷
を蓄積時間内に蓄積するゲートであり、バリヤゲート9
よシボテンシャルが深くなるような電位を与えておく必
要がある。
(accumulation gate) 10 is a gate for accumulating the charges photoelectrically converted in the photocharge accumulating section 1 within the accumulating time;
It is necessary to apply a potential that makes the texture deep.

第4図は第3図の構造のポテンシャルを示す。FIG. 4 shows the potential of the structure of FIG.

第3図の構造では、光電荷蓄積部1で光電変換した電荷
は直ちに、蓄積ゲート下に移動し、蓄積時間中、電荷の
移動が行なわれ、電荷の取残しは0.5チ以下となる。
In the structure shown in Fig. 3, the charges photoelectrically converted in the photocharge accumulation section 1 immediately move to the bottom of the accumulation gate, and the charges are moved during the accumulation time, so that less than 0.5 inches of charges are left behind. .

また蓄積ゲート10の下の電荷8ヲCCD部6へ転送す
るには、シフトゲート5にパルス電圧を印加して、第4
図(&)の状態から(b)の状態に移す。この転送は、
CcD転送でラシ、電荷の取り残しは01%以下でアシ
、結果として光電荷蓄積部1から600部6への転送の
際の電荷の取り残しは0.6%以下となる。しかしなが
ら第3図の構造のもので□は、バリヤゲート9及び蓄積
ゲート10にそれぞれ別々の電圧を与えなければならず
、電圧の設定及び供給方法に種々の問題点があった。
Further, in order to transfer the charge 8 below the storage gate 10 to the CCD section 6, a pulse voltage is applied to the shift gate 5 and the fourth charge 8 is transferred to the CCD section 6.
Move from the state shown in (&) to the state shown in (b). This transfer is
In CcD transfer, the amount of charge left behind is 0.1% or less, and as a result, the amount of charge left behind during transfer from the photocharge storage section 1 to the 600 section 6 is 0.6% or less. However, in the structure shown in FIG. 3, separate voltages must be applied to the barrier gate 9 and the storage gate 10, and there are various problems in the voltage setting and supply method.

本発明は、上記欠点に鑑み、転送効率を上げ、取シ残し
電荷を少なくすることのできる電荷転送装置を提供する
ものである。
In view of the above drawbacks, the present invention provides a charge transfer device that can increase transfer efficiency and reduce unused charges.

(発明の構成) この目的を達成するために、本発明の電荷転送装置は、
基板とは反対の導電型を有する光電荷蓄積部と、この光
電荷蓄積部の電位を決めるバリアゲートおよび蓄積ゲー
トからなる二段ゲートとを備え、その二段ゲート直下に
埋込みチャンネルが形成された構成となっている。
(Structure of the Invention) In order to achieve this object, the charge transfer device of the present invention includes:
It includes a photocharge accumulation section having a conductivity type opposite to that of the substrate, and a two-stage gate consisting of a barrier gate and an accumulation gate that determine the potential of the photocharge accumulation section, and a buried channel is formed directly under the two-stage gate. The structure is as follows.

(実施例の説明) 以下、実施例について、図面を参照しながら説明する。(Explanation of Examples) Examples will be described below with reference to the drawings.

第5図は、本発明の一実施例におけるCCD固体撮像装
置の光電変換部近辺の断面を示したものである。1は光
電荷蓄積部で、基板2とは反対の導電型を有する領域で
ある。3は基板2と同じ導電型で、基板2よシも濃度の
高いチャンネルストッパ領域であシ、9は光電荷蓄積部
1の電位を決定するバリヤゲートでS、!+、1iは基
板とは反対の導電型を有するウェル領域で多る。1oは
光電荷蓄積部lで発生した電荷を蓄積する蓄積ゲートで
あり、12は基板とは反対の導電型を有し、濃度がウェ
ル領域11よυも高いウェル領域である。
FIG. 5 shows a cross section of the vicinity of a photoelectric conversion section of a CCD solid-state imaging device according to an embodiment of the present invention. Reference numeral 1 denotes a photocharge storage region, which is a region having a conductivity type opposite to that of the substrate 2. 3 is a channel stopper region which is of the same conductivity type as the substrate 2 and has a higher concentration than the substrate 2; 9 is a barrier gate that determines the potential of the photocharge storage section 1; S,! +, 1i is abundant in the well region having the opposite conductivity type to the substrate. 1o is a storage gate that stores charges generated in the photocharge storage section l, and 12 is a well region having a conductivity type opposite to that of the substrate and having a concentration υ higher than that of the well region 11.

光電荷蓄積部lと蓄積ゲート10とは内部で接続されて
おシ、更にそれらは基板2に接続されている。5は蓄積
ゲー) 10の下に蓄積されている電荷を600部6に
転送する役目をなし、かつ蓄積時間を決定するシフトゲ
ートであり、7はゲート酸化膜である。第6図は第5図
の構造のポテンシャルを示す。
The photocharge storage section 1 and the storage gate 10 are connected internally, and furthermore, they are connected to the substrate 2. Reference numeral 5 denotes an accumulation gate) A shift gate serves to transfer the charges accumulated under 10 to the 600 section 6 and determines the accumulation time, and 7 is a gate oxide film. FIG. 6 shows the potential of the structure of FIG.

第5図において、光電荷蓄積部1に光照射された場合こ
の領域で光電変換された電荷は、ンフトゲ−)5にパル
ス電圧を印加されていない状態(第6図(a) )にお
いてバリヤゲート9の下の領域11と蓄積ゲート10の
下の領域12の濃度差により旭ボテ//ヤルに差がつい
た結果、蓄積ゲート10の下に移動する。電荷のこの移
動は蓄積期間る。また、蓄積ゲー・ト10から600部
6への転送は埋込みチャンネルClCDモードであり、
この転送による電荷の取り残しは0002%以下とな9
、結果として残像特性の良い固体撮像装置が得られる。
In FIG. 5, when the photoelectric charge storage section 1 is irradiated with light, the charges photoelectrically converted in this region are transferred to the barrier gate 9 when no pulse voltage is applied to the digital camera 5 (FIG. 6(a)). As a result of the difference in density between the area 11 under the storage gate 10 and the area 12 under the storage gate 10, the area moves under the storage gate 10. This movement of charge takes an accumulation period. Further, the transfer from the storage gate 10 to the 600 unit 6 is in the embedded channel ClCD mode,
The amount of charge left behind due to this transfer is less than 0002%9
As a result, a solid-state imaging device with good afterimage characteristics can be obtained.

(発明の効果) 以上のように1本発明は、光電荷蓄積部に隣接する2段
ゲート下に埋込みチャノイ・ルを設けることにより、−
蓄積期間内の電荷転送効率を大幅に向上することができ
る。
(Effects of the Invention) As described above, the present invention provides -
Charge transfer efficiency within the storage period can be significantly improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第3図は、それぞれ従来のCCD固体撮像装
置の光電変換部近辺の断面図、第2図及び第4図は、そ
れぞれ第1図、第3図の各構造におけるポテンシャルを
示す図であり、(a)は蓄積期間、(b)は転送期間の
状態を示す。第5図は、本発明の一実施例におけるCC
D固体撮像装置の光電変換部近辺の断面図、第6図は、
第5図の構造におけるポテンシャルを示す図で、(a)
は蓄積期間、(b〕は転送期間の状態を示す。 5 ・・・・・川・ シフトゲート、 6 川・・曲C
CD部、9・・・・・・・・・バリアゲート、1o・・
・・・曲蓄積ゲート、11.12・・・・・・・・ウェ
ル領域。 特許出願人 松下電子工業株式会社 第1図 第2図 第3図 第4図 第5図 第6図
1 and 3 are cross-sectional views of the vicinity of the photoelectric conversion section of a conventional CCD solid-state imaging device, respectively, and FIGS. 2 and 4 are diagrams showing the potential in each structure of FIGS. 1 and 3, respectively. (a) shows the state of the storage period, and (b) shows the state of the transfer period. FIG. 5 shows the CC in one embodiment of the present invention.
FIG. 6 is a cross-sectional view of the vicinity of the photoelectric conversion section of the solid-state imaging device D.
A diagram showing the potential in the structure of Figure 5, (a)
indicates the storage period, and (b) indicates the state of the transfer period. 5... River Shift Gate 6 River... Song C
CD section, 9...Barrier gate, 1o...
...Track accumulation gate, 11.12...well area. Patent applicant Matsushita Electronics Co., Ltd. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

【特許請求の範囲】[Claims] 一導電型を有する半導体基板の表面に、前記−導電型と
は反対の導電型を有する光電荷蓄積部が形成され、前記
光電荷蓄積部の電位を決めるバリアゲートおよび蓄積ゲ
ートからなる2段ゲートを備え、前記2段ゲート直下に
、前記反対導電型を有する埋込みチャノネルが形成され
てなることを特徴とする電荷転送装置。
A photocharge accumulation section having a conductivity type opposite to the -conductivity type is formed on the surface of a semiconductor substrate having one conductivity type, and a two-stage gate consisting of a barrier gate and an accumulation gate that determines the potential of the photocharge accumulation section. A charge transfer device comprising: a buried channel having the opposite conductivity type formed directly under the two-stage gate.
JP58191668A 1983-10-15 1983-10-15 Charge transfer device Expired - Lifetime JPH0669089B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58191668A JPH0669089B2 (en) 1983-10-15 1983-10-15 Charge transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58191668A JPH0669089B2 (en) 1983-10-15 1983-10-15 Charge transfer device

Publications (2)

Publication Number Publication Date
JPS6084868A true JPS6084868A (en) 1985-05-14
JPH0669089B2 JPH0669089B2 (en) 1994-08-31

Family

ID=16278465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58191668A Expired - Lifetime JPH0669089B2 (en) 1983-10-15 1983-10-15 Charge transfer device

Country Status (1)

Country Link
JP (1) JPH0669089B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2656158A1 (en) * 1989-12-19 1991-06-21 Thomson Composants Militaires HYBRID PHOTOSENSOR.
KR100364792B1 (en) * 1999-11-03 2002-12-16 주식회사 하이닉스반도체 Solied state image sensor
WO2012098747A1 (en) * 2011-01-20 2012-07-26 浜松ホトニクス株式会社 Solid-state imaging device
US8841714B2 (en) 2011-01-14 2014-09-23 Hamamatsu Photonics K.K. Solid state imaging device
JP2019117949A (en) * 2019-04-08 2019-07-18 浜松ホトニクス株式会社 Solid-state imaging apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS558007A (en) * 1978-06-30 1980-01-21 Toshiba Corp Electric charge transferring device
JPS5698865A (en) * 1980-01-09 1981-08-08 Nec Corp Charge coupled device
JPS60105273A (en) * 1983-08-03 1985-06-10 フアウ・エ−・ベ−・ウエルク・フユ−ル・フエルンゼ−エレクトロニク・イム・フアウ・エ−・ベ−・コムビナ−ト・ミクロエレクトロニク Charge coupled type semiconductor sensor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS558007A (en) * 1978-06-30 1980-01-21 Toshiba Corp Electric charge transferring device
JPS5698865A (en) * 1980-01-09 1981-08-08 Nec Corp Charge coupled device
JPS60105273A (en) * 1983-08-03 1985-06-10 フアウ・エ−・ベ−・ウエルク・フユ−ル・フエルンゼ−エレクトロニク・イム・フアウ・エ−・ベ−・コムビナ−ト・ミクロエレクトロニク Charge coupled type semiconductor sensor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2656158A1 (en) * 1989-12-19 1991-06-21 Thomson Composants Militaires HYBRID PHOTOSENSOR.
KR100364792B1 (en) * 1999-11-03 2002-12-16 주식회사 하이닉스반도체 Solied state image sensor
US8841714B2 (en) 2011-01-14 2014-09-23 Hamamatsu Photonics K.K. Solid state imaging device
WO2012098747A1 (en) * 2011-01-20 2012-07-26 浜松ホトニクス株式会社 Solid-state imaging device
JP2012151364A (en) * 2011-01-20 2012-08-09 Hamamatsu Photonics Kk Solid state image sensor
KR20140015292A (en) * 2011-01-20 2014-02-06 하마마츠 포토닉스 가부시키가이샤 Solid-state imaging device
US9419051B2 (en) 2011-01-20 2016-08-16 Hamamatsu Photonics K.K. Solid-state imaging device
JP2019117949A (en) * 2019-04-08 2019-07-18 浜松ホトニクス株式会社 Solid-state imaging apparatus

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Publication number Publication date
JPH0669089B2 (en) 1994-08-31

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