JPH02253658A - Solid-state image sensing element - Google Patents

Abstract

PURPOSE:To reduce variations of a dark output and further reduce a residual image component included in an output signal by incorporating an impurity in the opposite conductivity type impurity layer in a self-alignment manner. CONSTITUTION:A P-type impurity layer 46 is formed in a self-alignment manner by the use of an ion implantation preventing film 52, so that there are produced less variations at a location of the end of a P-type impurity layer 46 on the side of a charge read gate 48 and are produced less variations of a dark output of a photodiode part 18. Additionally, the P-type impurity layer 46 has very thin thickness and hence is formed substantially over the entire surface of a photodiode N-type impurity layer 38. Hereby, when electric charge stored in a photodiode N-type impurity layer 38 is read out into a CCD channel N-type impurity layer 40 through a charge read gate 48, electric charge trapped in a potential dip is reduced and hence a residual component included in an electric signal outputted from the CCD image sensor is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device capable of reducing afterimage components included in its output and variations in dark output.

[Prior Art] FIG. 6 is an example of a solid-state image sensor, and is a schematic diagram showing the basic configuration of a CCD image sensor using a charge-coupled device (hereinafter abbreviated as CCD).

Referring to FIG. 6, this CCD image sensor 10 is
It includes a photosensitive section 12 that generates an electrical signal in response to incident light, and a horizontal CCD transfer section 14 that horizontally transfers the electrical signal output from the photosensitive section 12.

The photosensitive section 12 includes a plurality of unit pixels 16 regularly arranged in rows and columns in all directions.

Each unit pixel 16 includes a photodiode section 18 that performs photoelectric conversion in response to incident light and stores charges, and a vertical section that reads charges from the photodiode section 18 and sequentially transfers them in the direction of the horizontal CCD transfer section 14. A CCD transfer unit 20 is included. The vertical CCD transfer section 20 has a structure similar to that of a four-channel CCD shift register, and has terminals 22 and 24.
．． It has 26.28.

The horizontal CCD transfer section 14 has a structure similar to a two-phase CCD shift register, and has terminals 30 and 32.

FIG. 7 is an enlarged plan view showing the unit pixel 16 in detail,
FIG. 8 is a cross-sectional view of FIG. Referring to FIGS. 7 and 8, unit pixel 16 is provided on P-type well layer 36 formed on N-type silicon substrate 34. Referring to FIGS. The unit pixel 16 includes a photodiode N-type impurity layer 38 formed on a P-type well layer 36 and a CCD channel N-type of a vertical COD transfer section formed at a predetermined distance from the photodiode N-type impurity layer 38. Impurity layer 40
, a high concentration P+ impurity layer 42 for element isolation formed adjacent to the CCD channel N-type impurity layer 40, a photodiode N-type impurity layer 38, a CCD channel N-type impurity layer 40, a P+ impurity layer 42, etc. and a vertical silicon oxide film 37 formed on the CCD channel N-type impurity layer 40 and the P+ impurity layer 42 adjacent to the photodiode N-type impurity layer 38. It includes a CCD gate electrode 44 and a P-type impurity layer 46 formed on the surface of the photodiode N-type impurity layer 38 . a photodiode N-type impurity layer 38;
A portion of the P-type well layer 36 between the CCD channel N-type impurity layer 40 forms a charge read gate 48 .

The operation of the CCD image sensor 10 as an example of a conventional solid-state image sensor will be explained with reference to FIGS. 6 to 8. In response to light incident from the direction of the arrow in FIG. 8, photoelectric conversion occurs at the PN junction at the interface between the photodiode N-type impurity layer 38 and the P-type well layer 36. Charges generated by photoelectric conversion are accumulated in the photodiode N-type impurity layer 38 for a predetermined period of time.

When a high level potential is applied to the vertical CCD gate electrode 44, a channel is formed under the charge read gate 48. The charges accumulated in the photodiode N-type impurity layer 38 pass through this channel to the CCD channel N.
Moving on to the type impurity layer 40.

The charge transferred to the CCD channel N-type impurity layer 40 is transferred to a horizontal CCD similar to the charge transfer in a general four-phase CCD shift register by pulse voltages sequentially applied between terminals 22, 24, 26 and 28. It is transferred in the direction of section 14. This direction is indicated by arrow V in FIG. The charges transferred to the horizontal CCD transfer section 14 are sequentially sent toward a processing circuit (not shown) by a shift register operation using a pulse voltage applied between terminals 30 and 32. This direction is indicated by arrow H in FIG.

Two-dimensional image information is converted into electrical signals as described above.

P-type impurity layer 46 has two functions. The function of the - side is to fix the surface potential of the photodiode section 18. P-type impurity layer 46 is connected to P1 impurity layer 42. The P+ impurity layer 42 is electrically fixed to a ground potential (hereinafter referred to as GND). The potential of the P-type impurity layer 46 is also G.
Fixed to ND.

Without the P-type impurity layer 46, the surface potential of the potential profile in the depth direction of the photodiode section 18 depends on the photodiode potential and the overflow control voltage applied between the P-type well layer 46 and the N-type silicon substrate 34. It may become deeper. If this surface potential becomes deep, there is a possibility that charges will be left behind in this portion when charges are read out from the photodiode section 18 to the vertical CCD transfer section 20. When residual charge is generated, an afterimage component is generated in the electrical signal 10 output from the CCD image sensor IO. The P-type impurity layer 46 is for fixing the surface potential of the photodiode section 18 to GND to prevent the potential profile from becoming deep.

The other function of the P-type impurity layer 46 is to reduce the dark output of the photodiode section 18.

An interface level exists at the interface between the photodiode N-type impurity layer 38 and the silicon oxide film 37 on the surface thereof. This interface level causes the dark output of the photodiode section 18 to occur. Therefore, on the surface of the photodiode N-type impurity layer 38, an impurity layer of a conductivity type opposite to that of the photodiode N-type impurity layer 38, that is, a P-type impurity layer is formed.

In this case, the P-type impurity layer 46 functions as a source of holes to the interface level, and the photodiode surface is not depleted. Therefore, the dark output generated in the photodiode section 18 due to the interface state at the interface between the photodiode N-type impurity layer 38 and the silicon oxide film 37 on its surface is reduced.

[Problem to be solved by the invention] However, in the conventional solid-state image sensor, the P-type impurity layer 4
No. 6, there is a problem in that variations in the shape of the end on the read gate 48 side cause variations in the magnitude of the dark output. Further, there is a problem in that charges that are not read out to the CCD channel N-type impurity layer 40 are generated between the charge readout gate 48 and the P-type impurity layer 46. Therefore, an afterimage component appears in the output signal of the photodiode section 18.

FIG. 9 is a cross-sectional view of the solid-state imaging device showing the process of forming the P-type impurity layer 46. Referring to FIG. 9, in the conventional solid-state imaging device formation process, the P-type impurity layer 46 on the surface of the photodiode N-type impurity layer 38 is removed by ion implantation using a patterned photoresist 50 as a mask. It is formed.

The end of the P-type impurity layer 46 on the charge readout gate 48 side is determined by the photoresist 50.

The thickness of the sidewall portion of the vertical CCD gate electrode 44 of the photoresist 50 is about 0.6 to 0.8 μm. In the photo process, variations occur in the thickness of this side wall portion. Therefore, the charge readout gate 4 of the P-type impurity layer 46
Variations also occur in the position of the end on the 8 side. Depending on the size of the area of the P-type impurity layer 46, the value of the dark output due to the interface state at the interface between the photodiode N-type impurity layer 38 and the silicon oxide film 37 varies. Therefore, variations in the dark output of the photodiode section 18 occur.

FIG. 10 is a potential profile of the photodiode shown in FIG. 9. A curve a shown by a solid line in FIG. 10 shows a potential profile of a cross section taken along the line A--A in FIG. 9. The curved line indicated by a dotted line in FIG. 10 represents the potential profile of a cross section taken along the line B--B in FIG. 9.

As shown in FIG. 10, the potential profile of the portion where the P-type impurity layer 46 is formed is deeper than that of the portion where the P-type impurity layer 46 is not formed. Therefore, a portion of the charge read out from the photodiode N-type impurity layer 38 passing under the charge readout gate 48 accumulates in the deeper potential dip portion of this potential profile. In this part, the readout of charges becomes incomplete, and one accumulated charge will be outputted at the next readout. Therefore, the output of this photodiode will include an afterimage component.

In order to avoid the above-mentioned problem, a method may be considered in which the end of the P-type impurity layer 46 on the charge readout gate 48 side is determined by the vertical CCD gate electrode 44. However, in this case, the P-type impurity layer 46 is also formed in the channel region under the read gate 48. Therefore, the charge is CC
When reading into the D channel N type impurity layer 40, the inside of the photodiode N type impurity layer 38 is not depleted. The succession of charges is incomplete, and in this case as well, afterimage components are included in the output electrical signal.

Therefore, an object of the present invention is to provide a solid-state image sensor that has less variation in dark output and is capable of reducing afterimage components included in the output signal.

[Means for Solving the Problems] A solid-state imaging device according to the present invention includes a plurality of unit regions arranged on a semiconductor substrate, each unit region having a region of a certain conductivity type on the surface side and a layer below the region. a photoelectric conversion section including a semiconductor junction with a region of opposite conductivity type, a charge transfer section adjacent to the photoelectric conversion section, and a charge readout control section that controls readout of charge from the photoelectric conversion section to the charge transfer section. an impurity layer of an opposite conductivity type, which is formed on the surface of a region of a certain conductivity type on the surface side of the semiconductor junction of the photoelectric conversion section, for fixing the potential of the surface of the region of a certain conductivity type.

The solid-state imaging device according to the present invention is characterized in that impurities are introduced into the reverse conductivity type impurity layer in a self-aligned manner.

[Operation] In the solid-state imaging device having the above-described configuration, impurities are introduced into the reverse conductivity type impurity layer in a self-aligned manner.

Therefore, the position of the end on the charge readout control section side does not include variations due to the patterning process of the photoresist as in the conventional case. Therefore, on the surface of the photoelectric conversion part,
The variation in area of the opposite conductivity type impurity layer is reduced.

Furthermore, the area of the portion of the surface of the photoelectric conversion section where the reverse conductivity type impurity layer is not formed is reduced compared to the case where a photoresist is used as in the past.

Therefore, there is no portion where the potential profile becomes deep in the photoelectric conversion section.

[Embodiment] FIG. 1 is an enlarged plan view of one unit pixel 16 of a CCD image sensor as an embodiment of the solid-state image sensor according to the present invention. FIG. 2 is a cross-sectional view of FIG. The overall outline of the CCD image sensor of this embodiment is similar to that of the conventional image sensor described with reference to FIG.

Referring to FIGS. 1 and 2, this image sensor includes an N-type silicon substrate 34, a P-type well layer 36 formed on the N-type silicon substrate 34, and a P-type well layer 36 formed on the P-type well layer 36. A photodiode N-type impurity layer 38 , a P+ impurity layer 42 for element isolation provided adjacent to one side of the photodiode N-type impurity layer 38 , and a photodiode N-type impurity layer 38 on the other side of the photodiode N-type impurity layer 38 . Diode N
A CCD channel N-type impurity layer 40 for charge transfer formed at a predetermined distance from the type impurity layer 38, a silicon oxide film 37 formed on the surface of the P-type well layer 36, and a silicon oxide film 37 on the silicon oxide film 37. , a vertical CCD gate electrode 44 formed in a portion where the photodiode N-type impurity layer 38 is not formed, covering the CCD channel N-type impurity layer 40 and having one end in contact with the photodiode N-type impurity layer 38; , an ion implantation blocking film 52 uniformly formed on the surface of the vertical CCD gate electrode 44 by thermal oxidation, and a P-type impurity layer 46 formed by ion implantation using the ion implantation blocking film 52 as a mask. The CCD channel N-type impurity layer 40 is a P+ impurity layer 42 for element isolation.
Therefore, it is separated from the photodiode N-type impurity layer 38 of the adjacent unit pixel.

The portion of the P-type well layer 36 between the photodiode N-type impurity layer 38 and the CCD channel N-type impurity layer 40 is
A charge readout gate 48 having the vertical CCD gate electrode 44 as a gate is formed.

The ion implantation blocking film 52 is formed, for example, by thermal oxidation. Therefore, it is easy to adjust the film thickness.

For example, the side walls of the vertical CCD gate electrode 44 have a film thickness of 1
It is possible to form it uniformly with OA of 000 to 200OA.

The image sensor shown in FIG. 1 and FIG.
An ion implantation blocking film 52 is newly added to the conventional image sensor shown in FIGS. Furthermore, the image sensor shown in FIGS. 1 and 2 differs from conventional image sensors in that the P-type impurity layer 46 is formed in a self-aligned manner using the ion implantation blocking film 52 as a mask. There is. - otherwise the image sensor shown in FIGS. 1 and 2 has a structure similar to the image sensor shown in FIGS. 7 and 8;
Corresponding parts are given the same reference numerals and names. Furthermore, since the functions of each part are the same, detailed explanation will be omitted here.

In the image sensor shown in FIGS. 1 and 2, the P-type impurity layer 46 is formed in a self-aligned manner using the ion implantation blocking film 52 as a mask. Therefore, there is no variation in the position of the end of the P-type impurity layer 46 on the charge read gate 48 side. Therefore, variations in the output of the photodiode section 18 during dark times are reduced. Further, the P-type impurity layer 46 is puffed to a thickness of about 1,000 to 2,000 layers. This film thickness is 0.6 the film thickness of the photoresist in the conventional technology.
It is very small compared to ~0.8 μm. Therefore, P
The type impurity layer 46 is the photodiode N type impurity layer 38.
It is formed almost entirely on the top.

Conversely, the area of the portion on the photodiode N-type impurity layer 38 where the P-type impurity layer 46 is not formed is very small. Therefore, in the photodiode N-type impurity layer 46, there is almost no portion where the potential profile becomes deep.

As a result, when the charge in the photodiode N-type impurity layer 38 is read out to the CCD channel N-type impurity layer 40 via the charge readout gate 48, the amount of charge accumulated in the potential data is reduced.

Therefore, the afterimage component included in the electrical signal output from the CCD image sensor is reduced.

The ion implantation blocking film 52 is formed on the side wall of the vertical CCD gate electrode 44 to a predetermined thickness. Therefore, during formation by ion implantation, the P-type impurity layer 46 does not enter under the charge read gate 48. Therefore, charges are completely read out from the photodiode N-type impurity layer 38. Therefore, in the conventional technology, the P-type impurity layer 4
6 is determined by the vertical CCD gate electrode 44, no afterimage components are included in the signal output of the image sensor.

3A to 3C are cross-sectional views showing a part of the process for manufacturing the CCD image sensor of FIG. 2. FIG. Third
Figure C corresponds to Figure 2.

Referring to FIG. 3A, a P-type well layer 36 formed on an N-type silicon substrate 34, a photodiode N-type impurity layer 38 formed on the P-type well layer 36, and a photodiode N-type impurity layer 38 formed on the P-type well layer 36 are formed using a known technique. A P+ impurity layer 42 for element isolation formed adjacent to one side of the diode N-type impurity layer 38 and a predetermined distance from the photodiode N-type impurity layer 38 are formed on the other side of the photodiode N-type impurity layer 38. a CCD channel N-type impurity layer 40 formed in
A vertical CCD gate electrode 44 formed on the CCD channel N-type impurity layer 40 and in contact with the photodiode N-type impurity layer 38 is prepared.

Referring to FIG. 3B, an ion implantation blocking film 52 having a thickness of 1,000 to 2,000 thick is formed by thermal oxidation to cover the entire surface of the vertical CCD gate electrode 44. Ion implantation is performed using the ion implantation blocking film 52 as a mask.

Referring to FIG. 3C, P-type impurity layer 4 is formed by ion implantation.
6 is formed to obtain the photodiode of this example.

FIG. 4 is a sectional view of a CCD image sensor according to another embodiment of the invention. In this embodiment, an ion implantation blocking film 54 is formed only on the side walls of the vertical CCD gate electrode 44 in place of the ion implantation blocking film 52 of the previous embodiment. The P-type impurity layer 46 is an ion implantation blocking film 54.
Since it is formed by ion implantation using a mask, it is formed in the same shape as the P-type impurity layer 46 in the first embodiment. Therefore, the CCDC tie sensor according to this embodiment also exhibits the same effects as the CCD image sensor shown in FIGS. 1 and 2.

5A to 5C are cross-sectional views showing a part of the process of obtaining the CCD image sensor of FIG. 4.

FIG. 5A is completely similar to FIG. 3A, and detailed explanation thereof will be omitted.

Referring to FIG. 5B, a silicon oxide film 54 is formed over vertical CCD gate electrode 44 by, for example, vapor phase growth. Thereafter, the ion implantation blocking film 54 is formed by leaving the silicon oxide film only on the side walls of the vertical CCD gate electrode 44 using an etch-back method. Using the ion implantation blocking film 54 as a mask, boron or the like is implanted into the surface of the photodiode N-type impurity layer 38 by ion implantation to form a P-type impurity layer 46.

Also in this embodiment, the ion implantation blocking film 54 is formed to have a uniform thickness. In addition, it is easy to adjust the film thickness, and 1
An ion implantation blocking film 54 having a thickness of approximately 0.000 to 200 OA is formed.

Also in the CCD image sensor according to this example,
P-type impurity layer 46 is photodiode N-type impurity layer 38
It is formed in a self-aligned manner covering almost the entire surface of the surface. Therefore, as in the first embodiment, variations in the dark output of each photodiode and afterimage components included in the output signal are reduced.

Note that this invention is not limited to the above-described embodiments.

For example, it goes without saying that similar effects can be obtained even if the conductivity types of the above-described embodiments are reversed.

[Effects] In the solid-state imaging device according to the present invention, impurities are introduced into the reverse conductivity type impurity layer in a self-aligned manner. Therefore, the position of the end of the opposite conductivity type impurity layer on the charge readout control section side is constant. Therefore, in the photoelectric conversion section, variations in the area of the reverse conductivity type impurity layer on the surface thereof are reduced, and variations in the dark output of the solid-state image sensor are also reduced.

Further, on the surface of the photoelectric conversion section, the area of the portion where the reverse conductivity type impurity layer is not formed is small.

Therefore, since no reverse conductivity type impurity layer is formed in the photoelectric conversion section, there is no portion where the potential profile becomes deep. Therefore, when reading out the charges of the charge conversion section, the amount of charges that are accumulated in a deep part of the potential profile and are not read out is reduced. Therefore,
Afterimage components are less likely to be included in the output of the solid-state image sensor.

That is, it is possible to provide a solid-state imaging device with less variation in dark output and with reduced afterimage components included in the output signal.

[Brief explanation of drawings]

FIG. 1 shows a CC as a solid-state image sensor according to an embodiment of the present invention.
FIG. 2 is an enlarged plan view of one unit pixel of the D image sensor; FIG.
3C are cross-sectional views showing a part of the manufacturing process of the CCD image sensor shown in FIGS. 1 and 2, and FIG. 4 is a sectional view showing a part of the manufacturing process of the CCD image sensor shown in FIGS. 5A to 5C are sectional views showing a part of the manufacturing process of the CCD image sensor shown in FIG. 4; FIG. 6 is a general sectional view of one unit pixel of a CCD image sensor; FIG. 7 is an enlarged plan view of one unit pixel of a CCD image sensor as an example of a conventional solid-state image sensor, and FIG. 8 is a schematic plan view showing the configuration of a CCD image sensor. 9 is a schematic cross-sectional view showing one step in the manufacturing process of a conventional photodiode, and FIG. 10 is a cross-sectional view taken in the direction A--A of FIG. It is a graph showing a potential profile of the photodiode section 18 in a cross section taken in the direction of arrow B. In the figure, 34 is an N-type silicon substrate, 36 is a P-type well layer, 37 is a silicon oxide film, and 38 is a photodiode N.
type impurity layer, 40 is a CCD channel N type impurity layer, 4
2 is a P+ impurity layer, 44 is a vertical CCD gate electrode, 46
48 is a charge reading gate, and 52 and 54 are ion implantation blocking films. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 3A Figure 54: A left 3 main λ? And t3 further Figure 5A Figure 5C Figure

Claims (1)

[Claims] (1) A photovoltaic device including a plurality of unit regions arranged on a semiconductor substrate, each unit region including a semiconductor junction between a region of a certain conductivity type on the front side and a region of an opposite conductivity type in a lower layer. a conversion section; a charge transfer section adjacent to the photoelectric conversion section; and a charge readout control section that controls readout of charges from the photoelectric conversion section to the charge transfer section; In a solid-state image sensing device, an impurity layer of a reverse conductivity type is formed on the surface of a region of a certain conductivity type on the front side and is provided with an impurity layer of a reverse conductivity type for fixing the potential of the surface of the region of the certain conductivity type. A solid-state imaging device characterized in that the impurity layer has impurities introduced in a self-aligned manner.