JP2738589B2 - Solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly, to an improvement in a structure of a light receiving section of a solid-state imaging device with a small dark current and a driving method thereof.

[Conventional technology]

FIG. 4 (a) shows, for example, IEE International Solid-State Circuits
Conference Digest of Technical Papers 1982 166, 167, "CCD Linear Image Sensor" (IEEE ISSCC82 Digest of Technical Papers pp.1)
FIG. 66, 167 “A CCD Linear Image Sensor”) is a plan view showing a configuration of a light receiving section of a solid-state imaging device by a conventional skimming method.

In the figure, 1 is a photodiode, 2 is a control (SC) gate for controlling the potential of the photodiode, 3 is an accumulation (ST) gate for accumulating signal charges, and 4 is a charge transfer element described below. Transfer (TG) to transfer to
The gate 5 is a charge transfer element (hereinafter abbreviated as CTD) for transferring a signal charge to an output unit (not shown), and transfers the charge in the y direction in the figure.

FIG. 4 (b) is a diagram showing a cross-sectional structure of a portion AB in FIG. 4 (a).

In the figure, reference numeral 6 denotes, for example, a P-type Si semiconductor substrate, 7 denotes an element isolation region composed of a high-concentration P-type layer, 8 denotes an N-type region constituting the photodiode 1, and 9 denotes an N-type region forming a charge transfer channel. It is. In this example, a buried channel charge-coupled device (BCCD) is shown as CTD5. 10 is BC
A transfer electrode constituting a CD, 11 is an insulating film made of, for example, SiO ₂ , and 12 is a light-shielding film made of a material such as Al to prevent light from being incident on portions other than the photodiode portion.

FIG. 5 is a clock timing chart applied to the ST gate 3 and the TG gate 4, and FIGS. 6 (a) and 6 (b) show potential diagrams at t = t ₁ and t = t ₂ in FIG. FIG.

 Next, the operation will be described.

In FIG. 5, a constant voltage V _S is applied to the ST gate 3. The SC gate 2 has a constant voltage smaller than V _S
V _C is given. Therefore, the potential diagram in the AB of FIG. 4 in t = t ₁ (a) sixth
The result is as shown in FIG. The potential of one part of the photodiode is
Since the charge is determined by the potential under the SC gate 2, when charge is generated by light, the charge 14 is stored under the ST gate 3. Reference numeral 13 denotes the charge in the photodiode.

In FIG. 5, when t = t ₂ , the TG gate 4 goes to the high level, and as shown in the diagram at t = t ₂ in FIG.
The signal charge under gate 3 is transferred to BCCD5.

Note that in t = t ₁ of FIG. 6 (a), BCCD5 so doing charge transfer, the potential is varied in the range indicated by the arrows in FIG.

[Problems to be solved by the invention]

In the conventional light receiving unit, the constant DC voltage V _S to the ST gate 3 is applied to generate via an interface level existing in Si-SiO ₂ interface, there is a disadvantage that the dark output is large.

FIG. 7 shows a band diagram in the Z direction below the ST gate 3 in FIG. 4 (b). Since the ST gate 3 is given a DC voltage V _S band are bent downward,
The curve B is shown in the figure. In FIG, E _C represents the bottom of the conduction band, E _V represents the top of the valence band, E _F denotes a Fermi level. Reference numeral 15 denotes an interface state existing between the Si substrate 6 and the SiO ₂ film 11. Interface state and the band gap (E _C
Although many exist between E and _V ), only one is shown in the figure for convenience.

Since the ST gate 3 is fixed at the High level for a long time, the interface state is almost filled with electrons excited from the valence band by thermal excitation. In FIG. 7, a mark indicated by a circle indicates that the interface state is filled with electrons.

These electrons are excited by the thermal excitation into the conduction band and have a dark output. Since such dark output becomes background noise, it causes the S / N under a low illuminance to be significantly deteriorated.

The present invention has been made in order to solve the above-described problems, and provides a light receiving unit having a small dark output. .

[Means for solving the problem]

The solid-state imaging device according to the present invention has a structure in which the storage gate includes at least one or more electrodes, and a signal charge of a type opposite to the signal charge is provided at an interface between the semiconductor substrate and the insulating film for a certain period during the storage period for storing the signal charge. A voltage sufficient to induce carriers is applied to the storage gate.

[Action]

According to the present invention, the storage gate is not fixed at the high level for a long time, and a period in which the interface state is filled with holes occurs for a certain period. As a result, in order to generate a dark output, it is necessary to fill the interface state with electrons again, and the dark output is significantly reduced as compared with the related art.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1A shows a plan view of a light receiving section of a solid-state imaging device according to a first embodiment of the present invention, and FIG. 1B shows a cross-sectional view of a section AB in FIG. Fig. 7 (a) (b)
Is different from the structure shown in FIG. 1 in that the storage gate is divided into two parts, a first storage gate (STI) and a second storage gate (STI).
II), which is 3 and 1 in the figure.
Shown at 6.

FIG. 2 shows a timing chart of the clock applied to this element. Clocks that alternately go to the LL level are applied to the two storage gates ST I3 and ST II16.
Here, the LL level is a voltage sufficient to accumulate holes at the Si-SiO ₂ interface. A potential diagram along AB in FIG. 1A at times t ₀ , t ₁ , and t ₂ in FIG.
Shown in the figure. As can be seen from the drawing, the signal charge 14 is the storage gate.
The interface is in a hole accumulation state while the signal charge is not accumulated, moving back and forth below 3,16, contributing to a reduction in dark output. This is due to the following mechanism. Electrons excited to the interface state when the ST I or ST II gate is at the H level
During the period in which the LL level is given, the electrons recombine with holes, and electrons hardly exist in the interface states. When the level becomes H level again, in order to excite the electrons into the valence band, the electrons must be excited again to the interface state, so that the dark output is suppressed. Furthermore, in the present invention, since the potential of the photodiode does not change during the accumulation period, the advantage of the skimming method that the linearity of sensitivity to light intensity is good is not impaired. In FIG. 3, + indicates holes accumulated under the accumulation gate.

In the first embodiment, the PN junction type is described as the photodiode. However, a so-called buried photodiode structure in which a P ⁺ layer is provided on the surface and the N layer is completely depleted may be used.

In the above embodiment, the ST gate 3 and the SC gate 2 are of the surface channel type. However, the ST gate 3 and the SC gate 2 may be of the buried channel type.

Alternatively, the relationship between the P-type and the N-type may be switched, and holes may be used as signal charges. However, in this case, the positive / negative relationship between the clocks is completely reversed.

Further, the transfer gate 4 may also be used as the transfer electrode 10 of the charge transfer element 5.

〔The invention's effect〕

As described above, according to the present invention, the storage gate has a structure including at least two or more electrodes, and during the accumulation period for accumulating signal charges, an interface opposite to the first type is formed at the interface between the semiconductor substrate and the insulating film. A first voltage sufficient to induce a second type of carriers and a second voltage not otherwise are alternately applied to the two or more electrodes such that the first voltage is not applied simultaneously to one another. Therefore, the linearity of the output with respect to the light intensity can be improved, the dark current under the storage gate can be suppressed, and a solid-state imaging device having a good S / N even at low illuminance can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing the structure of a light receiving section of a solid-state imaging device according to a first embodiment of the present invention, FIG. 2 is a clock timing diagram applied to the embodiment of FIG. 1, and FIG. Time t =
A diagram showing a potential diagram at t ₀ , t ₁ , t ₂ ,
Figure 4 (a) (b) is a diagram showing a structure of a light receiving portion of a conventional solid-state imaging device, Fig. 5 conventional clock timing diagram, FIG. 6 is a time t = t ₁ of FIG. 5, t ₂ FIG. 7 is a diagram illustrating a mechanism of generation of dark output. In the figure, 1 is a photodiode, 2 is a control gate, 3 and 16 are storage gates, 4 is a transfer gate, 5 is a charge transfer element, 6 is a P-type semiconductor substrate, 7 is a high-concentration P-type element isolation region, 9 is an N-type region, 10 is a transfer electrode, 11 is an insulating film, 12 is a light shielding film, 1
3, 14 are electric charges. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] A photoelectric conversion element, a storage gate having an MIS structure for storing a first type of signal charge obtained from the photoelectric conversion element, a charge transfer element for transferring the charge stored in the storage gate, In a solid-state imaging device including a light-receiving unit based on a so-called skimming method including a transfer gate provided between the storage gate and the charge transfer device, the storage gate includes at least two or more electrodes. During an accumulation period for accumulating electric charges, a first voltage sufficient to induce a second type of carrier opposite to the first type at an interface between the semiconductor substrate and the insulating film, and a second voltage that is not the same are set to the above-mentioned values. A solid-state imaging device characterized in that the first voltage is alternately applied to two or more electrodes so that the first voltage is not applied simultaneously to each other.