JPS6079775U - integrated circuit device - Google Patents

integrated circuit device

Info

Publication number
JPS6079775U
JPS6079775U JP17358483U JP17358483U JPS6079775U JP S6079775 U JPS6079775 U JP S6079775U JP 17358483 U JP17358483 U JP 17358483U JP 17358483 U JP17358483 U JP 17358483U JP S6079775 U JPS6079775 U JP S6079775U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
solder
conductive pattern
surface contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17358483U
Other languages
Japanese (ja)
Inventor
福井 逸雄
中川 文男
Original Assignee
関西日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 関西日本電気株式会社 filed Critical 関西日本電気株式会社
Priority to JP17358483U priority Critical patent/JPS6079775U/en
Publication of JPS6079775U publication Critical patent/JPS6079775U/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の集積回路装置の部分平面図、第2図は第
1図の一部拡大図、第3図は第2図のA−A線に沿う断
面図、第4図は第3図のB−B線に沿う断面図、第5図
は本考案の一実施例を示す部分平面図、第6図は第5図
の一部拡大図、第7図は第6図のC−C線に沿う断面図
、第8図及び第9図は本考案の他の各実施例を示す部分
側断面図である。 7・・・絶縁基板、8・・・導電パターン、9.9’。 9″・・・電子部品、10・・・部品本体、11・・・
リード、llc、lid・・・半田溜り部、12・・・
半田。 第6図 第8図 一 第9図
FIG. 1 is a partial plan view of a conventional integrated circuit device, FIG. 2 is a partially enlarged view of FIG. 1, FIG. 3 is a sectional view taken along line A-A in FIG. 2, and FIG. 5 is a partial plan view showing an embodiment of the present invention, FIG. 6 is a partially enlarged view of FIG. 5, and FIG. A sectional view taken along line C, and FIGS. 8 and 9 are partial side sectional views showing other embodiments of the present invention. 7... Insulating substrate, 8... Conductive pattern, 9.9'. 9″...Electronic component, 10...Part body, 11...
Lead, llc, lid...solder pool, 12...
solder. Figure 6 Figure 8- Figure 9

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電子部品の本体より導出した複数のリードと絶縁基板上
に形成した導電パターンとを半田を介して面接触させ接
続したものにおいて、前記導電パターンと接続するリー
ドの面接触部分の一部を屈曲し余分な半田を吸収する半
田溜め部を形成したことを特徴とする集積回路装置。
In a device in which a plurality of leads led out from the main body of an electronic component and a conductive pattern formed on an insulating substrate are connected by surface contact via solder, a part of the surface contact portion of the lead connected to the conductive pattern is bent. An integrated circuit device characterized in that a solder reservoir is formed to absorb excess solder.
JP17358483U 1983-11-08 1983-11-08 integrated circuit device Pending JPS6079775U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17358483U JPS6079775U (en) 1983-11-08 1983-11-08 integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17358483U JPS6079775U (en) 1983-11-08 1983-11-08 integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6079775U true JPS6079775U (en) 1985-06-03

Family

ID=30378111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17358483U Pending JPS6079775U (en) 1983-11-08 1983-11-08 integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6079775U (en)

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