JPS6075119A - Comparison circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction against pulse noise other than an input signal or at transient state by providing a logical circuit generating an output only when a signal is outputted alternately from the 1st and 2nd comparators. CONSTITUTION:A common input terminal 16 to the 1st and 2nd comparators 12, 14 is formed and a comparison input signal is given thereto. The 1st and 2nd comparison levels VREF1, VREF2 are set to the comparators 12, 14. The 1st comparison level VREF1 is set to a positive amplitude giving a positive signal component to a non-signal level of the input signal and the 2nd comparison level VREF2 is set to a negative amplitude corresponding to the 1st comparison level VREF1. An output of the comparators 12, 14 is given to a logical circuit 22 generating an output when the outputs are inputted alternately and the output is extracted from an output terminal 24. If no alternate output is generated because of malfunction in any of the 1st and 2nd comparators 12, 14 in this case, no output is produced from the logical circuit 22.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a comparison circuit, and particularly to prevention of malfunctions when power is turned on.

FIG. 1 shows a typical comparator. An input signal to be compared is applied to the non-inverting input terminal 4 of the comparator 2, and a comparison level V is applied to the inverting input terminal 6 by a reference voltage source 8.
RE_F is set, and its comparison output can be taken out from the output terminal 10.

Now, the AC signal shown in FIG. 2A is applied to the non-inverting input terminal 4, and the comparison level vRE not shown in FIG. 2A is applied to the inverting input terminal 6.
When F is set, the comparison level vRE is output to the output terminal 10.
During the input signal period exceeding F, the comparison output shown in FIG. 2B, in which the output is inverted, is generated.

In such a comparator 2, when the power supply voltage is established when the power is turned on as shown in FIG. 3A, the transient signal S shown in FIG. 3B is input to the input terminal 4 or 6, and this transient signal input There is a risk of malfunction.

This invention proposes a comparison circuit (J4) that prevents malfunction when configured with a single comparator and generates a highly accurate comparison output.
With the goal.

This invention provides a first comparator with a first comparison level set, a second comparator with a second comparison level set, and a common input signal provided to these first and second comparators. The present invention is characterized in that it is constructed from a logic circuit which is provided with a comparison output obtained by the comparison and which generates the logic output.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.

FIG. 4 shows an embodiment of the comparison circuit of the present invention. In the figure, this comparison circuit includes first and second comparators 12.
．． 14 is installed, and the non-inverting input terminal (+) of the comparator 12
A common input terminal 16 is formed at the inverting input terminal (=) of the comparator 14 and the comparator 14, and a comparison input signal is applied thereto. Also,
The inverting input terminal (-) of the comparator 12 and the non-inverting input terminal (+) of the comparator 14 are individually provided with input terminals 1 and 20, and the input terminal 18 is provided with a first comparison level VR.
EF+, the input terminal 20 has a second comparison level vREF
2 are set respectively. First comparison level VR
E F I is set to the positive amplitude side, which is a positive signal component with respect to the no-signal level of the input signal, and the second comparison level VRE
F 2 is set to the negative amplitude side corresponding to the first comparison level vRE F I, which is a negative signal component.

The output of each comparator 12.14 is applied to a logic circuit 22 which generates an output only when each output is input alternately;
Its output can be taken out from the output terminal 24.

According to such a configuration, when the power is turned on, even if a malfunction occurs in either the first comparator 12 or the second comparator 12 or 14, if the outputs of both comparators do not occur alternately, the logic circuit 22 will output no output. Therefore, it is possible to prevent malfunction output from occurring. Furthermore, during transient times, malfunctions can be prevented even with pulse noise other than the input signal.

FIG. 5 shows a specific example of the circuit configuration of the logic circuit 22, and parts common to the embodiment shown in FIG. 4 are given the same reference numerals. The logic circuit 22 is composed of switching circuits 26 and 28, and the switching circuit 26 receives the output of the comparator 12 applied to its input terminal 30, and the switching circuit 2B receives the switching output from the output of the comparator 14 applied to its input terminal 32. generated and its combined output is output terminal 2.
It is configured to be taken out from 4. That is, the switching circuit 26 includes transistors 36.38 and resistors 40.42.
and a capacitor 44, a transistor 36,
The resistor 40 and the capacitor 44 constitute a tornado wave generation circuit, and the transistor 38 and the resistor 42 constitute a gate circuit. Further, the switching circuit 28 includes transistors 46 and 48,
It is composed of a resistor 50 and a capacitor 52, and its configuration is similar to that of the switching circuit 26. A driving voltage Vcc is applied between the common power supply terminal 54 and the reference potential point terminal 56.

The operation of such a configuration will be explained in detail with reference to FIG. An AC signal is applied to the input terminal 16,
When the comparison level VREFI is set on the positive signal component side (positive amplitude side) with respect to the no-signal level of the AC signal level, and the comparison level vRE F 2 is set on the negative signal component side (negative amplitude side), the AC signal level The comparator 12 generates an inverted output during a period in which VREFI exceeds the comparison level VREFI, and
Comparator 1 during the period when comparison level VRE becomes lower than F2
4 produces an inverted output. In this case, the output of the comparator 12 is the pulse shown in FIG. 6A, and the output of the comparator 14 is the pulse shown in FIG. 6B.
Let the pulse be as shown in .

During the high level (H) period of the pulse shown in FIG. 6A, the transistor 36 is in a conductive state, and after passing through that period, the transistor 36 is in a non-conductive state, and in response to the switching operation of the transistor 36, the capacitor 36 is turned on. 44 is charged through the resistor 40 and discharged through the transistor 36 when the transistor 36 is conductive. FIG. 6C shows the transition of the terminal voltage due to charging and discharging of the capacitor 44, which appears in the form of a tornado voltage.

Further, in the high level (I()) section of the pulse shown in FIG. Charging and discharging are repeated, and the final voltage becomes an overtopping voltage as shown in Figure 6.

When such an overflow voltage is applied to the transistor 38 or the transistor 48, the voltage value is changed to the transistor 38.
．． In the section where the threshold level Vs of 48 is exceeded, the transistor 38 or 48 becomes non-conductive,
A signal output is generated at the output terminal 24 by combining the outputs of the picture transistors 38 and 48, and as shown in FIG. This is the pulse output.

In this way, the comparison output is not generated unless both of the outputs of the comparators 12 and 14 are established alternately, so the generation of the output is prohibited in the transient state when the power is turned on, and malfunctions during the transient can be prevented, making it reliable. It is possible to generate a highly accurate comparison output.

In the embodiment, the case where two sets of comparators are installed has been described, but the same effect can be expected in the case where three or more comparators are installed.

As described above, according to the present invention, it is possible to prevent malfunctions and generate a highly reliable comparison output in a transient state when the power is turned on.

[Brief explanation of the drawing]

Fig. 1 is a program diagram showing a general comparator, Fig. 2 is an explanatory drawing showing its operation, Fig. 3 is an explanatory drawing showing malfunction when the power is turned on, and Fig. 4 is a comparator circuit of the present invention. FIG. 5 is a circuit diagram showing a specific circuit configuration example of the comparison circuit of the present invention, and FIG. 6 is a waveform explanatory diagram showing the operation of the embodiment shown in FIG. 12...first comparator, 14...second comparator, 2
2...Logic circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (3)

[Claims] (1) A first comparator with a first comparison level set, a second comparator with a second comparison level set, and
and a logic circuit that is provided with a comparison output obtained by applying a common input signal to the second comparator and generates the logical output. (2) The first comparator operates only with positive signal components relative to the input no-signal level, and the second comparator operates only with negative signal components relative to the input no-signal level. A comparison circuit according to claim 1, characterized in that the comparison circuit is constructed as follows. (3) The comparison circuit according to claim 1, wherein the logic circuit is configured to generate an output only when the outputs of the first and second comparators are alternately input. .