JPH01144720A - Double pulse forming circuit - Google Patents

Abstract

PURPOSE:To stably obtain a double pulse by comparing an input signal, which is monotonously increased or decreased, with two reference voltages, forming a first pulse, forming a signal, which is monotonously increased or decreased, by a time constant circuit with synchronizing to the formation of the first pulse, comparing this signal with the two reference voltages and forming the second pulse. CONSTITUTION:When the input signal is between reference voltages V1 and V2, the output of a comparator A1 goes to be L H. However, since the output of a comparator A2 is still H, the output of an AND gate G1 goes to be H. When the input signal is over the V2, since only the output of the comparator A2 is changed to be H L, the output of the AND gate G1 goes to be H L. At such a time, when the potential of a node V5 is over a reference voltage V4 regardless of the input signal, a comparator A6 goes to be H L and the output of an AND gate G2 is also changed to be H L. Thus, regardless of the characteristic of the input signal, the double pulse can be generated and further, an interval between the two pulses can be arbitrarily set.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a double pulse forming circuit that can stably form double pulses even at low power supply voltages.

[Conventional technology]

Conventionally, there has been a circuit of this type as shown in FIG.

FIG. 2(a) shows its circuit configuration, and FIG. 2(b) shows its operation. In FIG. 2, A1 to A4 are comparators, R1 to R5 are voltage dividing resistors for determining reference voltages v1 to v4 of the comparators A1 to A4, and G1 and 62 are AND gates.

Next, the operation will be explained. When the input signal is less than v1, comparator Al, A2. A3. The outputs of A4 are respectively, )(, L, H, and the AND game 1-Gl,
The output of G2 is shared. Next, when an input signal comes between vl and v2, comparator A3. The output of ^4 remains unchanged, but the output of comparator A1 changes from L to H, and the output from AND gate Gl changes from L to H. Next, when the input signal is between v2 and v3, the output of comparator A2 is H-
Since it becomes L, the output of AND gate G1 changes to H-L. However, comparator A3. The output of A4 remains unchanged. Next, when the input signal is between v3 and v4, the output of comparator ^3 is L-H and the output of comparator 84 remains H, so the output of AND gate G2 becomes L-H, and v
4 or more, only the output of the comparator 4 changes from H to L, so the output of the AND gate G2 changes from HL to HL.

In this way, a double pulse can be obtained as the output of AND gates G1 and G2.

[Problem that the invention seeks to solve]

Since the conventional double pulse forming circuit is configured as described above, it is not only difficult to operate when the power supply voltage is low, but also the interval t1 between the two pulses depends on the input signal, and the four values of the comparator When setting the level, there were problems such as difficulty in designing the pulse interval.

This invention was made to solve the above-mentioned problems of the conventional ones.It can operate stably even at low power supply voltages, can generate double pulses regardless of the characteristics of the input signal, and can generate double pulses regardless of the characteristics of the input signal. The object of the present invention is to obtain a double pulse forming circuit that can arbitrarily set the pulse interval.

[Means for solving problems]

The double pulse forming circuit according to the present invention creates a monotonically increasing or decreasing signal from a first pulse formed by two comparators, and compares this signal by two comparators to form a second pulse. This is how it was done. - [Operation] In this invention, the first pulse is formed by two comparators, a monotonically increasing or decreasing signal is generated in synchronization with the first pulse, and the second pulse is formed from this signal. Therefore, it is possible to operate at a lower voltage than synthesis using four comparator levels, and the delay circuit allows the interval between two pulses to be designed regardless of the characteristics of the input signal.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a double pulse forming circuit according to an embodiment of the present invention, in which 10 is a first pulse forming circuit, comparators A1. A2, the comparator A1.
＾2 reference voltage Vl, voltage dividing resistor for determining V2,
and an AND gate G1. Reference numeral 20 denotes a time constant circuit, which includes an inverter G3, a capacitor C1, a transistor for discharging the capacitor C1, and a constant current source 11. Note that the capacitor CI and the constant current source 11 constitute a delay circuit 20a using the time constant of CR. 30 is a second pulse forming circuit, and comparator A5
．． A6. The comparator A5. A6 reference voltage V3
．． Voltage dividing resistors R4 to R6 and A for determining V4
It is composed of an ND gate G2.

Next, the operation will be explained. When the input signal is below Vt, the output of the comparator A1 is high and the output of the comparator A2 is high, so the output of the AND gate G1 is active and the transistor Q1 is on. Therefore, since node v5 is at a potential lower than reference voltage v3, comparator A5
Since the output of A6 is H, the AND gate G
2 is L.

Next, when the input signal is between Vl and v2, the output of the comparator A1 changes from L to H, but since the output of the comparator A2 remains H, the output of the AND gate Gl changes to H. At this time, transistor 1 is turned off, so capacitor C1 is charged by constant current source 1, and node v5
When the potential of comparator A becomes higher than the reference voltage 73
5 becomes L-H, and 86 is still H, so AND
The output of gate G2 becomes H.

When the input signal becomes 2 or more, only the output of the comparator A2 changes to H-4L, so the output of the AND gate Gl becomes H-L. At this time, the comparator A6 becomes H-4L when the potential of the node v5 exceeds the reference voltage v4, regardless of the input signal, and the output of the AND gate G2 also changes to H-L.

From the above, the pulse interval t of AND gates Gl and G2 is t= (C1/II) ・V3 becomes.

In the above embodiment, the potential of the node v5 is obtained by charging the capacitor C1 with the constant current source 11, but a resistor may be used instead of the constant current source, and Ql may be changed to a pnp) transistor. The capacitor C1 may be connected to VCC, and the constant current source or resistor may be connected to GND, and the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the double pulse forming circuit according to the present invention, a monotonically increasing or decreasing input signal is compared with two reference voltages to form a first pulse, and
A monotonically increasing or decreasing signal is created using a time constant circuit in synchronization with the formation of the first pulse, and this is compared with two reference voltages to form the second pulse.
Double pulses can be stably obtained even when CC is low, and the interval between two pulses can also be output without depending on the input signal.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a double pulse forming circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional double pulse forming circuit. In the figure, 10 is a first pulse forming circuit, 20 is a time constant circuit, 20a is a delay circuit, 30 is a second pulse forming circuit, 11 is a constant current source, R1-R6 are resistors, A1 to A6 are comparators, G1. G2 is an AND gate, G3 is an inverter, C1 is a capacitor, and Ql is a transistor.

Claims (1)

[Claims] (1) A first pulse forming circuit that compares a monotonically increasing or decreasing input signal with first and second reference voltages using two comparators to form a first pulse; and a monotonically increasing or decreasing input signal. a time constant circuit that is created in synchronization with the formation of the first pulse; and two comparators that compare the output signals of the time constant circuit with third and fourth reference voltages to form a second pulse. A double pulse forming circuit comprising: a second pulse forming circuit.