JP2011024063A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for avoiding a malfunction when starting/stopping the semiconductor device without using any complicated circuit. <P>SOLUTION: When an ON/OFF signal VEin (150) is increased and a drain voltage of an N-channel MOS transistor M1 (110) is increased, a voltage (VDD1-VE11) indicated by a product of a drain current and a resistor R1 (111) is generated in both terminals of the resistor R1 (111). Furthermore, a voltage VE21 indicated by a product of the drain current and a resistor R2 (112) is generated in both terminals of the resistor R2 (112). Therefore, by adjusting values of the resistor R1 (111) and the resistor R2 (112), a variation amount of the signals VE11 and VE21 with respect to the VEin (150) can be adjusted. A clamp circuit 1 (120) and a clamp circuit 2 (130) protect an input section (not illustrated) of a circuit on the next stage and a clamp circuit 3 (140) protects a gate of the N-channel MOS transistor M1 (110). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technique for starting / stopping a semiconductor device without malfunctioning.

  FIG. 5 is a circuit block diagram showing a general configuration of a semiconductor device having an analog circuit. In FIG. 5, a semiconductor device 100 includes a main circuit 10 that performs signal processing, a bias circuit 20 that generates at least one of a bias voltage, a bias current, a reference voltage, or a reference current and supplies it to the main circuit 10, and an ON / OFF signal 50. In response, an ON / OFF circuit 30 for starting / stopping the bias circuit 20 and the main circuit 10 is provided. Although there are other elements such as a protection circuit among the constituent elements of the semiconductor device 100, they are omitted in FIG.

  An ON / OFF signal 30 is input to the ON / OFF circuit 30 in FIG. 5, and a signal VE1 for starting / stopping the bias circuit 20 according to the ON / OFF signal 50 and for starting / stopping the main circuit 10 Outputs signal VE2. Here, in order to prevent malfunction at the time of starting / stopping of the semiconductor device 100, the bias circuit 20 must be started before the main circuit 10 is started. When stopping, it is necessary to stop the bias circuit 20 after the main circuit 10 stops.

  FIG. 6 is a diagram illustrating a first configuration example of a conventionally known ON / OFF circuit. In the example of the ON / OFF circuit of FIG. 6, the delay circuit 31 that delays the ON / OFF signal 50 by a predetermined time and the bias circuit 20 are provided when the high voltage system (for example, 30V to 100V or more) is provided. When the voltage system is the same as the output, the level shift circuit 32 is not provided. That is, in the case of the same potential system, the ON / OFF signal 50 becomes the activation signal VE1 of the bias circuit 20 as it is and the input signal of the delay circuit 31. Further, since the ON / OFF signal 50 is given from the outside, the change speed may be slow. On the other hand, when the two potential systems are different, that is, when the potential system of the activation signal VE1 is a high voltage system, the level shift circuit 32 is required. If the level shift of the level shift circuit 32 is performed by an open collector (not shown) and a pull-up resistor (not shown), a pull-up resistor (not shown) and a parasitic capacitance (not shown) are used. The change of the start signal VE1 becomes slow with a constant. Note that, regardless of whether or not the level shift circuit 32 is provided, the ON / OFF signal 50 is a factor that gives the activation signal VE1 to the bias circuit 20. The delay circuit 31 outputs a start signal VE2 to the main circuit 10 in response to the ON / OFF signal 50 input to the delay circuit 31.

  Here, the case of activation will be described. By using a signal delayed from the activation signal VE1 of the bias circuit 20 as the activation signal VE2 of the main circuit 10, the bias circuit 20 is activated before the main circuit 10 is activated. Can do. Further, by performing similar processing (processing for delaying the other with respect to one), it is possible to stop the bias circuit 20 after stopping the main circuit 10 when stopping.

  FIG. 7 is a diagram showing a second configuration example of a conventionally known ON / OFF circuit. In the example of the ON / OFF circuit of FIG. 7, the threshold for the ON / OFF signal 50 used when generating the start signal VE1 for the bias circuit 20 is adjusted by the reference voltage Vref1 (33), and the start signal for the main circuit 10 is adjusted. The threshold for the ON / OFF signal 50 used when generating VE2 is adjusted by the reference voltage Vref2 (34). Thus, for example, when the bias circuit 20 and the main circuit 10 are H (high) enabled with respect to the start signals VE1 and VE2, the bias circuit 20 and the main circuit 10 are correctly set by setting Vref1 (33) <Vref2 (34). Can be started / stopped in order. A technique similar to this conventional technique is disclosed in Patent Document 1 below.

Japanese Patent Laying-Open No. 2005-312175 (paragraphs 0014-0015, FIGS. 1 and 2)

  However, in the method of FIG. 6 using the delay circuit 31 described above, the change in the startup VE1 signal is slow because the change speed of the ON / OFF signal 50 given from the outside is slow and the delay of the level shift circuit 32 is large. In some cases, problems may occur. For example, when the bias circuit 20 and the main circuit 10 enable H for the start signals VE1 and VE2, the threshold value of the VE1 input terminal of the bias circuit 20 is higher than the threshold value of the input terminal of the delay circuit 31, and If the time from when the OFF signal 50 reaches the threshold value of the input terminal of the delay circuit 31 until the start signal VE1 reaches the threshold value of the VE1 input terminal of the bias circuit 20 is longer than the delay time of the delay circuit 31, There is a problem that the circuit 10 starts up faster than the bias circuit 20.

  Further, in the ON / OFF circuit example of FIG. 7, a comparator dedicated to the ON / OFF circuit (comparators 35 and 36 in the illustrated example) and a reference voltage generating circuit that generates reference voltages (Vref1 (33), Vref2 (34)). Further, it is necessary to provide a bias circuit (not shown) for the comparator and the reference voltage generation circuit, which causes a problem that the circuit becomes complicated.

  Accordingly, an object of the present invention is to provide a semiconductor device that avoids a malfunction at the time of starting / stopping the semiconductor device without using a complicated circuit.

  The present invention is a semiconductor comprising a first circuit, a second circuit, and an ON / OFF circuit that outputs first and second output signals for starting / stopping the first circuit and the second circuit. In the device, the ON / OFF circuit connects the drain of the N-channel transistor and the terminal of the first resistor, connects the other terminal of the first resistor to the power supply terminal on the high potential side, and the N-channel transistor. The source of the second resistor is connected to the terminal of the second resistor, the other terminal of the second resistor is connected to the power supply terminal on the low potential side, the gate of the N-channel transistor is used as input, and the drain is used as the first output terminal. And the source is the second output terminal.

  In the ON / OFF circuit, a first clamp circuit is provided between the power terminal on the high potential side and the drain of the N channel transistor, or the source terminal of the power terminal on the low potential side and the N channel transistor is provided. A second clamp circuit is provided between them, or a third clamp circuit is provided between the power terminal on the low potential side and the gate of the N-channel transistor.

In the above, it is preferable that the first to third clamp circuits are Zener diodes.
In the semiconductor device, the first output terminal is connected to the input terminal of the first threshold adjustment circuit, and the second output terminal is connected to the input terminal of the second threshold adjustment circuit. The first output signal is obtained from the output of the first threshold adjustment circuit, and the second output signal is obtained from the output of the second threshold adjustment circuit.

  The semiconductor device is a main circuit in which one of the first circuit and the second circuit performs signal processing, and the other of the first circuit and the second circuit has at least a bias voltage applied to the main circuit. , A bias circuit for supplying one of a bias current, a reference voltage or a reference current.

  The present invention also includes a first circuit, a second circuit, and an ON / OFF circuit that outputs first and second output signals for starting / stopping the first circuit and the second circuit. In the semiconductor device, the ON / OFF circuit connects a drain of a P-channel transistor and a terminal of a first resistor, connects the other terminal of the first resistor to a power supply terminal on a low potential side, and the P-channel The source of the transistor is connected to the terminal of the second resistor, the other terminal of the second resistor is connected to the power supply terminal on the high potential side, the gate of the P-channel transistor is used as input, and the drain is used as the first output. And a source as a second output terminal.

  In the ON / OFF circuit, a first clamp circuit is provided between the low-potential-side power supply terminal and the drain of the P-channel transistor, or the high-potential-side power supply terminal and the source of the P-channel transistor are connected. A second clamp circuit is provided between them, or a third clamp circuit is provided between the power supply terminal on the high potential side and the gate of the P-channel transistor.

In the above, it is preferable that the first to third clamp circuits are Zener diodes.
The semiconductor device connects the first output terminal and the input terminal of the first threshold adjustment circuit, connects the second output terminal and the input terminal of the second threshold adjustment circuit, The first output signal is obtained from the output of the first threshold adjustment circuit, and the second output is obtained from the output of the second threshold adjustment circuit.

  The semiconductor device is a main circuit in which one of the first circuit and the second circuit performs signal processing, and the other of the first circuit and the second circuit has at least a bias voltage applied to the main circuit. , A bias circuit for supplying one of a bias current, a reference voltage or a reference current.

  In the above, it is desirable that the first and second threshold adjustment circuits are composed of inverters or buffer circuits.

  According to the present invention, the ON / OFF threshold value of each component circuit of the semiconductor device can be adjusted with a simple circuit configuration, and malfunction during start / stop can be avoided.

It is a figure which shows the basic composition of the ON / OFF circuit which concerns on this invention. It is a figure which shows the input-output voltage characteristic of the ON / OFF circuit shown in FIG. It is a figure which shows the Example with respect to the basic composition of the ON / OFF circuit shown in FIG. It is a figure which shows each part voltage characteristic of the specific circuit example shown in FIG. It is a circuit block diagram which shows the general structure of the semiconductor device which has an analog circuit. It is a figure which shows the 1st structural example of the ON / OFF circuit known conventionally. It is a figure which shows the 2nd structural example of the ON / OFF circuit known conventionally.

Hereinafter, embodiments of the present invention will be described in detail.
The semiconductor device according to the present invention receives a main circuit that performs signal processing, a bias circuit that generates at least one of a bias voltage, a bias current, a reference voltage or a reference current and supplies it to the main circuit 1, and an ON / OFF signal. And an ON / OFF circuit for starting / stopping the bias circuit and the main circuit. The basic configuration to be provided is the same as that of a general semiconductor device having the analog circuit shown in FIG. The semiconductor device according to the present invention can be used in various power supply devices such as a converter and an inverter. However, the present invention is characterized in that the above-described configuration includes an ON / OFF circuit as shown below. Hereinafter, it will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a basic configuration of an ON / OFF circuit according to the present invention. The ON / OFF circuit of FIG. 1 includes an N channel MOS (Metal Oxide Semiconductor) transistor M1 (110) and resistors R1 (111) and R2 (112). A constant current source circuit (not shown) may be used instead of the resistor R1 (111) and the resistor R2 (112). The clamp circuit 1 (120) and the clamp circuit 2 (130) in the figure are for protecting the input part (not shown) of the circuit of the next stage, and the input part (not shown) of the circuit of the next stage. ) May be removed if the pressure resistance is sufficient. The clamp circuit 3 (140) is for protecting the gate of the N-channel MOS transistor M1 (110), and may be removed if the gate breakdown voltage of the N-channel MOS transistor M1 (110) is sufficient. In the above description, the configuration using N-channel MOS transistor M1 (110) has been described. However, a configuration using P-channel MOS transistor M1 instead of N-channel MOS transistor M1 (110) may be used.

  In FIG. 1, the drain and source of an N channel MOS transistor M1 (110) are the first and second output terminals of the ON / OFF circuit, respectively, and signals (N channel) output from the first and second output terminals. The drain potential and source potential of the MOS transistor M1 (110) are VE11 and VE21.

  FIG. 2 is a diagram showing input / output voltage characteristics of the ON / OFF circuit shown in FIG. That is, FIG. 2 shows a signal VE11 and a main circuit (FIG. 5) for starting / stopping the bias circuit (see the bias circuit 20 of FIG. 5) when the ON / OFF signal VEin (150) is changed in FIG. This shows the state of the signal VE21 for starting / stopping the main circuit 10). In the ON / OFF circuit of FIG. 1, when the ON / OFF signal VEin (150) increases and the drain voltage of the N-channel MOS transistor M1 (110) increases, the voltage (shown by the product of the drain current and the resistance R1 (111)) VDD1-VE11) occurs across resistor R1 (111). In addition, a voltage (VE21) indicated by the product of the drain current and the resistance R2 (112) is generated at both ends of the resistance R2 (112). Therefore, the amount of change of the signals VE11 and VE21 with respect to VEin (150) can be adjusted by adjusting the values of the resistors R1 (111) and R2 (112). By adjusting the relationship between the signals VE11 and VE21 and the threshold value of the input section (not shown) of the next stage circuit, the ON / OFF sequence in each component circuit of the semiconductor device can be adjusted.

FIG. 3 is a diagram showing an embodiment of the basic configuration of the ON / OFF circuit according to the present invention shown in FIG. In the embodiment shown in FIG. 3, the relationship between the resistor R1 (111) and the resistor R2 (112) is adjusted so that the resistance value of the resistor R1 (111)> the resistance value of the resistor R2 (112). A first channel is formed of a P-channel MOS transistor M2 (162) receiving at its gate the signal VE11 obtained from the drain of the N-channel MOS transistor M1 (110), and a resistor 164 connected to the drain of the transistor M2 (162). Inverter circuit 160, a high-voltage side waveform shaping circuit 180 comprising a second inverter (INV) circuit whose input terminal is connected to the drain of MOS transistor M2 (162), and the source of N-channel MOS transistor M1 (110) A third inverter circuit 170 composed of an N-channel MOS transistor M3 (172) receiving the obtained signal VE21 at its gate and a resistor 174 connected to the drain of the transistor M3 (172), also of the MOS transistor M3 (172) A low-voltage side waveform shaping circuit 190 comprising a fourth inverter (INV) circuit whose input terminal is connected to the drain; Each input to the input unit of the next stage circuit (not shown) performs adjustment and waveform shaping of the threshold to the input of the next stage circuit (not shown). Here, the first inverter circuit 160 and the high voltage side waveform shaping circuit 180 constitute a high voltage side threshold adjustment circuit, and the third inverter circuit 170 and the low voltage side waveform shaping circuit 190 constitute a low voltage side threshold adjustment circuit. It is composed. The output signal VE12 of the high voltage side threshold adjustment circuit becomes the first output signal of the ON / OFF circuit, and the output VE22 of the low voltage side threshold value adjustment circuit becomes the second output signal of the ON / OFF circuit. Further, voltages VDD1 and VSS2 are supplied as power sources to the high voltage side threshold adjustment circuit, and voltages VDD2 and VSS1 are supplied as power sources to the low voltage side threshold adjustment circuit.

  Considering the case where each circuit is enabled when the ON / OFF signal VEin (150) is H, the output signal VE12 is L (= VSS2) when the ON / OFF signal VEin (150) is H. Thus, the circuit that inputs the signal VE12 as the start / stop signal is L (low) enabled. On the other hand, since the signal VE22 becomes H, the circuit that inputs the signal VE22 as the start / stop signal is H-enabled. In order to change between L enable and H enable, the high-voltage side threshold adjustment circuit has only the first inverter circuit 160, and the low-voltage side threshold adjustment circuit has only the third inverter circuit 170. do it. Alternatively, a circuit in which another inverter circuit is connected to the first inverter circuit 160 and the high voltage side waveform shaping circuit 180 is used as a high voltage side threshold adjustment circuit, and the third inverter circuit 170 and the low voltage side waveform shaping circuit 190 are already connected. A circuit to which a one-stage inverter circuit is connected may be used as a low voltage side threshold adjustment circuit. That is, the high-voltage side threshold adjustment circuit or the low-voltage side threshold adjustment circuit has a non-inverting buffer circuit or inverter configuration. In the above, the voltage value of the high-voltage power supply VDD1 (the symbol VDD1 is applied to the power supply name and its voltage value. The same applies to VDD2, VSS1, VSS2), for example, a voltage value of 30V to 100V is taken. Furthermore, it may be 30 V or less or 100 V or more. Further, as the voltage value of VSS2, for example, voltage values such as VDD1-3.3V, VDD1-5V, etc. can be taken. The voltage value of the low-voltage power supply VDD2 does not exceed the voltage value of the high-voltage power supply VDD1, but may be equal. Examples of the voltage value of the low-voltage power supply VDD2 can include 3.3V, 5V, 30V to 100V, etc., but the point is that the voltage value of the high-voltage power supply VDD1 is equal to or lower. Further, a ground voltage can be used as the voltage value of VSS1.

  FIG. 4 is a diagram showing the voltage characteristics of each part of the specific circuit example shown in FIG. As described above, the change in the signals VE12 and VE22 with respect to L / H of the ON / OFF signal VEin (150) is reversed, so that it is easy to understand that the hysteresis operation is performed. -VE12 is plotted. In this case, the threshold values VEin1 and VEin2 for the output signals VE12 and VE22 of the ON / OFF circuit of FIG. 3 are set to VEin1 <VEin2, as shown in FIG. That is, the threshold voltage of the P channel MOS transistor M2 (162) constituting the first inverter circuit 160 and the threshold voltage of the N channel MOS transistor M3 (172) constituting the third inverter circuit 170 are shown in FIG. 4 so that the signal VE12, which is the output of the high voltage side waveform shaping circuit, and the signal VE22, which is the output of the low voltage side waveform shaping circuit, have the relation shown in the lower part of FIG. By doing so, the bias circuit (see the bias circuit 20 in FIG. 5) to which the signal VE12 is input is activated before the main circuit (see the main circuit 10 in FIG. 5) to which the signal VE22 is input is activated. In addition, when the operation is stopped, the bias circuit (see the bias circuit 20 in FIG. 5) can be stopped after the main circuit (see the main circuit 10 in FIG. 5) stops.

  In FIG. 3, Zener diodes ZD1, ZD2, and ZD3 are used as the clamp circuit 1 (120), clamp circuit 2 (130), and clamp circuit 3 (140) for protecting each node. You may remove it. Further, the first inverter circuit 160 includes a P-channel MOS transistor M2 (162) and a resistor 164 connected to the MOS transistor M2 (162). Instead of the resistor 164, an N-channel MOS transistor is used. It is good also as a structure of a CMOS inverter by connecting. In this case, the threshold value of the inverter is adjusted by adjusting the sizes of the P channel MOS transistor M2 (162) and the N channel MOS transistor.

The third inverter circuit 170 is connected to the N-channel MOS transistor M3 (172) and the MO.
Although the resistor 174 connected to the S transistor M3 (172) is used, a CMOS inverter may be configured by connecting a P-channel MOS transistor instead of the resistor 174. In this case, the threshold value of the inverter is adjusted by adjusting the sizes of the N channel MOS transistor M3 (172) and the P channel MOS transistor.

  In the above description, the configuration using N channel MOS transistor M1 (110) has been described. However, a configuration using P channel MOS transistor M1 instead of N channel MOS transistor M1 (110) may be employed. This is applied to, for example, a semiconductor device driven by a negative power source having the voltage VDD1 as a reference potential (ground voltage), except that a P-channel MOS transistor M1 is used instead of the N-channel MOS transistor M1 (110). Can have the same configuration as FIG. However, it is necessary to consider the L / H of the ON / OFF signal VEin (150) in reverse to the case of FIG. For example, the change from L to H of the ON / OFF signal VEin (150) in FIG. 3 corresponds to the change from H to L when the P-channel MOS transistor M1 is used.

  In a semiconductor device in which the main circuit 10 is on the high potential side and the bias circuit 20 is on the low potential side, the relationship between the thresholds VEin1 and VEin2 shown in FIG. 4 is set to VEin1 <VEin2, and the signal VE12 is input to the main circuit 10. The signal VE22 may be input to the bias circuit. The negative logic / positive logic of the signals VE12 and VE22 are adjusted by inserting or deleting an inverter as appropriate.

  The semiconductor device of the present invention can be widely used in various semiconductor devices having analog circuits, including various power supply devices such as converters and inverters.

10 Main circuit
20 Bias circuit
30 ON / OFF circuit
100 Semiconductor devices
110 N-channel MOS transistor (M1)
111 First resistor (R1)
112 Second resistor (R2)
120 Clamp circuit 1 (ZD1)
130 Clamp circuit 2 (ZD2)
140 Clamp circuit 3 (ZD3)
150 ON / OFF signal
160 First inverter circuit
162 P-channel MOS transistor (M2)
164 resistance
170 Third inverter circuit
172 N-channel MOS transistor (M3)
174 resistance
180 High-voltage waveform shaping circuit (second inverter (INV) circuit)
190 Low voltage waveform shaping circuit (4th inverter (INV) circuit)
VDD1 High-voltage power supply or its voltage value
VDD2 Low-voltage power supply or its voltage value
VE11 High voltage side threshold adjustment circuit input signal
VE12 ON / OFF circuit first output signal
VE21 Low side threshold adjustment circuit input signal
Second output signal of VE22 ON / OFF circuit
ZD1 Zener diode
ZD2 Zener diode
ZD3 Zener diode

Claims (11)

In a semiconductor device comprising: a first circuit; a second circuit; and an ON / OFF circuit that outputs first and second output signals for starting / stopping the first circuit and the second circuit.
The ON / OFF circuit is
The drain of the N-channel transistor and the terminal of the first resistor are connected, the other terminal of the first resistor is connected to the power supply terminal on the high potential side, and the source of the N-channel transistor and the terminal of the second resistor are connected And connecting the other terminal of the second resistor to the low potential side power supply terminal, using the gate of the N-channel transistor as an input, using the drain as a first output terminal, and providing the source as the second output terminal. A semiconductor device characterized by the above.   In the ON / OFF circuit, a first clamp circuit is provided between the high-potential-side power supply terminal and the drain of the N-channel transistor, or between the low-potential-side power supply terminal and the source of the N-channel transistor. 2. The semiconductor device according to claim 1, wherein a second clamp circuit is provided, or a third clamp circuit is provided between the power terminal on the low potential side and the gate of the N-channel transistor.   3. The semiconductor device according to claim 2, wherein the first to third clamp circuits are Zener diodes.   The first output terminal is connected to the input terminal of the first threshold adjustment circuit, the second output terminal is connected to the input terminal of the second threshold adjustment circuit, and the first output terminal is connected. 2. The semiconductor device according to claim 1, wherein the first output signal is obtained from an output of a threshold value adjustment circuit, and the second output signal is obtained from an output of the second threshold value adjustment circuit. .   One of the first circuit and the second circuit is a main circuit that performs signal processing, and the other of the first circuit and the second circuit has at least a bias voltage, a bias current, and a reference voltage in the main circuit. The semiconductor device according to claim 1, wherein the semiconductor device is a bias circuit that supplies one of the reference currents. In a semiconductor device comprising: a first circuit; a second circuit; and an ON / OFF circuit that outputs first and second output signals for starting / stopping the first circuit and the second circuit.
The ON / OFF circuit is
The drain of the P-channel transistor is connected to the terminal of the first resistor, the other terminal of the first resistor is connected to the power supply terminal on the low potential side, and the source of the P-channel transistor and the terminal of the second resistor are connected And connecting the other terminal of the second resistor to the power supply terminal on the high potential side, using the gate of the P-channel transistor as an input, the drain as a first output terminal, and the source as a second output terminal. A semiconductor device comprising:   In the ON / OFF circuit, a first clamp circuit is provided between the low-potential-side power supply terminal and the drain of the P-channel transistor, or between the high-potential-side power supply terminal and the source of the P-channel transistor. 5. The semiconductor device according to claim 4, wherein a second clamp circuit is provided, or a third clamp circuit is provided between the power terminal on the high potential side and the gate of the P-channel transistor.   6. The semiconductor device according to claim 5, wherein the first to third clamp circuits are Zener diodes. The first output terminal is connected to the input terminal of the first threshold adjustment circuit, the second output terminal is connected to the input terminal of the second threshold adjustment circuit, and the first output terminal is connected. 7. The semiconductor device according to claim 6, wherein the first output signal is obtained from an output of a threshold value adjustment circuit, and the second output signal is obtained from an output of the second threshold value adjustment circuit. .   One of the first circuit and the second circuit is a main circuit that performs signal processing, and the other of the first circuit and the second circuit has at least a bias voltage, a bias current, and a reference voltage in the main circuit. The semiconductor device according to claim 6, wherein the semiconductor device is a bias circuit that supplies one of the reference currents.   10. The semiconductor device according to claim 4, wherein the first and second threshold adjustment circuits are configured by inverters or buffer circuits.

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